1. Course Introduction Purpose: Objectives: Content: Learning Time:
This course provides an overview of the Bus State Controller and the Data Transfer Controller on SH-2 and SH-2A families of 32-bit RISC microcontrollers, members of the SuperH® series
Objectives:
Gain a basic knowledge of the features and operation of the bus state controller
Learn about the features and operation of the data transfer controller
Content:
25 pages
3 questions
Learning Time:
20 minutes
Welcome to this Renesas Interactive course on the bus state controller and data transfer controller peripherals of Renesas SuperH® series microcontrollers. This information is designed to help engineers learn facts that can shorten the system development process and empower them to take full advantage of the functionality that the microcontrollers provide.
To benefit the most from this course you should be familiar with microcontrollers in general and understand the basic issues related to the design and development of embedded control systems.
In this course you will learn about the the features and operation of the bus state controller (BSC). Then you will gain some insight into how the data transfer controller (DTC) operates and what its capabilities are.

2. SuperH Peripheral Functions
Microcontrollers for embedded system applications require extensive on-chip peripherals to
Minimize system chip count
Reduce overall system cost
Facilitate small system size, etc.
Built-in peripheral functions must
Provide required capabilities
Deliver needed performance levels
Offer design flexibility
Maintain a basic commonality within product family, if possible
Offer an acceptable cost-benefit compromise, etc.
SH-2 SuperH
32-bit RISC CPU
MAC32/DSP Function
SH7047 SuperH™ Series Microcontroller
Multi-function Timer
Pulse Unit
Compare-Match
Timer
Watchdog Timer
A/D Converter
Advanced User
Debugger
Bus
Interface
FLASH
Bus State
Controller
High-performance
User Debug Interface
Clock Pulse Generator
RAM
Data Transfer Controller
Interrupt Controller
User Break
I/O
Ports
Motor Management Timer
Serial Communication
Controller Area
Network Function
Here is a block diagram of the SH bit RISC microcontroller, a member of the popular SH-2 series.
The microcontroller’s many built-in hardware functions help reduce the number of semiconductor devices in the design, minimize the overall system cost, and keep the system size small.
The peripherals in a device must provide essential functions used in key applications, deliver the requisite performance capabilities, and be flexible enough to accommodate a reasonable span of requirements.
Within a product family, the peripherals should have a degree of commonality that allows engineers to gain experience that can be applied in subsequent designs.
Finally, the peripherals must offer enough benefits to justify the cost of implementing them in the microcontroller.
With that as background, let’s now introduce the bus state controller. Later we will explain the data transfer controller.

3. SH-2 Series Bus State Controller
In SH-2 series BSCs, the address space is divided into multiple memory areas, each of which
Has its own chip select (CS) signal
Accesses internal memory as 32 bits wide, in 1 cycle
Supports connection to SRAM, DRAM, SDRAM
Can be configured individually for data bus width and number of wait states
Inserts idle cycles to eliminate contention on the data bus
Multiplexed address and data bus interfaces simplify ASIC connection
Parallel execution of external writes and internal access improves performance
Internal bus arbitrator prioritizes bus masters as shown below:
On-chip Memory
Control Unit
Bus Interface
Module Bus
Internal Bus
BRC1
BRC2
WRC1
RAMER
WAIT
CS0 RD
WRL
Wait
Area
Memory
BSC (SH7047)
The bus state controller (BSC) divides the microcontroller’s address space and provides control for various types of memory. You can then link memory types such as SRAM and ROM directly to the chip without external circuitry.
The BSC in the SH-2 series differs from the SH-2A BSC, so we will cover each product family separately, beginning with the SH-2. The address space in the SH-2 BSC is divided into four memory areas.
Each area has its own chip select (CS) signal, which can be obtained automatically from the microcontroller. We’ll look at address space format more closely in the next page.
However, be aware that the BSC accesses internal memory (RAM and ROM) as 32 bits wide and in a single cycle.
Standard interfaces on the SH-2 series support SRAM for easy connection of the microcontroller to SRAM and ROM/Flash. Additionally, first-generation SH-2 devices support DRAM interfaces with fast-page mode, while newer devices support SDRAM. All SH-2 series BSCs include a built-in refresh timer that can also function as an interval timer when the DRAM or SDRAM interface is not in use.
For flexibility in programming the interfaces, you can configure the data bus width and number of wait states one memory area at a time.
When memory access is slow, you can direct the BSC to insert idle cycles between memory locations being accessed to eliminate possible conflicts on the data bus.
To enable connection of ASICs to the microcontroller, many SH-2 series devices also support multiplexed address and data bus interfacing.
The BSC manages internal and external memory accesses in parallel to improve overall performance. For example, during a slow external memory access, the BSC might also send a fetch instruction to the fast internal memory.
Finally, the BSC is responsible for arbitrating among the various bus masters supported by the microcontroller, including the CPU, DRAM or SDRAM refresh, DMAC, DTC, and external bus request. Should any of these bus masters simultaneously request bus access, the BSC prioritizes its response in the order shown here.
BREQ > DRAM > DTC > DMAC > CPU

4. Memory Address Format 4GB space 16MB space 4MB space A31 - A24
Space selection
Not output externally; used to select the type of space as follows:
On-chip ROM space or CS space when
DRAM space when
Reserved space form to
On-chip peripheral module space or on-chip RAM for 0b
Chip Select space selection Decoded outputs /CS0 - /CS3 when
A24-A31=0b
Output address on address pins
This diagram shows the address format used in the BSC of an SH7040 series microcontroller. Other SH-2 series BSCs may have differing numbers of chip selects and pinned-out address lines, but the basic principles of operation remain the same.
As we noted earlier, SH-2 memory addresses can be as long as 32 bits. The diagram shows how the 32-bit address relates to the external world.
Address bits A0 to A21 are the only ones available on external pins, and they provide access to 4MB of memory—the typical size of a memory area.
Address bits A22 and A23 are decoded internally to provide the chip select signals.
The remaining address bits determine whether the memory address relates to DRAM/SDRAM, reserved, or on-chip peripheral space.

5. Memory Interface Examples
32-bit data-width connection
SH-2 MCU Kx8 SRAM
16-bit data-width connection
SH-2 MCU Kx8 SRAM
8-bit data-width connection
SH-2 MCU Kx8 SRAM
Here we see examples of how 32-bit-wide, 16-bit-wide, and 8-bit-wide memory can be interfaced to SH-2 series microcontrollers without the need for any glue logic. (This process also applies to SH-2A microcontrollers, as we will see later.) The BSC’s versatile design allows connection of four discrete, 8-bit-wide chips in parallel to obtain a 32-bit-wide memory area.
In examining these diagrams, observe that in the 16-bit data-width example, address A0 on the memory is connected to address A1 on the microcontroller.
In the 32-bit data-width example, address A0 on the memory is connected to A2 on the microcontroller.
The reason for these connections is that the microcontroller outputs addresses in multiples of bytes. Thus, the connection to the microcontroller must be shifted one bit to the right to get the address in 16-bit units, or shifted two bits to the right to get the address in 32-bit units.

6. Normal space basic access with software wait
Basic Bus Access
These diagrams illustrate basic methods of bus access in SH-2 or SH-2A series microcontrollers.
On the left you see that 2 states are required to perform the shortest external memory access.
On the right you see that when wait states are needed in a particular memory area, the BSC inserts them between states T1 and T2. The wait states are shown as Tw in this diagram.
Normal space basic 2-state access
Normal space basic access with software wait

7. Chip Select Insertion
CS insertion process is useful for mixing fast and slow memory devices
/CSn asserted before /RD and /WR
/RD and /WR de-selected before /CSn
There are some instances—for example, when the microcontroller is connected to an ASIC—in which a chip select signal must be asserted before an /RD or /WR signal and then de-asserted after the /RD or /WR signal.
This diagram shows how the SH-2 or SH-2A series BSC accomplishes chip-select assertion.
We will take a look at the features of the BSC in devices in the SH-2A family shortly.
Normal space /CSn period expansion

8. Quiz1

9. SH-2A Bus State Controller
Operation is similar to that of the SH-2 series BSC
External address space supports
9 memory areas of 64MB each
SRAM
Burst ROM – clocked sync and async
Multiplexed-IO (MPX-IO)
Burst MPX-IO
SDRAM
PCMCIA interface
8-, 16-, and 32-bit data bus widths, settable for each area
Wait cycle number, selectable for each area
Idle cycle insertion
Now we will turn our attention to the specifics of the SH-2A bus state controller. This version of the BSC is found on SH-2A devices and later-model SH-2 series microcontrollers, including the SH7080. Although the two generations of BSC peripherals operate in a similar fashion, certain BSC features vary from one product family to another. For example, they may differ in the number of memory areas, chip selects, and so forth.
The SH-2A BSC typically provides nine memory areas, each 64MB in size. These memory areas support standard SRAM-type devices, burst ROM, multiplexed address and data interfaces, SDRAM, and PCMCIA.
You can set the data width of each area independently to 8, 16, or 32 bits, and set individual wait states, as well.
The SH-2A BSC supports idle cycle insertion, too, as did the SH-2 BSC.

10. SH-2A BSC Features
SDRAM interface, available on 2 memory areas, supports
Multiplexed row and column addresses
Auto-refresh and self-refresh modes
Mode register set (MRS) and extended mode register set (EMRS) commands
Low frequency and power-down modes
Use of refresh timer as an interval timer
Bus arbitration allocates shared memory resources among the CPU, internal, and external bus masters
Let’s look more closely at some of the features of the SH-2A BSC.
Two memory areas support the SDRAM interface with multiplexed row and column addresses.
The BSC provides both auto- and self-refreshing modes and issues both standard mode register set (MRS) and extended mode register set (EMRS) commands.
Because many embedded systems have strict low power requirements, the SH-2A’s SDRAM interface supports low-frequency operation and power-down modes.
You may recall that the SH-2 BSC offered a refresh timer that could be used as an interval timer when the DRAM or SDRAM interface was not in use. The same is true of the SH-2A BSC. When used as an interval timer, this feature can generate a periodic interrupt tick.
The SH-2A bus state controller also arbitrates among the various bus masters in the system, as does the SH-2 BSC.

11. SH-2A Address Space Division
SH-2A further divides the 32-bit address space into
Cache-enabled areas
Cache-disabled areas
On-chip areas (RAM, peripheral modules and reserved space)
Division is defined by upper bits of address
External spaces CS0 to CS7 are cache-enabled when the internal address is A29=0
External spaces CS0 to CS7 are cache-disabled when the internal address is A29=1
The CS8 space is always cache-disabled
Likewise, the address space in the SH-2A BSC is divided into memory areas. However, the SH-2A design further divides address space into cache-enabled, cache-disabled, and on-chip areas. The on-chip areas include the on-chip memory, peripherals, and reserved areas that must not be accessed.
The address bits determine whether or not a memory address in the CS0 to CS7 spaces is cache-enabled.
If a memory location is accessed with address bit A29 cleared to 0, then this access can be cached.
However, if A29 is set to 1, then the access cannot be cached. Thus, a single physical memory location can be accessed as cached or non-cached—a strategy that is useful when multiple devices in a system must share the same memory.
Finally, note that the CS8 on-chip RAM and peripheral areas are always accessed as cache-disabled.

12. SH-2A Addressing Example
This table illustrates the previous points. It shows the addresses of the memory areas in the SH7206 microcontroller, which has an SH-2A CPU core.
As you can see, memory areas 0 through to 7 are available as both cache-enabled and cache-disabled,…
while area 8 is always cache-disabled.

13. 16-bit data-width connection
SH-2A SDRAM Interface
32-bit data-width connection
SH-2A MCU Mx16x4bank SDRAM
16-bit data-width connection
SH-2A MCU Mx16x4bank SDRAM
16-bit data-width connection
SH-2A MCU Mx16x4bank SDRAM
Here we see examples of how SDRAM can be interfaced to an SH-2A-based microcontroller without the need for any glue logic.
These diagrams are similar to the examples we saw earlier for the SH-2 series memory connections.
Again, note that the address shifts when 16-bit-wide or 32-bit-wide memory is connected to the microcontroller.
With the BSC, no glue logic is needed to make these connections, reducing part count and saving cost.
No glue logic needed!

14. SH-2A BSC PCMCIA Interface
SH-2A MCU
PC Card
(memory or I/O)
The SH-2A BSC also supports physical connection to PCMCIA-based peripherals, as illustrated in this example.
The tri-state buffers shown in the diagram are required to support the “hot-swapping” of cards — that is, the insertion and removal of memory or I/O cards while the system is powered on. This application example concludes our look at the SH-2 and SH-2A bus state controllers.
PCMCIA connection example

15. Quiz2

16. Data Transfer Controller
DTC moves the contents of memory or peripherals between locations without using the CPU core
Transfers can be requested by most peripherals, by interrupts, or by software
Transfer information is stored in RAM, so
DTC can handle a large number of data transfer channels
Number of channels is limited only by memory size, not hardware (unlike a DMAC)
One activation source can trigger a number of data transfers using DTC’s chain mode
DTC supports a wide range of transfer modes
Normal
Repeat
Block transfer
Increment or decrement source or destination
However, DTC is 3 times slower than a DMAC!
Now let’s turn our attention to data transfer controller (DTC) peripheral. The versions included in SH-2 and SH-2A devices differ slightly in their register sets, but perform identical functions. Thus, although we will restrict our discussions to the SH-2 DTC, we will still thoroughly cover the capabilities of this type of on-chip peripheral.
The DTC performs a task similar to that of a direct memory access controller (DMAC). That is, when triggered, the DTC transfers data from one memory location to another without CPU intervention. This eases the load on the CPU, freeing up processing power for applications and control tasks.
When software or another peripheral requests a data transfer, the transfer configuration information (for example, source and destination addresses) is loaded “on the fly” from RAM into the DTC. Limited only by the amount of RAM available to store the configuration information, the DTC can support many more transfer channels than can a hardware-based DMAC.
Moreover, a single activation source can trigger a series of transfers by means of the DTC’s chain mode, and the DTC supports a wide range of data transfer modes, including those listed here.
It’s important to remember that the DTC has a key disadvantage compared to a DMAC, though: The DTC’s operation produces data transfer times that are about three times longer.

17. DTC Operation To transfer data, the DTC
DTC activated by an interrupt request
To transfer data, the DTC
Is programmed to receive interrupt requests from specific external memory and peripherals (other requests are sent to CPU)
Receives an interrupt request
Loads appropriate configuration data from internal RAM
Transfers the data
Writes configuration data back to RAM
Clears source interrupt flag or sends interrupt to the CPU
Here are more details about how the DTC operates. First, you must configure the DTC to accept interrupt requests from specific external memory and peripherals.
Then, when the DTC receives an interrupt request from one of those sources, it loads the proper configuration information (stored in on-chip RAM) for that interrupt source.
You can specify the DTC’s transfer mode as normal, repeat, or block, and you can invoke the chain feature for multiple data transfers from a single source. We’ll talk more about these features later.
Next, the data transfer is made and the configuration information is written back to RAM.
The process of writing back to RAM is important because the source and destination addresses may be incremented or decremented during the data transfer and count values will change.
When the data transfer is complete, the DTC can clear the interrupt source or send the interrupt to the CPU.

18. DTC Setup
General setup is done in the DTC registers, which can be accessed directly by the CPU
Specific transfer information is stored in RAM
One block of RAM specifies a transfer
Transfer registers cannot be accessed directly by CPU; instead, transfer register contents are read from memory
Blocks are addressed from a vector table
DTC vector table
For each DTC transfer, the setup sequence must occur before the DTC can read the corresponding RAM contents
Calculation of DTC information
DTC vector table stores low-order address word (16 bits) according to interrupt source
DTBR stores the high-order address word (16 bits)
Recombining low-order and high-order words gives the 32-bit pointer to DTC register information
This page explains how to set up the DTC for a data transfer. The DTC peripheral has a number of registers that the CPU can access. These registers are used to establish which interrupts will be handled by the DTC.
The transfer configuration information is stored in RAM, as noted earlier.
The address of the RAM-based information must be loaded correctly into a vector table that resides in the DTC.
To minimize the DTC’s memory usage, this vector table stores only the lower 16-bits of each address. The upper 16-bits are stored in the DTC base register (DTBR). Recombining the two 16-bit values provides the complete 32-bit address.
It’s worth pointing out that the second-generation SH-2 DTC does not use the DTBR. It stores the complete 32-bit address in the vector-table entry.

19. Data Transfer Speed
END
Yes No
Store register
information to RAM
Next transfer?
Load register
information from RAM
Data transfer
Read DTC vector
Start
Transfer speed depends in a number of factors; in particular, the memory type (internal or external) and speed
Execution state count = vector read
+ register information R/W
+ data R/W
+ internal operation
Example of data transfer process:
On-chip RAM to I/O registers
DTC information in internal memory
Number of states = 13
(for first-generation SH-2 DTC)
This flow chart will help you visualize the data transfer process we’ve been discussing.
The overall speed of the transfer will depend on a number of factors; in particular, the type (internal or external) and speed of the memory used to store the source and destination data and the configuration information and vectors.
A transfer consists of the following actions: read vector, load register information, transfer data, and store register information (register information write-back).
This process can be written in equation form as follows:
Execution state count = vector read + register information R/W + data R/W + internal operation
This example shows the complete process of transferring data between internal RAM and a peripheral. In the first-generation SH-2 DTC, this process takes 13 states.
In the following pages, we will look more closely at some of the features and functions of the SH-2 series DTC. 62

20. DTC Configuration Information1 2 3
Register information
start address
DTMR
DTCRA
- / DTIAR / DTCRB
Register information
DTSAR
DTDAR
Chain transfer
if selected
Register information
for second transfer
in chain transfer mode
The format of the RAM-based configuration information occupies 16 bytes of memory per transfer channel.
The DTC mode register (DTMR) stores transfer mode information, including whether the source and destination address are to be incremented, decremented, or remain fixed for a transfer. DTMR also stores the transfer data width; whether the chain mode is enabled; and whether an interrupt to the CPU should be generated after the transfer.
DTC control register A (DTCRA) stores the number of transfers to be performed.
DTC initial address register (DTCIAR) stores the base address when repeat mode is used.
DTC control register B (DTCRB) contains the block length when block transfer mode is used.
DTC source address register (DTSAR) holds the source address for the transfer
DTC destination address register (DTDAR) holds the destination address.
All of this data is loaded into the DTC after the vector read, and then written back after the transfer.
4 Bytes

21. Construction of Address in RAM
DTC Information Base Register
(DTBR)
Upper 16 bits
DTC Vector Table
0x400
Lower 16 bits
DTC RAM + +
adrs:16
Start of setup table
DTMR
DTCRA
0x4B4
- / DTIAR / DTCRB
16 bytes of on-chip RAM
required for each DTC
channel
DTSAR
DTDAR
This diagram illustrates how the information-configuration address is constructed in RAM in the first-generation SH-2 series DTC.
As you read the diagram from left to right, observe that the upper 16 bits of the RAM-based configuration data are read from the DTC information base register (DTBR)…
and then combined with the lower 16 bits read from the DTC vector table, as we discussed earlier.
The resulting 32-bit address points to the RAM-based configuration information, which is automatically loaded into the DTC upon receipt of an interrupt request.
DTC
Module 32
Start of next table

22. Three Transfer Modes Normal Mode Repeat Mode Block Mode DTC (SH7047)
Register
Control
Internal Bus
CPU interrupt request source clear control
Request
Priority
External device
(memory mapped)
Bus Interface
DTC Module Bus
Bus Controller
DTMR
DTCR
DTSAR
DTDAR
DTIAR
DTER
DTCSR
DTBR
Activation
Peripheral Bus
External Bus
On-chip ROM
On-chip RAM
On-chip
Peripheral
Module
Interrupt request
External memory
DTC (SH7047)
Here is the block diagram of the DTC. You may recall from our discussion of its operation that the SH-2 series DTC supports three basic transfer modes: normal, repeat, and block, which are controlled by the DTC Mode Register (DTMR). Next we'll learn about each mode.

23. Transfers in Normal Mode
In normal mode, the DTC
Transfers one byte, word, or longword per activation
Makes 1 to 65,536 transfers
Can generate a CPU interrupt at the end of the transfer
Fixes, increments, or decrements source and destination addresses at the end of the transfer
Clears the interrupt source flag at the end of each transfer
Transfer
Source
Address
Register
(SAR)
Destination
(DAR)
In the normal mode each interrupt received from a peripheral initiates a transfer of data in the form of a single byte, word, or longword unit. This initiation process is called transfer activation.
The DTC can make up to 65,536 transfers with the requesting peripheral and can generate an interrupt for the CPU at the end of the transfer sequence.
It’s worth noting that when the DTC is used in normal mode and, for example, is set for 100 transfers, then you must generate 100 triggers to complete those transfers. This is because the DTC makes only one transfer per request.
At the end of every transfer, the DTC can increment or decrement both, either, or neither of the source and destination addresses.
Also, the DTC can automatically clear the interrupt flag associated with the source of the transfer request so that the CPU does not have to intervene in the transfer process.

24. Transfers in Repeat Mode
In repeat mode, the DTC
Transfers a byte, word, or longword per activation
Makes 1 to 256 transfers
Can generate a CPU interrupt at the end of the transfer
Can increment or decrement the source and destination addresses
Restores the SAR or DAR and transfer count registers to their initial values at the end of the transfer
Transfer
SAR or
DAR
In general, DTC operation in repeat mode is similar to operation in normal mode. The main difference is that in repeat mode either the source or the destination address is reset back to its original value at the end of the specified number of transfers.
In repeat mode the DTC transfers a byte, word, or longword per activation and makes from 1 to 256 transfers.
It can generate a CPU interrupt at the end of the transfer and can increment or decrement the source and destination addresses.
At the end of the transfer, it restores the SAR or DAR and transfer count registers to their initial values.

25. Transfers in Block Mode
In block mode, the DTC
Transfers one block of data per activation
Designates either destination or source as the block area
Specifies block length of 1 to 65,536
Makes 1 to 65,536 block transfers
Restores initial values of address register for block area and block size counter at the end of the transfer
Transfer
SAR or
DAR
First block
nth block
Block area
In contrast to the normal and repeat modes, in which a single DTC trigger (interrupt or activation) initiates a single transfer…
in block mode one trigger initiates the transfer of a block of data.
The block size can be anywhere from 1 to 65,536 units (bytes, words or longwords) and the DTC can transfer up to 65,536 blocks.
At the end of the block transfer, the DTC can automatically reset the address for either the source or the destination block.

26. Chain Transfers Chain transfer enables the DTC to
Make a number of data transfers consecutively in response to a single transfer request
Make transfers using different modes
DTC vector
address
Register information start address
Register information CHNE=1
Register information CHNE=0
Source
Destination
Having covered the basic transfer modes, let’s now explore a special case: chain transfer. If you want a single activation source to trigger multiple, consecutive data transfers, you can use the DTC’s chain transfer feature.
When chain transfer is activated, the DTC first performs a data transfer as usual. When that transfer is complete, the DTC tests the chain bit, CHNE.
If this bit is set to 1 in the DTMR register, the DTC automatically loads the next block of RAM-based configuration data and performs the next transfer.
You can specify different transfer modes for the various transfers during this process.
The process continues until the DTC reaches a DTMR with the CHNE bit set to 0.
That ends the chain transfer.

27. Quiz3

28. Course Summary Bus state controller Data transfer controller
This concludes this course on the bus state controller and data transfer controller built into the RISC microcontrollers in the SH-2 and SH-2A series.
In this course you learned that the BSC divides up the address spaces, provides control for various types of memory, and enables memory such as SRAM and ROM to be linked directly to the microcontroller without external circuitry.
You also discovered that the DTC provides many flexible channels for data transfer between memory and peripherals, that it is slower than a DMAC, and that it relieves the load on the CPU so that the execution speed of control tasks and applications can be maximized.
Thank you for your interest in Renesas microcontrollers. We now invite you to take other courses that introduce the SH-2 and the SH-2A series. We also encourage you to take advantage of the many additional free resources available at the Renesas Interactive Web site.