1. 29th Oct
Review Session 8

2. Sequential Circuit Design Counters
Outline
Sequential Circuit Design
Counters

3. Exercise 1
1. Design a sequential circuit for verifying parity in a stream of bits. An even parity means that there are even number of 1s observed so far in the bit stream and an odd parity means that there are odd number of 1s observed in the bit stream so far. The sequential circuit will take a single bit X as input and generates an output bit Y to indicate the odd parity. In other words, the generated output is 1 if and only if the the total number of 1s seen so far are odd. Here is an example of the output sequence generated for the given input - Sample input: Sample output: Draw the state diagram. Label each arc with X/Y. Label the initial state with A and other states with B, C, D, etc. as required. Explain the purpose of each state. Use the minimum number of states.

4. Exercise 1
1. Sample input: Sample output: a. Draw the state diagram. Label each arc with X/Y. Label the initial state with A and other states with B, C, D, etc. as required. Explain the purpose of each state. Use the minimum number of states.

5. Exercise 1 (solution) 1. Sample input: 0 0 1 0 1 0 1 1 0 0 1 0 0 0
Sample output:
Draw the state diagram. Label each arc with X/Y. Label the initial state with A and other states with B, C, D, etc. as required. Explain the purpose of each state. Use the minimum number of states.

6. Sequential Circuit Design
Step 1: Make a state table based on the problem statement. The table should show the present states, inputs, next states and outputs. (It may be easier to find a state diagram first, and then convert that to a table.) Step 2: Assign binary codes to the states in the state table, if you haven’t already. If you have n states, your binary codes will have at least log2 n digits, and your circuit will have at least log2 n flip-flops. Step 3: For each flip-flop and each row of your state table, find the flip-flop input values that are needed to generate the next state from the present state. You can use flip-flop excitation tables here. Step 4: Find simplified equations for the flip-flop inputs and the outputs. Step 5: Build the circuit!

7. Exercise 2
Fill in the state table from the state diagram below, including flip-flop input values, assuming a JK flip-flop will be used..

8. Example – Step 1: State Table

9. Example – Step 2: Assign Binary Codes

10. Example – Step 3: Find FF inputs
Excitation Table

11. Example – Step 3: Find FF inputs
Excitation Table

12. Example – Step 4: Find simplified equations
J1 = Q0X'         K1 = Q0X
J0 = X               K0 = Q1’X' + Q1X = Q1 XNOR X

13. Example – Step 5: Build the circuit
J1 = Q0X'         K1 = Q0X
J0 = X               K0 = Q1’X' + Q1X = Q1 XNOR X

14. Summary (Course Slide)
Counters serve many purposes in sequential logic design.
There are lots of variations on the basic counter.
Some can increment or decrement.
An enable signal can be added.
The counter’s value may be explicitly set.
There are also several ways to make counters.
You can follow the sequential design principles from last week to build counters from scratch.
You could also modify or combine existing counter devices.
Counters

15. More complex counters (Course Slide)
More complex counters are also possible. The full-featured LogicWorks Counter-4 device below has several functions.
It can increment or decrement, by setting the UP input to 1 or 0.
You can immediately (asynchronously) clear the counter to 0000 by setting CLR = 1.
You can specify the counter’s next output by setting D3-D0 to any four-bit value and clearing LD.
The active-low EN input enables or disables the counter.
When the counter is disabled, it continues to output the same value without incrementing, decrementing, loading, or clearing.
The “counter out” CO is normally 1, but becomes 0
when the counter reaches its maximum value, 1111.
Counters

16. Exercise 3
2. The counter that will change the output order instead of overflowing / underflowing so that it counts up to 1110 and then back to 0 and repeat this whole process again and again, i.e. the counting output sequence is 0000, 0001, 0010, ..., 1101, 1110, 1101, 1100, ..., 0010, 0001, 0000, 0001, ...

17. Exercise 3 (solution)
2. The counter that will change the output order instead of overflowing / underflowing so that it counts up to 1110 and then back to 0 and repeat this whole process again and again, i.e. the counting output sequence is 0000, 0001, 0010, ..., 1101, 1110, 1101, 1100, ..., 0010, 0001, 0000, 0001, ...