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Project Owyhee Digital Lock
Team Jessica Rice Julie Barton-Smith Cory Johnson Advisor Dr. Inan, Dr. Osterberg Industry Representative Mr. Wes Mickanin November, 2005 University of Portland School of Engineering
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Overview Introduction Scorecard Additional Accomplishments Plans
Issues/Concerns November, 2005 University of Portland School of Engineering
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Introduction Digital lock Block Diagram On MOSIS chip
Keypad entry with key override Block Diagram November, 2005 University of Portland School of Engineering
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Introduction ctd. November, 2005
University of Portland School of Engineering
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Scorecard Establish Testing Protocol Test Logic & Debug Logic Design
Series of 6 tests Right and Wrong Codes Door Open 2 Wrongs Make a Right Test Logic & Debug Logic Design Ran Command File It Worked! November, 2005 University of Portland School of Engineering
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Scorecard ctd. Begin Design of Macro-model Update Website
Discussed Using CPLD’s Use 6 Functional Blocks Update Website Formalize Project Plan Change Request Approved November, 2005 University of Portland School of Engineering
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Additional Accomplishments
Acquired electric latch and door knob Sent in chip 2 days early Teleconferenced with Dr. Osterberg November, 2005 University of Portland School of Engineering
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Plans Finish designing macro-model Design Approval Meeting Order Parts
November, 2005 University of Portland School of Engineering
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Integrate with Macro Model
Milestones Number Description Original Previous Present 1 Product Approval 2 Plan Approval 3 Design Release 4 Chip out 5 Macro Model Built 6 Lock Built 7 TOP's Approval 8 Integrate with Macro Model 9 Integrate with Chip 10 Prototype Release 11 Founder's Day 12 Final Report November, 2005 University of Portland School of Engineering
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Concerns/Issues Hardware Interface with MOSIS Chip Re-Learning ABEL
Not Being in Same State Over Break November, 2005 University of Portland School of Engineering
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Conclusions Introduction Scorecard Additional Accomplishments Plans
On Chip Digital Lock Scorecard All finished except Macro-model Design Additional Accomplishments Sent Out Chip Early Plans Macro-model Issues/Concerns Interfacing with chip November, 2005 University of Portland School of Engineering
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Questions? November, 2005 University of Portland School of Engineering
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