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Energy Efficient Computing in Nanoscale CMOS

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Presentation on theme: "Energy Efficient Computing in Nanoscale CMOS"— Presentation transcript:

1 Energy Efficient Computing in Nanoscale CMOS
Vivek De Intel Fellow Director of Circuit Technology Research Intel Labs

2 Internet of Everything (IoE)

3 Moore’s Law scaling

4 Dynamic platform control

5 Near Threshold Voltage (NTV) computing

6 NTV IA processor

7 NTV design techniques

8 NTV IA – powered by solar cell!

9 Power performance measurements

10 Power components

11 Minimum energy operation

12 NTV and variability

13 Voltage-frequency margins

14 Dynamic adaptation & reconfiguration

15 Dynamic V & F adaptation

16 Resilient platforms

17 Resilient & adaptive core

18 Performance & efficiency gains

19 Integrated voltage regulators

20 Fully integrated VR

21 Energy efficient interconnects

22 Memory capacity & bandwidth

23 Efficient & scalable neuromorphic systems

24 Efficient & scalable neuromorphic architecture

25 Efficient information encoding

26 Information capacity scaling

27 Sparsity vs. efficiency

28 Neuron models & building blocks

29 Neurosynaptic plasticity for learning

30 Multiple learning modes via spike timing

31 Multi-scale synaptic plasticity

32 Efficient & scalable neurosynaptic network

33 Distributed memory + compute

34 Neuromorphic computing futures

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