1. I/O system

2. High-level subsystems
Application
File System
Virtual
memory
Management
I/O System Interface
I/O System
Block device interface
Open/close
Read/write
Stream device interface
Open/close get/put io_control
Network interface
Open/close read/write send/receive
Block-oriented
device management
Stream-oriented
device management
Network communication
software
Device independent software
CD-ROW
Driver
Hard disk
drive …
Keyboard
driver
Printer
driver …
Network
driver …
Device dependant software
SW/HW interface
Low-level subsystems
CD-ROW
controller
Hard disk
controller …
Keyboard
controller
Printer
controller …
Network
controller …
HW controls
devices
::::::::::

3. Device Controller Interface
write
read
read/write
opcode register
operand registers
busy register
status register
data buffer
Controller
Device
Driver
Describes the operation which the driver wants the controller to carry out
Indicates if controller is busy and that it cannot accept any new requests
(boolean value)
Indicates a ‘completed operation’ report to the driver
Transfers data to and from the device

4. Explicit Device Interface Memory-mapped Interfaces
vs.
Main Memory
Main Memory
n -1
n -1
Extension of Main Memory
Controllers
dev_0
opcode register
operand registers
dev_0
opcode register
operand registers
dev_1
dev_1
opcode register
operand registers
opcode register
operand registers
dev_n
dev_n
2 different types of instructions used to address Main Memory and Device
Same format of instructions used to address Main Memory and Device

5. Programmed Input/Output with polling
Controller
opcode register
operand registers
busy register
status register
data buffer 2
CPU writes opcode for input operation; controller executes; flag set to busy 1
CPU writes operands required for input in operand registers
Device
busy 4
CPU 5
After operation completes CPU checks status register for problems 3
Data transferred from device to data buffer 6
If no errors found, CPU transfers data from data buffer to Main Memory
Main Memory 4
During data transfer in 3, CPU polls controller by testing busy flag

6. Programmed Input/Output with Interrupts
Controller
opcode register 2
CPU writes opcode for input operation; controller executes; flag set to busy
operand registers 1
CPU writes operands required for input in operand registers
Control Logic 4
Operation complete, controller issues interrupt; running pr. suspends & waiting pr. resumes
Device
busy register
busy
CPU
status register 5
Resumed process checks status register for problems
data buffer 6
If no errors found, process transfers data from data buffer to Main Memory 3
Data transferred from device to data buffer
Main Memory

7. Direct Memory Access I/O (DMA)
CPU overhead is high in fast devices.
DMA reduces the CPU overhead in initiating and monitoring individual data transfer between device and main memory.
Controller
opcode register
operand registers
busy register
status register
data buffer 2
CPU writes opcode for input operation; controller executes; flag set to busy 1
CPU writes operands required for input in operand registers
Control Logic 5
After operation completes, controller resets busy flag to 0 and sends interrupt to CPU
Device
busy
CPU 6
CPU reads status register to check for successful operation 3
Data transferred from device to data buffer 4
Controller copies data between main memory and data buffer; (repeated)
Main Memory

8. DMA – CPU Cycle Stealing
Memory
Device
CPU
CTL 1