1. TAO1221 COMPUTER ARCHITECTURE AND ORGANIZATION LAB 3 & 4 Part 2
Prisha Palpunavam
Postgraduate Lab 2 FIST (PG LAB 2)

2. INSTRUCTION SET OF 8085
8085 instructions can be classified into several groups: 1. Data Transfer (Copy Operation) 2. Arithmetic 3. Logical and Bit manipulation 4. Branch 5. Machine Control (Input/Output)

3. Logic Gates

4. 3. Logical and Bit Manipulation Operations Instruction Set

5. 3.1 Logical and Bit Manipulation (AND Operation) Instruction Set
ANA E Perform AND operation to data stored in accumulator and to data stored in register E. Assuming, accumulator holds data 44H and register E holds data 34H. Upon executing ANA E, accumulator will hold 04H as a result.
ANA M Perform AND to the contents stored in memory location whose address is loaded in HL with accumulator. Assuming accumulator holds 54H and HL register contains 3000H and the data in 3000H is 82H. Upon executing ANA M, accumulator will hold 00H.

6. 3.1 Logical and Bit Manipulation (AND Operation) Instruction Set
ANI 89H Perform AND immediate to data stored in accumulator and store result in accumulator. Assuming, accumulator holds data A8H. Upon executing ANI 83H, accumulator will hold 80H as a result.

7. 3.2 Logical and Bit Manipulation (OR Operation) Instruction Set
ORA C Perform OR operation to data stored in accumulator and to data stored in register C. Assuming, accumulator holds data A7H and register C holds data 6EH. Upon executing ORA C, accumulator will hold 04H as a result.
ORA M Perform OR to the contents stored in memory location whose address is loaded in HL with accumulator. Assuming accumulator holds FOH and HL register contains 3000H and the data in 3000H is 0FH. Upon executing ORA M, accumulator will hold FFH.

8. 3.2 Logical and Bit Manipulation (OR Operation) Instruction Set
ORI 8FH Perform OR immediate to data stored in accumulator and store result in accumulator. Assuming, accumulator holds data 3AH. Upon executing ORI 8FH, accumulator will hold BFH as a result.

9. 3.3 Logical and Bit Manipulation (Exclusive-OR Operation) Instruction Set
XRA C Perform X-OR operation to data stored in accumulator and to data stored in register C. Assuming, accumulator holds data F7H and register C holds data 89H. Upon executing XRA C, accumulator will hold 7EH as a result.
XRA M Perform X-OR to the contents stored in memory location whose address is loaded in HL with accumulator. Assuming accumulator holds F2H and HL register contains 3000H and the data in 3000H is 23H. Upon executing XRA M, accumulator will hold D1H.

10. 3.2 Logical and Bit Manipulation (Exclusive-OR Operation) Instruction Set
XRI FEH Perform X-OR immediate to data stored in accumulator and store result in accumulator. Example, accumulator holds data 88H. Upon executing XRI FEH, accumulator will hold 76H as a result.

11. 3.3 Logical and Bit Manipulation (Compare Operation) Instruction Set
CMP B Compare contents of register B with contents of accumulator. The comparison is done by subtracting contents of B and accumulator. Comparison is shown by using the flags below:
If [A] < [B], carry = 1 and zero = 0;
If [A] = [B], carry = 0 and zero = 1;
If [A] > [B], carry = 0 and zero = 0;

12. 3.3 Logical and Bit Manipulation (Compare Operation) Instruction Set
CMP M Compare the contents stored in memory location whose address is loaded in HL with accumulator. Assuming accumulator holds 57H and HL register contains 3000H and the data in 3000H is 62H. Upon executing CMP M, accumulator will hold 9DH meeting criteria, If [A] < [B], carry flag is set and zero flag is reset.
CPI 9EH Compare the contents in register D immediately with accumulator. Assuming register D holds 62H, perform 2s complement and compare to accumulator by executing CPI 9EH. Condition met is [A] = [B], carry flag is reset and zero flag is set.

13. 3.4 Logical and Bit Manipulation (Complement Operation) Instruction Set
CMA Finds 1s complement (invert each bit) of the data loaded in accumulator. Example, accumulator holds data of 4FH. Upon executing CMA, accumulator will hold B0H.
STC Setting carry flag = 1.
CMC Complement carry flag. Assuming carry =1, after executing CMC the carry flag = 0.

14. 3.5 Logical and Bit Manipulation (Rotate Operation) Instruction Set
RLC Rotate A left. Each binary bit of the accumulator is rotated left by one position. Assuming register A holds A7H. After executing RLC, accumulator will hold 4FH.
RRC Rotate A right. Each binary bit of the accumulator is rotated right by one position. Assuming register A holds A7H. After executing RRC, accumulator will hold D3H.
RAL Each binary bit of the accumulator is rotated left by one position through the carry flag.

15. 3.5 Logical and Bit Manipulation (Rotate Operation) Instruction Set
RAR Rotate accumulator right through carry Each binary bit of the accumulator is rotated right by one position through the carry flag. Assuming register A holds A7H. After executing RAR, accumulator will hold 53H.
RRC Rotate A right. Each binary bit of the accumulator is rotated right by one position. Assuming register A holds A7H. After executing RRC, accumulator will hold D3H.

16. 4. Branching Operations Instruction Set

17. 4.1 Branching (Jump Operation) Instruction Set
JMP The program sequence is transferred to the memory location specified by the 16-bit address. The 16-bit address of the operand is entered in memory in reverse order, the low-order byte first, followed by the high-order byte.
PCHL Copy the H and L register contents to program counter. The contents of H are placed as a high-order byte and of L as a low-order byte.

18. 4.1 Branching (Jump Operation) Instruction Set
Jcond Jump to the given address if a specified condition is satisfied. The conditions could be:
JC Jump on Carry CY=1
JNC Jump on No Carry CY=0
JP Jump on Positive S=0
JM Jump on Minus S=1
JPE Jump on Parity Even P=1
JPO Jump on Parity Odd P=0
JZ Jump on Zero Z=1
JNZ Jump on No Zero Z=0

19. 4.1 Branching (Jump Operation) Instruction Set
QUESTION: An Assembly Language Program to arrange an array of 4 data (04H,04H, 02H,01H, 03H) in ascending order using 8085? *Value in red is Array Size.
1)      Initialize HL pair as memory pointer.
2)      Get the count at 4200 in to C register.
3)      Copy it in D register.
4)      Get the first value in Accumulator.
5)      Compare it with the value at next location.
6)      If they are out of order, exchange the contents of accumulator and
memory.
7)      Decrement D register’s content by 1.
8)      Repeat steps 5 and 7 till the value in D register become zero.
9)      Decrement C register’s content by 1.
10)  Repeat steps 3 to 9 till the value in C register becomes zero.
11)  Terminate the program.

20. 4.2 Branching (Subroutine Operation) Instruction Set
CALL Call unconditionally a subroutine at the address given. This pushes the current PC contents onto the stack and loads the given address onto the PC; thus, the CPU jumps to the given address. The stack pointer is decremented by two.

21. 4.2 Branching (Subroutine Operation) Instruction Set
Ccond Call the subroutine at the given address conditionally. The subroutine at the given address if a specified condition is satisfied. The Stack Pointer is decremented by two.
CC Jump on Carry CY=1
CNC Jump on No Carry CY=0
CP Jump on Positive S=0
CM Jump on Minus S=1
CPE Jump on Parity Even P=1
CPO Jump on Parity Odd P=0
CZ Jump on Zero Z=1
CNZ Jump on No Zero Z=0

22. 4.2 Branching (Subroutine Operation) Instruction Set
QUESTION: An Assembly Language Program to get the factorial of given number, 06H at memory location address 4500H.

23. 4.2 Branching (Subroutine Operation) Instruction Set
RET Return from subroutine unconditionally. The program sequence is transferred from the subroutine to the calling program. The two bytes from the top of the stack are copied into the program counter and the program execution begins at the new address.

24. 4.2 Branching (Subroutine Operation)
Rcond Return from the subroutine conditionally. This instruction returns the control to the main program, if the specified condition is satisfied. The changes of PC and SP are the same as in an unconditional RET:
RC Jump on Carry CY=1
RNC Jump on No Carry CY=0
RP Jump on Positive S=0
RM Jump on Minus S=1
RPE Jump on Parity Even P=1
RPO Jump on Parity Odd P=0
RZ Jump on Zero Z=1
RNZ Jump on No Zero Z=0

25. 5. Machine Control Instruction Set

26. 5.1 Stack Operations and Machine Control Related Instruction Set
IN 45H Input data to accumulator from a port with 8-bit address. Assuming port 45h contains FFH, upon executing IN 45H accumulator will hold FFH data.
OUT 45H Output data from accumulator to a port with 8-bit address. Assuming accumulator contains 33H, upon executing OUT 78H accumulator will hold 33H data.

27. 5.2 Stack Operations and Machine Control Related Instruction Set
PUSH B Push register pair (BC/DE/HL)onto the stack. The stack pointer register is decremented and the contents of the high-order register (B/D/H) are copied into that location. The stack pointer register is again decremented and the contents of the low-order register (C/E/L) are copied to that location.
PUSH PSW Push program status word onto stack. PSW is the Program Status Word; PUSH operation, SP is decremented and the high-order byte (A) is copied onto the location pointed to by Stack Pointer; SP is again decremented and the low-order byte (Flag Register) is copied onto the location pointed to by SP.

28. 5.2 Stack Operations and Machine Control Related Instruction Set
POP B Pop register pair (BC/DE/HL) out off the stack. The contents of the memory location indicated by the stack pointer register are copied into the low-order register (C/E/L), and then the stack pointer register is incremented by 1. The contents of the next memory location are copied into the high-order register (B/D/H) and the stack pointer register is again incremented by 1.

29. 5.2 Stack Operations and Machine Control Related Instruction Set
POP PSW Pop off stack to Program Status Word (Accumulator and Flag register). It copies the contents of the location pointed to by SP onto the low-order byte of the PSW (Flag register), increments SP, and copies the contents of the location pointed to by SP onto the high order byte of the PSW (accumulator). SP is again incremented by one.

30. 5.2 Stack Operations and Machine Control Related Instruction Set
XTHL Exchange top of the stack with H
and L registers. The contents of the L register are exchanged with the stack location pointed out by the contents of the stack pointer register. The contents of the H register are exchanged with the next stack location (SP+1).
SPHL Copy H and L registers to the stack pointer. This instruction copies the contents of HL onto the stack pointer register. H provides the high-order byte of the address while L provides the low-order byte of the address. The contents of the H and L registers are not altered.

31. LAB 4-DISCUSSION

32. 2. What is the function of condition codes in CPU?
Condition codes are bits set by the CPU hardware as the result of operations. For example, an arithmetic operation may produce a positive, negative, zero, or overflow result. In addition to the result itself being stored in a register or memory, a condition code is also set. The code may subsequently be tested as part of a conditional branch operation.
Operand – data to be operated on

33. 4. List and briefly explain various ways in which an instruction pipeline can deal with conditional branch instructions.
Multiple streams: A brute-force approach is to replicate the initial portions of the pipeline and allow the pipeline to fetch both instructions, making use of two streams. Pre-fetch branch target: When a conditional branch is recognized, the target of the branch is pre-fetched, in addition to the instruction following the branch. This target is then saved until the branch instruction is executed. If the branch is taken, the target has already been pre-fetched. Loop buffer: A loop buffer is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions, in sequence. If a branch is to be taken, the hardware first checks whether the branch target is within the buffer. If so, the next instruction is fetched from the buffer. Branch prediction: A prediction is made whether a conditional branch will be taken when executed, and subsequent instructions are fetched accordingly. Delayed branch: It is possible to improve pipeline performance by automatically rearranging instructions within a program, so that branch instructions occur later than actually desired.
Operand – data to be operated on

34. 5. If the last operation performed on a computer with an 8-bit word was an addition in which the two operands were and , what would be the value of the following flags? Carry Zero Overflow Sign Even Parity Half-Carry
Operand – data to be operated on

35. 5. If the last operation performed on a computer with an 8-bit word was an addition in which the two operands were and , what would be the value of the following flags? _________   Carry = 0; Zero = 0; Overflow = 0;  is set to 1 when there is a signed overflow/ If the result is not in ( -128 to +127) range. Sign = 0; Even parity = 1; Half-carry= 0;
Operand – data to be operated on

36. END OF LAB 3 & LAB 4 (Part 2)