1. SPARC’s INTEGER uNIT
By Teddy Mopewou

2. Introduction
SPARC : a scalable processor architecture consists of a 32 bit integer unit, an IEEE-standard floating point unit and a user defined co-processor unit
Each unit has its own set of registers enabling maximum concurrency between units
Architecture assumes a linear, 32-bit virtual address space for user application programs

3. Design goals
Define a very simple yet efficient architecture that could be implemented cost effectively in various technologies, where some of them could be faster and possibly less dense
Support for high level languages and keeping compilers relatively simple

4. 2. Integer UNIT
SPARC defines 55 basic integers instructions and their variations
Instructions include a comprehensive set of logical, arithmetic, control transfer, memory reference and multiprocessor instructions
Support for AI languages is provided through tagged arithmetic instructions

5. 2.1 registers
SPARC is a register intensive architecture where a large bank of registers is divided into two sets of overlapping registers known as windows
Architecture defines up to 32 windows. The number may vary across implementations
The IU may contain from 40 to 520 registers
Each window consists of 32 registers further divided into 8 global registers (same for all windows), 8 ins, 8 locals (unique to each window), and 8 outs.
Adjacent windows share 8 registers (out-ins)

7. 2.2 instructions
All the spare instructions are 32 bits wide and are defined by one of the three formats namely
The call instruction with a 30 bit word displacement
SETHI and branch instructions which defines a 22-bit immediate field
A “format 3” that encodes the remaining instructions including floating point and co-processor instructions.

9. 2.2.1 Memory reference instructions
Memory can be accessed only through load/store instructions, including floating point and co-processor load/stores, the IU generates the memory address and the IU, FPU or co- processor sources or sinks the data

10. 2.2.2 Multiprocessor instructions
SWAP and load-store instructions provide support for tightly coupled multiprocessors
SWAP exchanges the contents of an IU register with a word from memory. It can be used in conjunction with a memory- mapped co-processor to implement synchronizing instructions such as the non-blocking “fetch and add” instructions
LDSTUB reads a byte from memory into an IU register and then rewrites the same byte in memory to all ones. It can be used for blocking synchronization schemes, such as semaphores

11. 2.2.3 Arithmetic/logical instructions
These format 3 integer instructions perform either a logical or an arithmetic operation on two operands and optionally write the result into a destination register
Arithmetic instructions have two types: Ones that update the integer condition codes and ones that do not.
There are four condition codes, negative(N), zero (Z), overflow(V) and carry (C). They are stored in the processor state register

12. 2.2.4 Tagged instructions
These instructions provide support for languages that can benefit from operand tags, such as LISP and Smalltalk. They assume 30-bit left justified signed integers and use least significant two bits of a word as a tag. The tag add/substract instructions set the overflow condition code bit if either of the operand has a non zero tag.
Two variants, TADDccTv and TSUBccTv, trap if the overflow bit has been set and can be used to detect operand type errors

13. 2.2.5 Special instructions
These instructions are used to read and write architecturally defined registers. Some of them are privileged and can be executed only in the supervisor mode
SAVE and RESTORE instructions are used to decrement or increment the current window pointer
They also operate like an ordinary ADD instruction and thus can also be used to automatically adjust a program stack pointer

14. 2.2.6 Control transfer instructions
These instructions consist of call, branch, jump and link and trap condition code instructions.
SPARC uses the concept of delayed branches.
For most of these instructions the instruction that follows the control transfer instruction is executed before program control is transferred to the target instruction

15. References
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IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std , IEEE, New York, NY, 1985.
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S. Muchnick [1988]. “Optimizing Compilers for SPARC”, Sun Technology, sum- mer 1988, pp ; also appeared in W. Stallings (ed.), Reduced Instruc- tion Set Computers (2nd edition), IEEE Computer Society Press, 1990, pp , and M. Hall and J. Barry (eds.), The Sun Technology Papers, Springer- Verlag, 1990, pp
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