1. Hardware building blocks in detail
Prof. Giancarlo Succi, Ph.D., P.Eng.

2. Gates and Boolean Algebra
The symbols and functional behavior for the five basic gates.
Prof. G. Succi, Ph.D., P.Eng.

3. Boolean Algebra
(a) The truth table for the majority function of three variables.
(b) A circuit for (a).
(b)
Prof. G. Succi, Ph.D., P.Eng.

4. Implementation of Boolean Functions
Write truth table for function
Provide inverters to generate complement of each input
Draw AND gate for each term with 1 in result column
Wire AND gates to appropriate inputs
Feed output of all AND gates into an OR gate
Prof. G. Succi, Ph.D., P.Eng.

5. Circuit Equivalence (1)
Construction of (a) NOT, (b) AND, and (c) OR gates using only NAND gates or only NOR gates.
Prof. G. Succi, Ph.D., P.Eng.

6. Circuit Equivalence (2)
Two equivalent functions.
Prof. G. Succi, Ph.D., P.Eng.

7. Circuit Equivalence (3)
Two equivalent functions.
Prof. G. Succi, Ph.D., P.Eng.

8. Circuit Equivalence (4)
Some identities of Boolean algebra.
Prof. G. Succi, Ph.D., P.Eng.

9. Exercise 1 Derive the Boolean expression for this circuit
Then, simplify it and redraw the circuit
Prof. G. Succi, Ph.D., P.Eng.

10. Solution
Prof. G. Succi, Ph.D., P.Eng.

11. Exercise 2
Suppose we were given the task of designing a flame detection circuit for a toxic waste incinerator. The intense heat of the fire is intended to neutralize the toxicity of the waste introduced into the incinerator. Such combustion-based techniques are commonly used to neutralize medical waste, which may be infected with deadly viruses or bacteria:
Prof. G. Succi, Ph.D., P.Eng.

12. Exercise 2
As long as a flame is maintained in the incinerator, it is safe to inject waste into it to be neutralized.
If the flame were to be extinguished, however, it would be unsafe to continue to inject waste into the combustion chamber, as it would exit the exhaust un-neutralized, and pose a health threat to anyone in close proximity to the exhaust.
What we need in this system is a sure way of detecting the presence of a flame, and permitting waste to be injected only if a flame is "proven" by the flame detection system.
Prof. G. Succi, Ph.D., P.Eng.

13. Exercise 2 Several different flame-detection technologies exist:
optical (detection of light),
thermal (detection of high temperature), and
electrical conduction (detection of ionized particles in the flame path),
each one with its unique advantages and disadvantages.
Suppose that due to the high degree of hazard involved with potentially passing un-neutralized waste out the exhaust of this incinerator, it is decided that the flame detection system be made redundant (multiple sensors), so that failure of a single sensor does not lead to an emission of toxins out the exhaust.
Prof. G. Succi, Ph.D., P.Eng.

14. Exercise 2
Each sensor comes equipped with a normally-open contact (open if no flame, closed if flame detected) which we will use to activate the inputs of a logic system:
Prof. G. Succi, Ph.D., P.Eng.

15. Exercise 2
Your task, now, is to design the circuitry of the logic system to open the waste valve if and only if there is good flame proven by the sensors.
First, though, we must decide what the logical behavior of this control system should be. Do we want the valve to be opened if only one out of the three sensors detects flame?
Probably not, because this would defeat the purpose of having multiple sensors. If any one of the sensors were to fail in such a way as to falsely indicate the presence of flame when there was none, a logic system based on the principle of "any one out of three sensors showing flame" would give the same output that a single-sensor system would with the same failure.
Prof. G. Succi, Ph.D., P.Eng.

16. Exercise 2
A far better solution would be to design the system so that the valve is commanded to open if and only if all three sensors detect a good flame. This way, any single, failed sensor falsely showing flame could not keep the valve in the open position; rather, it would require all three sensors to be failed in the same manner -- a highly improbable scenario -- for this dangerous condition to occur.
Prof. G. Succi, Ph.D., P.Eng.

17. Exercise 2 Thus, our truth table would look like this:
Prof. G. Succi, Ph.D., P.Eng.

18. Exercise 2
It does not require much insight to realize that this functionality could be generated with a three-input AND gate: the output of the circuit will be "high" if and only if input A AND input B AND input C are all "high:"
Prof. G. Succi, Ph.D., P.Eng.

19. Exercise 2
While this design strategy maximizes safety, it makes the system very susceptible to sensor failures of the opposite kind. Suppose that one of the three sensors were to fail in such a way that it indicated no flame when there really was a good flame in the incinerator's combustion chamber. That single failure would shut off the waste valve unnecessarily, resulting in lost production time and wasted fuel (feeding a fire that wasn't being used to incinerate waste).
It would be nice to have a logic system that allowed for this kind of failure without shutting the system down unnecessarily, yet still provide sensor redundancy so as to maintain safety in the event that any single sensor failed "high" (showing flame at all times, whether or not there was one to detect). A strategy that would meet both needs would be a "two out of three" sensor logic, whereby the waste valve is opened if at least two out of the three sensors show good flame.
Prof. G. Succi, Ph.D., P.Eng.

20. Exercise 2 The truth table for such a system would look like this:
Create the Boolean expression and draw the circuit
Simplify the expression and draw the simplified circuit
Prof. G. Succi, Ph.D., P.Eng.

21. Circuit Equivalence (5)
Alternative symbols for some gates: (a) NAND (b) NOR (c) AND (d) OR
Prof. G. Succi, Ph.D., P.Eng.

22. Circuit Equivalence (6)
(a) The truth table for the XOR function. (b)–(d) Three circuits for computing it.
Prof. G. Succi, Ph.D., P.Eng.

23. Circuit Equivalence (7)
(a) Electrical characteristics of a device. (b) Positive logic. (c) Negative logic.
Prof. G. Succi, Ph.D., P.Eng.

24. Integrated Circuits
Common types of integrated-circuit packages, including a dual-inline package (a), pin grid array (b), and land grid array (c).
Prof. G. Succi, Ph.D., P.Eng.

25. Multiplexers (1) An eight-input multiplexer circuit.
Prof. G. Succi, Ph.D., P.Eng.

26. Multiplexers (2)
(a) An eight-input multiplexer. (b) The same multiplexer wired to compute the majority function.
Prof. G. Succi, Ph.D., P.Eng.

27. Decoders
A 3-to-8 decoder circuit.
Prof. G. Succi, Ph.D., P.Eng.

28. Comparators
A simple 4-bit comparator.
Prof. G. Succi, Ph.D., P.Eng.

29. Arithmetic Circuits (1)
A 1-bit left/right shifter.
Prof. G. Succi, Ph.D., P.Eng.

30. Arithmetic Circuits (2)
(a) Truth table for 1-bit addition. (b) A circuit for a half adder.
Prof. G. Succi, Ph.D., P.Eng.

31. Arithmetic Circuits (3)
(a) Truth table for full adder. (b) Circuit for a full adder.
Prof. G. Succi, Ph.D., P.Eng.

32. Arithmetic Logic Units (1)
A 1-bit ALU.
Prof. G. Succi, Ph.D., P.Eng.

33. Arithmetic Logic Units (2)
Eight 1-bit ALU slices connected to make an 8-bit ALU. The enables and invert signals are not shown for simplicity.
Prof. G. Succi, Ph.D., P.Eng.

34. Clocks
(a) A clock. (b) The timing diagram for the clock. (c) Generation of an asymmetric clock.
Prof. G. Succi, Ph.D., P.Eng.

35. Latches
(a) NOR latch in state 0. (b) NOR latch in state 1. (c) Truth table for NOR.
Prof. G. Succi, Ph.D., P.Eng.

36. Clocked SR Latches
A clocked SR latch.
Prof. G. Succi, Ph.D., P.Eng.

37. Clocked D Latches
A clocked D latch.
Prof. G. Succi, Ph.D., P.Eng.

38. Flip-Flops (1)
(a) A pulse generator. (b) Timing at four points in the circuit.
Prof. G. Succi, Ph.D., P.Eng.

39. Flip-Flops (2)
A D flip-flop.
Prof. G. Succi, Ph.D., P.Eng.

40. Flip-Flops (3)
D latches and flip-flops.
Prof. G. Succi, Ph.D., P.Eng.

41. Memory Organization (1)
An 8-bit register constructed from single-bit flip-flops.
Prof. G. Succi, Ph.D., P.Eng.

42. Memory Organization (2a)
(On the next 2 slides): Logic diagram for a 4 x 3 memory. Each row is one of the four 3-bit words. A read or write operation always reads or writes a complete word.
Prof. G. Succi, Ph.D., P.Eng.

43. Prof. G. Succi, Ph.D., P.Eng.

44. Prof. G. Succi, Ph.D., P.Eng.

45. Memory Organization (3)
(a) A noninverting buffer. (b) Effect of (a) when control is high. (c) Effect of (a) when control is low. (d) An inverting buffer.
Prof. G. Succi, Ph.D., P.Eng.

46. Memory Chips (1) Two ways of organizing a 4-Mbit memory chip.
Prof. G. Succi, Ph.D., P.Eng.

47. Memory Chips (2) Two ways of organizing a 512-Mbit memory chip.
Prof. G. Succi, Ph.D., P.Eng.

48. Nonvolatile Memory Chips(2)
A comparison of various memory types.
Prof. G. Succi, Ph.D., P.Eng.

49. Field-Programmable Gate Arrays
(a) A field-programmable logic array lookup table (LUT). (b) The LUT configuration to create a 3-bit clearable counter.
Prof. G. Succi, Ph.D., P.Eng.

50. CPU Chip Control Pins Bus control Interrupts Bus arbitration
Coprocessor signaling
Status
Miscellaneous
Prof. G. Succi, Ph.D., P.Eng.

51. CPU Chips
The logical pinout of a generic CPU. The arrows indicate input signals and output signals. The short diagonal lines indicate that multiple pins are used. For a specific CPU, a number will be given to tell how many.
Prof. G. Succi, Ph.D., P.Eng.

52. Computer Buses (1) A computer system with multiple buses.
Prof. G. Succi, Ph.D., P.Eng.

53. Computer Buses (2) Examples of bus masters and slaves.
Prof. G. Succi, Ph.D., P.Eng.

54. Bus Width Growth of an address bus over time.
Prof. G. Succi, Ph.D., P.Eng.

55. Synchronous Buses (1) (a) Read timing on a synchronous bus.
Prof. G. Succi, Ph.D., P.Eng.

56. Synchronous Buses (2) (b) Specification of some critical times.
Prof. G. Succi, Ph.D., P.Eng.

57. Asynchronous Buses Operation of an asynchronous bus.
Prof. G. Succi, Ph.D., P.Eng.

58. Four Events of Full-Handshake
Prof. G. Succi, Ph.D., P.Eng.

59. Bus Arbitration (1)
(a) A centralized one-level bus arbiter using daisy chaining. (b) The same arbiter, but with two levels.
Prof. G. Succi, Ph.D., P.Eng.

60. Bus Arbitration (2) Decentralized bus arbitration
Prof. G. Succi, Ph.D., P.Eng.

61. Bus Operations (1)
A block transfer.
Prof. G. Succi, Ph.D., P.Eng.

62. Bus Operations (2) Use of the 8259A interrupt controller
Prof. G. Succi, Ph.D., P.Eng.

63. The Intel Core i7 The Core i7 physical pinout.
Prof. G. Succi, Ph.D., P.Eng.

64. The Core i7’s Logical Pinout
Logical pinout of the Core i7.
Prof. G. Succi, Ph.D., P.Eng.