Presentation is loading. Please wait.

Presentation is loading. Please wait.

Architecture Synthesis for Cost Constrained Fault Tolerant Biochips

Published byMarcus Elliott Modified over 5 years ago

Similar presentations

Presentation on theme: "Architecture Synthesis for Cost Constrained Fault Tolerant Biochips"— Presentation transcript:

1 Architecture Synthesis for Cost Constrained Fault Tolerant Biochips
M. C. Eskesen, P. Pop and S. Potluri Department of Applied Mathematics and Computer Science, Technical University of Denmark

2 Outline Introduction to mVLSI Flow-based biochips
Defects and need for reliability Fault model and fault tolerant components Motivational example Problem formulation and objective Optimization strategy Experimental results Conclusions

3 Introduction to mVLSI Source: W. Grover, “Designing, fabricating and using flow-based microfluidics: Past successes and future challenges”, Tutorial, VLSI Design 2015

4 Flow-based (FB) Biochips
Source:

5 Technology and high level abstraction
Multi-layer soft lithography Fabrication substrate – elastomers (PDMS) Source: S. R. Quake et al, “From micro- to nanofabrication using soft materials”, Science 2000 a Pressure Source Control Layer Flow Layer Valve va Fluidic Input Control Pin z1 3D View Top View Glass Plate

6 Defects in microfabrication of FB biochips
Source: K. Hu et.al, “Testing of Flow-based Microfluidic Biochips: Fault Modeling, Test Generation and Experimental Demonstration”, IEEE TCAD, 2014

7 Need for Reliability Sensitivity= positivity in disease, expressed as a % = TP/ (TP+FN) × 100 Specificity = absence of a particular disease, expressed as % = TN/ (FP+TN)× 100 TP = True Positives, the number of diseased patients correctly classified by the test TN = True Negatives, number of non-diseased patients correctly classified by the test FP = False Positives, the number of non-diseased patients misclassified by the test FN = False Negatives, the number of diseased patients misclassified by the test

8 System Specifications
The big picture System Specifications Architectural Design Functional Design Logic Design Circuit Design Physical Design Fabrication Schematic Design (Flow Layer) Application Mapping Control Synthesis (Control Layer) 1 v1 v2 ... t1 t2 t3 VLSI mVLSI X = (AB + CD) Y= (A(B+C))

9 Recompile biochemical application
The big picture Biochip synthesis Recompile biochemical application Original netlist Fault locations Add redundancy Diagnosis Fault tolerant netlist Defective biochip Testing Fabrication Fabricated biochip

10 Fault model

11 Fault-tolerant switch design
Cost overhead: 1 extra valve per switch

12 Fault-tolerant pump/mixer design
Cost overhead: 1 extra valve per pump

13 Fault-tolerant channels
Cost overhead: 4 extra valves and 3 extra channels

14 Motivational example

15 Straightforward vs. optimized synthesis
Straightforward solution: redundancy not optimized; biochip architecture cost: 129 Optimized solution: optimal addition of redundancy biochip architecture cost: 96

16 Problem formulation Fault Tolerant Architecture Synthesis (FTAS) Given
A biochemical application and a fault model Characterized component model library (including fault-tolerant components) Synthesize A biochip architecture Deciding on: Component allocation Fault-tolerant netlist generation Schedule for routing of fluids through the microfluidic channels Such that the cost of the architecture is minimized Satisfying the fault-tolerance, dependency and resource constraints Facilitates programmability and automation Cost = total number of valves + total number of channels in the architecture

17 Fault Tolerant Architecture Synthesis (FTAS)
Problem formulation Application model Component library& Design constraints Initial architecture Fault model Fault Tolerant Architecture Synthesis (FTAS) Fault tolerant architecture Cost = total number of valves + total number of channels in the architecture

18 Optimization strategy (FTAS)
Design transformations Add redundant component Make component fault-tolerant Add redundant connection Remove redundant component Make component non fault-tolerant Remove redundant connection

19 Optimization strategy (FTAS)
Metaheuristic optimization: Greedily Randomized Adaptive Search Procedure (GRASP) Searches the solution space to minimize the objective function Fault scenario generation: subset of all the possible scenarios Each iteration applies design transformations visits a neighboring solution Applies a fault scenario: injects the faults in the scenario Determines connectivity: can I still move fluids around? Finish time of the application: will the application finish correctly? Evaluates them based on the objective, to pick or drop the neighboring solution.

20 Optimization strategy (FTAS)
Connectivity 1 if connected, 0 otherwise Determined by Breadth First Search Considers blocked route and valve faults on switches Physical constraints Sum of Total number of valves Total number of connections Facilitates programmability and automation Scheduling Maximum of 0 or δ - application deadline Determined by List Scheduling Routes determined by Breadth First Search

21 Optimization strategy (FTAS)
Facilitates programmability and automation

22 Experimental Results A: Original biochip architecture
ASFS+ : Biochip architecture obtained using straightforward fault solution AFTAS+: Biochip architecture obtained using proposed FTAS approach N : Set of all microfluidic components in the biochip D : Set of all microfluidic channels in the biochip Name A |FS| |FS-| ASFS+ AFTAS+ |N| |D| Cost S-1 15 17 84 121 100 20 27 133 102 PCR 14 16 88 77 50 18 25 135 92 IVD 52 78 274 841 57 379 279

23 Yield Results for S-1 benchmark
FS : Exhaustive set of fault scenarios based on the fault model FS - : Chosen fraction of fault scenarios FST : Set of fault scenarios tolerated by the architecture |FS-| AFTAS+ |FST| %Yield 25 16 20 98 105 86.8% 50 15 19 99 117 96.7% 121 102 100%

24 Thank you!

25 Microfluidic Large Scale Integration
System Specifications Architectural Design Functional Design Logic Design Circuit Design Physical Design Fabrication Schematic Design (Flow Layer) Application Mapping Control Synthesis (Control Layer) 1 v1 v2 ... t1 t2 t3 VLSI mVLSI X = (AB + CD) Y= (A(B+C))

26 Component library

27 Optimization strategy
Fault scenario generation Each iteration Applies a fault scenario Determines connectivity Finish time, δ, of the application Channel S1 → Mixer1 is blocked, Channel of Heater1 suffers from a block defect. A valve in the pump of Mixer1 and the valves controlling the channel towards S3 and the channel towards S5 of S4 are stuck open Connectivity 1 if connected, 0 otherwise Determined by Breadth First Search Considers blocked route and valve faults on switches Scheduling Maximum of 0 or δ - application deadline Determined by List Scheduling Routes determined by Breadth First Search Physical constraints Sum of Total number of valves Total number of connections

28 Implementation

29 Experimental Setup Implemented in Python 3.4
Intel Xeon X5550 processor Running at 2.65 GHz, with 24 GB RAM One synthetic benchmark S-1 Two real-life benchmarks IVD (In-Vitro-Diagnostics) PCR (Polymerase-Chain-Reaction)

30 Experimental Results

Download ppt "Architecture Synthesis for Cost Constrained Fault Tolerant Biochips"

Similar presentations

Gate Sizing for Cell Library Based Designs Shiyan Hu*, Mahesh Ketkar**, Jiang Hu* *Dept of ECE, Texas A&M University **Intel Corporation.

Gate Sizing for Cell Library Based Designs Shiyan Hu*, Mahesh Ketkar**, Jiang Hu* *Dept of ECE, Texas A&M University **Intel Corporation.
Address comments to FPGA Area Reduction by Multi-Output Sequential Resynthesis Yu Hu 1, Victor Shih 2, Rupak Majumdar 2 and Lei He 1 1.

Address comments to FPGA Area Reduction by Multi-Output Sequential Resynthesis Yu Hu 1, Victor Shih 2, Rupak Majumdar 2 and Lei He 1 1.
NanoFabric Chang Seok Bae. nanoFabric nanoFabric : an array of connect nanoBlocks nanoBlock : logic block that can be progammed to implement Boolean function.

NanoFabric Chang Seok Bae. nanoFabric nanoFabric : an array of connect nanoBlocks nanoBlock : logic block that can be progammed to implement Boolean function.
A Field-Programmable Pin-Constrained Digital Microfluidic Biochip Dan Grissom and Philip Brisk University of California, Riverside Design Automation Conference.

A Field-Programmable Pin-Constrained Digital Microfluidic Biochip Dan Grissom and Philip Brisk University of California, Riverside Design Automation Conference.
A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization Yih-Chih Chou and Youn-Long Lin Department of Computer Science, Tsing.

A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization Yih-Chih Chou and Youn-Long Lin Department of Computer Science, Tsing.
1 of 14 1 /23 Flexibility Driven Scheduling and Mapping for Distributed Real-Time Systems Paul Pop, Petru Eles, Zebo Peng Department of Computer and Information.

1 of 14 1 /23 Flexibility Driven Scheduling and Mapping for Distributed Real-Time Systems Paul Pop, Petru Eles, Zebo Peng Department of Computer and Information.
Droplet-Aware Module-Based Synthesis for Fault-Tolerant Digital Microfluidic Biochips Elena Maftei, Paul Pop, and Jan Madsen Technical University of Denmark.

Droplet-Aware Module-Based Synthesis for Fault-Tolerant Digital Microfluidic Biochips Elena Maftei, Paul Pop, and Jan Madsen Technical University of Denmark.
An Optimal Algorithm of Adjustable Delay Buffer Insertion for Solving Clock Skew Variation Problem Juyeon Kim, Deokjin Joo, Taehan Kim DAC’13.

An Optimal Algorithm of Adjustable Delay Buffer Insertion for Solving Clock Skew Variation Problem Juyeon Kim, Deokjin Joo, Taehan Kim DAC’13.
1 of 10 April 25, 2001 Minimizing System Modification in an Incremental Design Approach Paul Pop, Petru Eles, Traian Pop, Zebo Peng Department of Computer.

1 of 10 April 25, 2001 Minimizing System Modification in an Incremental Design Approach Paul Pop, Petru Eles, Traian Pop, Zebo Peng Department of Computer.
TH EDA NTHU-CS VLSI/CAD LAB 1 Re-synthesis for Reliability Design Shih-Chieh Chang Department of Computer Science National Tsing Hua University.

TH EDA NTHU-CS VLSI/CAD LAB 1 Re-synthesis for Reliability Design Shih-Chieh Chang Department of Computer Science National Tsing Hua University.
NORM BASED APPROACHES FOR AUTOMATIC TUNING OF MODEL BASED PREDICTIVE CONTROL Pastora Vega, Mario Francisco, Eladio Sanz University of Salamanca – Spain.

NORM BASED APPROACHES FOR AUTOMATIC TUNING OF MODEL BASED PREDICTIVE CONTROL Pastora Vega, Mario Francisco, Eladio Sanz University of Salamanca – Spain.
Layout-based Logic Decomposition for Timing Optimization Yun-Yin Lien* Youn-Long Lin Department of Computer Science, National Tsing Hua University, Hsin-Chu,

Layout-based Logic Decomposition for Timing Optimization Yun-Yin Lien* Youn-Long Lin Department of Computer Science, National Tsing Hua University, Hsin-Chu,
1 of 14 1 / 18 An Approach to Incremental Design of Distributed Embedded Systems Paul Pop, Petru Eles, Traian Pop, Zebo Peng Department of Computer and.

1 of 14 1 / 18 An Approach to Incremental Design of Distributed Embedded Systems Paul Pop, Petru Eles, Traian Pop, Zebo Peng Department of Computer and.
Tabu Search-Based Synthesis of Dynamically Reconfigurable Digital Microfluidic Biochips Elena Maftei, Paul Pop, Jan Madsen Technical University of Denmark.

Tabu Search-Based Synthesis of Dynamically Reconfigurable Digital Microfluidic Biochips Elena Maftei, Paul Pop, Jan Madsen Technical University of Denmark.
Tradeoff Analysis for Dependable Real-Time Embedded Systems during the Early Design Phases Junhe Gan.

Tradeoff Analysis for Dependable Real-Time Embedded Systems during the Early Design Phases Junhe Gan.
L i a b l eh kC o m p u t i n gL a b o r a t o r y On Effective TSV Repair for 3D- Stacked ICs Li Jiang †, Qiang Xu † and Bill Eklow § † CUhk REliable.

L i a b l eh kC o m p u t i n gL a b o r a t o r y On Effective TSV Repair for 3D- Stacked ICs Li Jiang †, Qiang Xu † and Bill Eklow § † CUhk REliable.
Recent Research and Emerging Challenges in the System-Level Design of Digital Microfluidic Biochips Paul Pop, Elena Maftei, Jan Madsen Technical University.

Recent Research and Emerging Challenges in the System-Level Design of Digital Microfluidic Biochips Paul Pop, Elena Maftei, Jan Madsen Technical University.
CAD for Physical Design of VLSI Circuits

CAD for Physical Design of VLSI Circuits
LOPASS: A Low Power Architectural Synthesis for FPGAs with Interconnect Estimation and Optimization Harikrishnan K.C. University of Massachusetts Amherst.

LOPASS: A Low Power Architectural Synthesis for FPGAs with Interconnect Estimation and Optimization Harikrishnan K.C. University of Massachusetts Amherst.
TSV-Aware Analytical Placement for 3D IC Designs Meng-Kai Hsu, Yao-Wen Chang, and Valerity Balabanov GIEE and EE department of NTU DAC 2011.

TSV-Aware Analytical Placement for 3D IC Designs Meng-Kai Hsu, Yao-Wen Chang, and Valerity Balabanov GIEE and EE department of NTU DAC 2011.

Similar presentations

Ads by Google