Presentation is loading. Please wait.

Presentation is loading. Please wait.

積體電路元件與製程 半導體物理 半導體元件 PN junction CMOS 製程 MOS 元件.

Published byMaximilian Lloyd Modified over 5 years ago

Similar presentations

Presentation on theme: "積體電路元件與製程 半導體物理 半導體元件 PN junction CMOS 製程 MOS 元件."— Presentation transcript:

1 積體電路元件與製程 半導體物理 半導體元件 PN junction CMOS 製程 MOS 元件

2 ELECTRICAL CONDUCTION IN SOLIDS PROPERTIES OF THE MATERIALS
MOS Device ELECTRICAL CONDUCTION IN SOLIDS PROPERTIES OF THE MATERIALS MOS Device Behavior Sub-Micron MOS Transistor

3 ■ ELECTRICAL CONDUCTION IN SOLIDS

4 Energy Gap in solids

5 Fermi-Dirac distribution function for three different values of temperature

6 Carrier Density

7 Intrinsic and Impurity

8 Extrinsic

9 Conductivity

10 Why Doping ?

11 ■ PROPERTIES OF THE MATERIALS
Silicon Polysilicon Silicon Dioxide Silicon Nitride

12 Silicon

13 Sheet Resistance

14 Polysilicon

15 Silicon Dioxide

16 Growth Speed

17 Cont’d

18 Silicon Nitride

19 Characteristics of MOS Device

20 Depletion Region

21 Current-Voltage Relations

22 ■ MOS Device Behavior

23 Basic Shape – Ids vs. Vds

24 Basic Shape –Ids vs. Vgs

25 Subthreshold Conduction

26 A model for manual analysis

27 Dynamic Behavior of MOS Transistor

28 Gate Capacitance

29 Average Gate Capacitance

30 Diffusion Capacitance

31 Junction Capacitance

32 Interface Band Structure

33 Evaluation of Vth

34 Flat-Band Voltage

35 Threshold Voltage Vth

36 Regions

37 Saturation Region

38 Cont’d

39 Id - Body Effect

40 Pinch-Off

41 Channel Length Modulation

42 Id – Channel length modulation

43 Conductance

44 Transconductance

45 Cont’d

46 Cont’d

47 Avalanche Region

48 Avalanche

49 gds

50 MOS Scaling

51 Parameter Variation

52 Variations

53 Process Corners

54 Corners

55 Library

56 What to Look for

57 Style, cont’d

58 Some Struggle

59 ■ Sub-Micron MOS Transistor
Threshold Variations • Parasitic Resistances • Velocity Sauturation and Mobility Degradation • Subthreshold Conduction • Latchup

60 Technology Evolution

61 SPICE MODELS Level 1: Long Channel Equations - Very Simple
Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations Level 3: Semi-Emperical - Based on curve fitting to measured devices Level 4 (BSIM): Emperical - Simple and Popular

62 MAIN MOS SPICE PARAMETERS

63 SPICE Parameters for Parasitics

64 Technology Evolution

65 Process Variations Devices parameters vary between runs and even on
the same die! Variations in the process parameters, such as impurity concentration densities, oxide thicknesses, and diffusion depths. These are caused by nonuniform conditions during the deposition and/or the diffusion of the impurities. This introduces variations in the sheet resistances and transistor parameters such as the threshold voltage. Variations in the dimensions of the devices, mainly resulting from the limited resolution of the photolithographic process. This causes (W/L) variations in MOS transistors and mismatches in the emitter areas of bipolar devices.

66 Impact of Device Variations

Download ppt "積體電路元件與製程 半導體物理 半導體元件 PN junction CMOS 製程 MOS 元件."

Similar presentations

MICROWAVE FET Microwave FET : operates in the microwave frequencies

MICROWAVE FET Microwave FET : operates in the microwave frequencies
MODULE SYSTEM LOGIC GATE CIRCUIT DQ CMOS Inverter ASIC Full-Custom Semi-Custom Programmable FPGA PLD Cell-Based Gate Arrays General Purpose DRAM & SRAM.

MODULE SYSTEM LOGIC GATE CIRCUIT DQ CMOS Inverter ASIC Full-Custom Semi-Custom Programmable FPGA PLD Cell-Based Gate Arrays General Purpose DRAM & SRAM.
Digital Integrated Circuits© Prentice Hall 1995 Devices Jan M. Rabaey The Devices.

Digital Integrated Circuits© Prentice Hall 1995 Devices Jan M. Rabaey The Devices.
VLSI Design Lecture 3a: Nonideal Transistors. Outline Transistor I-V Review Nonideal Transistor Behavior Velocity Saturation Channel Length Modulation.

VLSI Design Lecture 3a: Nonideal Transistors. Outline Transistor I-V Review Nonideal Transistor Behavior Velocity Saturation Channel Length Modulation.
EE466: VLSI Design Lecture 02 Non Ideal Effects in MOSFETs.

EE466: VLSI Design Lecture 02 Non Ideal Effects in MOSFETs.
Design and Implementation of VLSI Systems (EN1600) Lecture08 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

Design and Implementation of VLSI Systems (EN1600) Lecture08 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.
Introduction to CMOS VLSI Design Lecture 15: Nonideal Transistors David Harris Harvey Mudd College Spring 2004.

Introduction to CMOS VLSI Design Lecture 15: Nonideal Transistors David Harris Harvey Mudd College Spring 2004.
Introduction to CMOS VLSI Design Lecture 19: Nonideal Transistors

Introduction to CMOS VLSI Design Lecture 19: Nonideal Transistors
Introduction to CMOS VLSI Design MOS Behavior in DSM.

Introduction to CMOS VLSI Design MOS Behavior in DSM.
Introduction to VLSI Circuits and Systems, NCUT 2007 Chapter 6 Electrical Characteristic of MOSFETs Introduction to VLSI Circuits and Systems 積體電路概論 賴秉樑.

Introduction to VLSI Circuits and Systems, NCUT 2007 Chapter 6 Electrical Characteristic of MOSFETs Introduction to VLSI Circuits and Systems 積體電路概論 賴秉樑.
VLSI Design Lecture 3a: Nonideal Transistors

VLSI Design Lecture 3a: Nonideal Transistors
CSCE 612: VLSI System Design Instructor: Jason D. Bakos.

CSCE 612: VLSI System Design Instructor: Jason D. Bakos.
Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective
Introduction to CMOS VLSI Design Nonideal Transistors.

Introduction to CMOS VLSI Design Nonideal Transistors.
MOS Capacitors MOS capacitors are the basic building blocks of CMOS transistors MOS capacitors distill the basic physics of MOS transistors MOS capacitors.

MOS Capacitors MOS capacitors are the basic building blocks of CMOS transistors MOS capacitors distill the basic physics of MOS transistors MOS capacitors.
EE213 VLSI Design S Daniels Channel Current = Rate of Flow of Charge I ds = Q/τ sd Derive transit time τ sd τ sd = channel length (L) / carrier velocity.

EE213 VLSI Design S Daniels Channel Current = Rate of Flow of Charge I ds = Q/τ sd Derive transit time τ sd τ sd = channel length (L) / carrier velocity.
NOTICES Project proposal due now Format is on schedule page

NOTICES Project proposal due now Format is on schedule page
© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.
The Devices Digital Integrated Circuit Design Andrea Bonfanti DEIB

The Devices Digital Integrated Circuit Design Andrea Bonfanti DEIB
© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Similar presentations

Ads by Google