1. Registers and clocking issues
CS/COE 0447 (term 2181)
Jarrett Billingsley

2. Class announcements Anyone not get their exams baaaaaack?
Trying to squeeeeeze some things into today's lecture
10/26/2017
CS/COE 0447 term 2181

3. Registers
10/26/2017
CS/COE 0447 term 2181

4. Follow the leader
The clock is the repeating signal that synchronizes everything.
We don't always want to write to a register.
Which register is changed in the instruction add t0, t1, t2?
What about the other 31 registers?
We want our registers to store their data:
in sync with the clock, and
only if we told that register to store the input data.
We call this a write enable signal.
Cause it enables writing.
There's an and up there…
10/26/2017
CS/COE 0447 term 2181

5. Trying to make it work
We can AND together the clock and the write enable signals, and feed that into the D latch's original "enable" input.
write enable
old enable
clock 𝐐
data
10/26/2017
CS/COE 0447 term 2181

6. Not quite there…
When the clock and write enable inputs are high (1), the latch will perfectly mirror its data input. That means…
The data input can't change while the clock signal is high.
Otherwise, it'll output incorrect values.
This is easier to demonstrate than it is to explain.
10/26/2017
CS/COE 0447 term 2181

7. The majestic D flap-flap
By chaining two D latches in a row and using some clever NOTs, we end up with the D Flip-Flop.
The triangle on the symbol is the clock input.
We might also call this a 1-bit register!
It stores the input data the instant the clock goes high, and then becomes latched. D Q
can't be changed.
clock
time
store!
10/26/2017
CS/COE 0447 term 2181

8. A school of D flip-flops
If we want an n bit register, we put n flip-flops next to each other.
Each flip-flop holds 1 bit of the 4-bit value.
write enable
clock D Q 4 D Q 4 D Q
Splitters can also bundle wires together. D Q
A splitter lets us split up wire bundles.
10/26/2017
CS/COE 0447 term 2181

9. Clocking Issues
10/26/2017
CS/COE 0447 term 2181

10. The Critical Path
A critical path is the path through a circuit (or a program, or any process) that requires the longest series of sequential operations.
Those steps can't be done in parallel!
For the following, what's the length of the critical path, in gates?
10/26/2017
CS/COE 0447 term 2181

11. Propagation Delay
Propagation delay is the time it takes for a signal to pass from the inputs to the outputs. Everything, even wires, adds a delay.
While the signal is moving through, the outputs are invalid.
When the signal finishes moving, the outputs are valid.
If you try to use the output before it's valid, things break.
Propagation delay is the reason there are limits to how fast your processor can run.
What's worse: the hotter it is, the worse the delay gets!
10/26/2017
CS/COE 0447 term 2181

12. Determining clock speed+ 1 A D Q
A value is written into register A.
1 is added to its output.
Go back to step 1.
Let's say that a register takes 2ns to propagate its value from D to Q, and the adder takes 3ns to compute its output.
How fast can we run the clock?
10/26/2017
CS/COE 0447 term 2181

13. Determining clock speedQ + A 1
0ns
2ns
5ns
time
A's Q becomes valid.
The adder has finished. Clock A to store!
A is clocked.
10/26/2017
CS/COE 0447 term 2181

14. Determining clock speed
It takes 5ns for a signal to propagate through our circuit. So how fast can we clock it?
If the time between clocks is less than 5ns, we'll clock the register too early (before the adder has finished).
If the time between clocks is longer than 5ns, no big deal.
𝟏 𝟓× 𝟏𝟎 −𝟗 𝒔 =𝟎.𝟐× 𝟏𝟎 𝟗 𝐇𝐳
=𝟐𝟎𝟎𝐌𝐇𝐳
In general, the fastest we can clock a sequential circuit is the reciprocal of the critical path's propagation delay.
10/26/2017
CS/COE 0447 term 2181

15. IN 12 ??? A D Q EN B D Q EN 12 ??? CLK Clock Skew
The clock signal isn't immune to propagation delay! IN
Watch the input as the clock pulse travels down the wire to B. 12
??? A
D Q EN B
D Q EN 12
???
CLK
This is called a race condition. There's a race between the data and clock signals, and in this case the data signal wins.
Avoiding race conditions is an extremely important part of design!
10/26/2017
CS/COE 0447 term 2181

16. Clock skew on a large scale
The clock signal has to visit EVERY part of the processor.
Long wires, lots of metal, nontrivial capacitance/inductance...
10/26/2017
CS/COE 0447 term 2181

17. Ripples in ripples If the clock sends out pulses too quickly...
Different parts of the processor will think it's different times!
Everything falls apart!
How can we avoid this??
Make clock slower? Ehh...
Make chip smaller
Shorter wires and less metal means faster ripples
Make gates faster
New process technologies can reduce gate delay
Use non-electronic clock distribution??
On-chip light guides to transmit clock pulses as light instead of electrons??!???!? Issues abound
10/26/2017
CS/COE 0447 term 2181