1. Chapter 4
Interconnect

2. Polysilicon for Local Connections
Transistor
(2l x 4l) WL
[0]
GND WL
[1]
ROM Layout
Polysilicon WL
[2]
Metal1
GND
Diffusion WL
[3]
Metal1 on Diffusion
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3. A Look on IC Interconnections
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4. Metal for Long Connections
Intel 4004 (‘71)
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Cortesia Intel

5. Metal Multi-layer
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3-5

6. Design Rules Manufacturer´s reliability limits - E.g. scalable l rules
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7. Electrical Parameters?
Design Rules
How about
Electrical Parameters?
Manufacturer´s reliability limits
- E.g. scalable l rules
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8. Electrical Parameters1 L 2
Wire length L1 < L2 R 1 R 2 C 1 C 2
For wire width W1= W2, what is the relation between R1 and R2 (or C1 and C2)? Why ?
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9. Interconnect Geometric Parameters
w: width
l: length
t: thickness
h: height (to next conducting layer)
s: spacing
w+s: pitch
t/w: aspect ratio
current
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10. Geometries in Six Metal Layers
(t/w)
longer
Current technoloies:
high resitance
(l >> t or w)
-high capacitance
(h and s small)
(h)
(h)
(h)
(h)
(h)
shorter
(h)
Top-down
Side-by-side
Remember h is the inter layer distance!!!
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11. Geometries in Six Metal Layers
(t/w)
longer
Pitches:
Metal 6– 1,72 mm
-Metal 1 – 0,5 mm
(h)
(h)
(h)
(h)
(h)
shorter
(h)
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4-11

12. W-L based Resistance ; r: material resistivity
- since t is a technology parameter:
R is the sheet resistance
(tech. parameter) I I
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13. Metal Resistivity
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14. Sheet Resistance Values
Why does R decrease?
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15. Vias and Resistance Reduction
For vias, typical R is 2 to 20 W
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16. Fringing Fields : classic parallel plate capacitance
There exist more exact (complex) empirical formulas to take into account the fringing effects
fringing effect
bottom plate effect
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17. Multilayer Capacitance Model 1
Upper-bound capacitance value: to consider the upper e lower layer as a substrate plate (conservative calculus)
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18. Example for Model 1
Obs. w and s are given as multiples of the minimum values (design rules) to the layer.
This number increases for higher level layers!!
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19. Example for Model 1
Ex. by design rules - for Metal 1, w minimum is 3l= 3X (180/2)= 270nm
For Metal 6, w minimum is 10l= =900nm
Also, the larger the width w of the plate, the larger the capacitance.
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20. Multilayer Capacitance Model 2
Lower-bound capacitance value: to consider the substrate below and nothing above (optimistic calculus)
Layer n
Substrate
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4-20

21. Example for Model2
Obs. w and s are given as multiples of the minimum values (design rules) to the layer.
This number increases for higher level layers!!
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22. Example for Model2
Ex. by design rules - for Metal 1, w minimum is 3l= 3X (180/2)= 270nm
For Metal 6, w minimum is 10l= =900nm
Also, the larger the width w of the plate, the larger the capacitance.
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23. Metal2 Example Model 1: lower effect for s higher effect for w
- higher effect for s
lower effect for w
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