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**Exclusive-OR and Exclusive-NOR Gates**

Chapter 6 Exclusive-OR and Exclusive-NOR Gates 1

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**Objectives You should be able to:**

Describe the operation and use of exclusive-OR and exclusive-NOR gates. Construct truth tables and draw timing diagrams for exclusive-OR and exclusive-NOR gates. Simplify combinational logic circuits containing exclusive-OR and exclusive-NOR gates. 2

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**Objectives (Continued)**

Design odd- and even-parity generator and checker systems. Explain the operation of a binary comparator and a controlled inverter. Implement circuits in FPGA ICs using VHDL. 2

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The Exclusive-OR Gate The output is HIGH if either one or the other inputs are HIGH., but not both. 4

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The Exclusive-OR Gate Logic circuits for the exclusive-OR function. 5

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The Exclusive-OR Gate Logic Symbol and Boolean equation 6

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**The Exclusive-NOR Gate**

The complement of the exclusive-OR. Often called an equality gate: The output is HIGH when the inputs are equal. 7

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**The Exclusive-NOR Gate**

Ex-NOR Logic Circuit 8

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**The Exclusive-NOR Gate**

EX-NOR Logic Symbol and Boolean equation 9

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**Parity Generator / Checker**

Electrical noise in the transmission of binary information can cause errors. Parity can detect these types of errors. Parity systems Odd parity Even parity Adds a bit to the binary information 10

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**Parity Generator / Checker**

Odd parity generator/checker 11

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**Parity Generator / Checker**

Four-bit even- and odd-parity generators 12

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**Parity Generator / Checker**

Eight-bit even-parity generator 13

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**Parity Generator / Checker**

Five bit even-parity checker 14

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**Parity Generator / Checker**

Integrated-Circuit Parity Generator/Checker 74280 TTL IC logic symbol and Function Table 15

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**Parity-Error Detection System**

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**Parallel Binary Counter**

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Controlled Inverter 19

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Discussion Point Describe the operation of an exclusive OR and an exclusive NOR gate. Design an exclusive OR gate from NOR gates. 20

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Discussion Point Does the circuit below function as an even or odd parity generator? 21

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**FPGA Design Applications with VHDL**

New concepts included in examples 6-8 though 6-10: 7400-series macro-functions Grouping nodes to a common bus Changing a group’s radix Creating a VHDL Process Statement and For Loop. 22

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Example 6-8 The Quartus II software provides the original 74280b in the bdf file. Note that the inputs are grouped as a bus.

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Example 6-8 The radix can be changed in the simulation report of the vwf file.

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Example 6-9 Each node line coming off a bus must be labeled correctly for the compiler.

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**Example 6-9 The hex counter values can be forced to inequality by**

highlighting the number choosing Value > Arbitrary Inserting a new value

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Example 6-10 Note that both the data inputs and the controlled output are grouped as a bus.

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**Example 6-10 When c is low the output is uncomplemented.**

When c is high the output is complemented.

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Example 6-10 An example of a sequential process loop.

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Summary The exclusive-OR gate provides a HIGH output if one input or the other input, but not both, is HIGH. The exclusive-NOR gate outputs a HIGH if both inputs are HIGH or if both inputs are LOW. 24

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Summary A parity bit is commonly used for error detection during the transmission of digital signals. Exclusive-OR and exclusive-NOR gates are used in applications such as parity checking, binary comparison and controlled complementing circuits. FPGAs can be used to implement circuits containing the exclusive gates. 25

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