Presentation on theme: "Exclusive-OR and Exclusive-NOR Gates"— Presentation transcript:
1 Exclusive-OR and Exclusive-NOR Gates Chapter 6Exclusive-OR and Exclusive-NOR Gates1
2 Objectives You should be able to: Describe the operation and use of exclusive-OR and exclusive-NOR gates.Construct truth tables and draw timing diagrams for exclusive-OR and exclusive-NOR gates.Simplify combinational logic circuits containing exclusive-OR and exclusive-NOR gates.2
3 Objectives (Continued) Design odd- and even-parity generator and checker systems.Explain the operation of a binary comparator and a controlled inverter.Implement circuits in FPGA ICs using VHDL.2
4 The Exclusive-OR GateThe output is HIGH if either one or the other inputs are HIGH., but not both.4
5 The Exclusive-OR GateLogic circuits for the exclusive-OR function.5
6 The Exclusive-OR GateLogic Symbol and Boolean equation6
7 The Exclusive-NOR Gate The complement of the exclusive-OR.Often called an equality gate: The output is HIGH when the inputs are equal.7
9 The Exclusive-NOR Gate EX-NOR Logic Symbol and Boolean equation9
10 Parity Generator / Checker Electrical noise in the transmission of binary information can cause errors. Parity can detect these types of errors.Parity systemsOdd parityEven parityAdds a bit to the binary information10
19 Discussion PointDescribe the operation of an exclusive OR and an exclusive NOR gate.Design an exclusive OR gate from NOR gates.20
20 Discussion PointDoes the circuit below function as an even or odd parity generator?21
21 FPGA Design Applications with VHDL New concepts included in examples 6-8 though 6-10:7400-series macro-functionsGrouping nodes to a common busChanging a group’s radixCreating a VHDL Process Statement and For Loop.22
22 Example 6-8The Quartus II software provides the original 74280b in the bdf file.Note that the inputs are grouped as a bus.
23 Example 6-8The radix can be changed in the simulation report of the vwf file.
24 Example 6-9Each node line coming off a bus must be labeled correctly for the compiler.
25 Example 6-9 The hex counter values can be forced to inequality by highlighting the numberchoosing Value > ArbitraryInserting a new value
26 Example 6-10Note that both the data inputs and the controlled output are grouped as a bus.
27 Example 6-10 When c is low the output is uncomplemented. When c is high the output is complemented.
28 Example 6-10An example of a sequential process loop.
29 SummaryThe exclusive-OR gate provides a HIGH output if one input or the other input, but not both, is HIGH.The exclusive-NOR gate outputs a HIGH if both inputs are HIGH or if both inputs are LOW.24
30 SummaryA parity bit is commonly used for error detection during the transmission of digital signals.Exclusive-OR and exclusive-NOR gates are used in applications such as parity checking, binary comparison and controlled complementing circuits.FPGAs can be used to implement circuits containing the exclusive gates.25