1. ATLAS strip CMOS
Development of Sensors for possible use in Silicon Strip region at phase II
Aggressive time schedule – drives choices
Three phase programme – see document attached to indico
Outline of Meeting – Intended as mostly discussion
Mandate & Integration Ingrid/Steve
First Year of Programme
Deliverables
People
Documentation & Meetings
Stanitzky, Fadeyev, Nickerson will make
‘suggestions’ to start discussion
These are just starting points

2. Mandate As part of the ATLAS strip Upgrade Programme:
Develop a strip specific CMOS sensor for ATLAS phase-II
in a three year programme to be ~consistent with the upgrade schedule.
At the end of the programme there should be a sensor characterised sufficiently that ATLAS can choose to re-evaluate the production schedules and consider switch from planar to CMOS in the strip sensor region.
Integrate available efforts from International Community
Interface to Strip Programme through …..Ingrid?
Organise Meetings and Documentation related to programme

3. Programme based on: Reticule or 4 x 1 reticule sized objects
ABC’ read-out chip, same backend, simplified front end
Pixels summed to ~800mm x 37mm areas for read-out
Simple pixels - analogue transmission to boundary
Discrimination & priority encoding at boundary
Reduced number of wire bonds to ABC’ (limited # hits)
Higher speed transmission of information sensor-ABC’
This is the output of WG1
Orientated towards speed of development
Does not include other essential elements
ABC’
Software/Physics studies
Mechanical studies

4. Proposal for meeting content
Firm up first year of programme (Or define route to fixing these things)
Foundries, dates for submissions
Content of first submissions
Read-out and interfaces
Required test programme
Deliverables
Define deliverables for the programme, and milestones (or route to defining)
Define by institute?
People
Identify or define route to identifying:
Sensor designers and who will be doing what
Designers for interface boards
Read-out system / test systems & who will design firmware/software
Who will evaluate parts
Who will organise irradiations
Documentation & Meetings
Define regular vidyo meeting schedule
Define any documentation

5. Foundries Two Foundries One an ‘HV’ process, the other an ‘HR’ process
understood that ‘HV’ can include high res wafers
Understood that these are not only choices, but choices are needed
AMS350 – Top priority as closest to known to be suitable
Tower Jazz – HR process
L-foundry – Experience from Bonn
Possible for designers to change, but WG1 outcome suggests these
Already known properties
Expected Costs
Ease of use
Familiarity – experience in community

6. Submissions
Strips  different optimization from the pixel detector work done so far:
The baseline thinking is to make strips out 37x800 mm2 segments: 32 segments/strip.
Each segment can be composed out of 1<= N <= 8 pixels. That is, pixel size is between 37x100 mm2 and 37x800 mm2 .
Each segment sends (analog) signals to the (digital) periphery, which encodes the data for ABCNCMOS . The connection with ABCNCMOS could feature much reduced number of wirebonds compared to the baseline design of the strip system.
Single beam crossing resolution.
We’ll need different submissions with MPW runs to assess basic properties and architectural issues:
“Basic” submission to answer the question on signal size, NIEL radiation hardness and drift/diffusion ratio. There is a separation the “Signal” and “Amplifier” part.
“Architectural” submission to find out if the signal readout along the strip and the individual pixel “OR’ing” works.

7. “Basic” Submission Test Devices
Proposed test circuits:
“Sensor” diodes, 3x3 pixels. Tests: signal development, depletion/capacitance, irradiation. Variation: pixel size, fill factor.
Integrated 5x5 pixels with amplifiers. Tests: depletion, CCE, irradiation. Variation: pixel size, fill factor.
Front-end amplifier without the “sensor” part, but with I/O test pads. Possibly different shaping time. Tests: gain, irradiation, timewalk (?), output matching.
Transistor test structures: gain, threshold matching. (E.g. see P. Pangaud’s GF talk.)

8. “Architectural” Submission
Partitioning the available area (assume 5x5 mm2) into 3 sub-sections to investigate the effect of different pixel size. Initially considered 3 sizes: x1, x2, x4.
Part 1: parallel traces to the periphery. Addresses the channel density, pixel size. Can use different timewalk design for different pixels. Can implement traces near pixels to inject external signals (noise susceptibility).

9. “Architectural” Submission (2)
Part 2: 2 complete channels with correct total length implemented in a “snaked” geometry. The idea is to test that OR’ing pixels does not cause problems.
Chip periphery should be close to final :
Timing and location information.
Tuning of shaping/thresholds, changing power.
Readout to an FPGA or equivalent.

10. Large pixel option
It may be possible to have 1 pixel/segment option, i.e. have long 37x800 mm2 pixels.
Naturally, this would influence the amplifier design due to larger capacitance.
However, it might be possible to reduce the capacitance with incomplete filling of the area.
One advantage of the single pixel/segment is no possible issue with the gain matching between different pixels in a segment.

11. Read-out & Interfaces What do we need for Testing ?
The DAQ should not be a limiting factor for testing,
CMOS Common DAQ (For “architectural” submission and later)
“Simple”
Available & Affordable
Avoid duplications
Easy for groups to start testing
Must not be the bottleneck

12. The CASE for HSIO Well know system, a lot of setups exist
As well as Firmware experience
A second generation is being made
Could jump on and get loads of boards (10-15)
Would need to develop CMOS specific Interface Card
Possibly also need a FE carrier board unless it’s functionality is incorporated into the Interface Card
Total Cost
~ 6000 USD (depends on the number of requests in the general call from the whole ATLAS)
30/04/2014
Marcel Stanitzki

13. DISCUSSION
30/04/2014
Marcel Stanitzki

14. Testing Sensors: What would we like to test?
Basic submission :
Amplifier speed and gain
Signal quality
Signal size (drift/diffusion fraction, depletion depth)
Charge collection Speed (drift/diffusion fraction)
Architectural submission: pixel readout along the strip:
Cross talk
General evaluation for both:
Noise
Signal Speed
Depletion Voltage
Power consumption and its interplay with noise and signal speed
Temperature dependence
Radiation hardness
Pixel size optimization
Pixel efficiency map?
30/04/2014
Marcel Stanitzki

15. What tools ? Laser 1064 nm .. Sources 55Fe 90Sr Test beams
DESY/CERN/Focused X-rays at Diamond
30/04/2014
Marcel Stanitzki

16. Radiation damage studies
What
X-rays
Neutrons
Protons
Where
Ljubljana, Karlsruhe, Birmingham …
Main issues
Time for Irradiating & Re-Testing
SHE Issues
30/04/2014
Marcel Stanitzki

17. DISCUSSION
30/04/2014
Marcel Stanitzki

18. Deliverables For discussion:
Define a lead institute for each deliverable – responsible for delivery
Deliverables may be at a global or more segmented scale
Gather team from multiple institutes to work in team
Sensor
AMS350
TOWER
TCAD Model
…..
DAQ/Test
Main Board
Interface mezzanine
Firmware
Software ….
Characterisation
Laser Testing
Source Testing
Beam Tests

19. Countries so far (know to be)expressing Interest
People
Countries so far (know to be)expressing Interest
Note this is NOT exclusive or complete
This is one of an ongoing process of gathering teams
Nevertheless – important to establish that enough effort is available
FTEs dedicated to this programme specifically matter
No time for delays caused by generalising effort to encompass multiple goals
Australia
Germany
USA UK
Slovenia ?

20. Currently Gathered Information on likely Participation
Separate slides

21. DAQ

22. Characterisation