1. Procedure Hopping: a Low Overhead Solution to Mitigate Variability in Shared-L1 Processor Clusters
Abbas Rahimi‡, Luca Benini†, and Rajesh Gupta‡
‡CSE, UC San Diego
†DEIS, Università di Bologna
micrel.deis.unibo.it
International Symposium on Low-Power Electronics and Design 

2. Procedure Hopping to Mitigate CMOS Variability
- How and why we leveraged a high-level concept like “procedure” to solve a problem as low-level as transistor-level?

3. Sources of Device Variation
10% VCC, ~160˚C Temperature, 40% VTH Variations are more challenging in a many-core platform!
guardband
actual circuit delay
Clock
Other
uncertainty
Across-wafer Frequency
Temperature
VCC Droop
1- within-die 3σ performance variation of more than 25% at 0.8V in
2- ITRS projects Vdd variation to be 10% while the operating temperature can vary from -30C to 175C (e.g., in automotive context)
3- Dynamic Variations contain high-frequency and low-frequency components which occur locally as well as globally across the die

4. Agenda Sources of Variations
Variation-tolerant Shared-L1 Processor Cluster
Process Variation → Variation-aware VDD-hopping
Dynamic Voltage Variation → Procedure hopping
Methodology for PLV
Design time characterization
Compile time PLV metadata generation
Runtime preventive compensation
Experimental Results

5. Shared-L1 Processor Clusters
Each cluster consists of:
16 32-bit in-order RISC cores
An intra-cluster shared-L1I$
An on-chip multi-banked tightly coupled data memory (TCDM)
Two single-cycle logarithmic interconnections for both instruction and data sides
A hardware synchronization handler module (SHM) to coordinate and synchronize cores for accessing shared data on TCDM.
VDD-hopping per core.
Shared-L1 TCDM cluster template
- The code is easily accessible via the shared-L1 I$.
The data and parameters are passed through the shared stack in TCDM.
4x8 cluster: 4 PEs and an 8-bank TCDM

6. VDD–hopping to Compensate Process Variation
VDD = 0.81V
VDD = 0.99V
VA-VDD-Hopping=(
0.81V ,
0.99V ) f0
862 f1
909 f2
870 f3
847 f4
826 f5
855 f6
877 f7
893 f8
820 f9
f10
f11
f12
901
f13
917
f14
f15 f0
1408 f1
1389 f2 f3
1370 f4 f5 f6 f7 f8 f9
f10
f11
f12
f13
f14
f15 f0
862 f1
909 f2
870 f3
847 f4
1370 f5
855 f6
877 f7
893 f8 f9
f10
f11
f12
901
f13
917
f14
f15
 Three cores (f4, f8, f9) cannot meet the target frequency of 830MHz.
 All cores of the same cluster meet the target frequency of 830MHz.
 VA-VDD-hopping can accordingly tune the cores' voltage based on their delay reported by CPMs.

7. VDD–hopping to Compensate Process Variation
The process variation is compensated 
but, cluster will have various Voltage/Temperature-islands! f0
862 f1
909 f2
870 f3
847 f4
1370 f5
855 f6
877 f7
893 f8 f9
f10
f11
f12
901
f13
917
f14
f15
Each core increases voltage if its delay is high.
Every core have its own voltage domain
All cores work with the same frequency
VDD-hopping tunes the voltage of each core based on CMP.

8. Fast Dynamic IR-drop within Cluster
(Vol., Temp.)
0.99V, 125C
0.90V, 25C
0.81V, 125C
0.81V, -40C
Power density
0.66 μW/μm2
0.21 μW/μm2
0.18 μW/μm2
0.16 μW/μm2
Max IR-drop
44 mV
< 35 mV
< 31 mV
The IR-drop of execution of FIR on cores with various operating corners.
FIR does not face any voltage emergency (IR-drop < 4%) at the corners with voltages of 0.81V-0.9V due to their lower power densities.

9. Procedure hopping to Compensate Voltage Variation
Each procedure hops from one core to another if it causes voltage variation.
Procedure hopping facilitates fast and proactive migration of procedures within a cluster to prevent voltage variation thanks to shared I$ and TCDM resources.

10. Agenda Sources of Variations
Variation-tolerant Shared-L1 Processor Cluster
Process Variation → Variation-aware VDD-hopping
Dynamic Voltage Variation → Procedure hopping
Methodology for PLV
Design time characterization
Compile time PLV metadata generation
Runtime preventive compensation
Experimental Results

11. Procedure-level Vulnerability (PLV)
The notion of PLV to fast dynamic voltage variation is defined.
The design time stage analyzes the dynamic voltage droops/rises for every ProcX under full operating conditions  generating PLVx metadata.
Observe IR-drops
int ProcX (…) { … } -
(Vi,Tj)
Corei
= 0.75

12. Characterization of PLV to IR-drop: Compile time + Runtime
At compile time, PLVx metadata of ProcX is attached to the procedure.
During runtime, the discretized (V,T) point to the corresponding characterized PLV metadata to assess the vulnerability of ProcX at the current (V,T).
If PLVx ≥ PLV_threshold, the ProcX will be hopped from caller core to a favor callee core.

13. Agenda Sources of Variations
Variation-tolerant Shared-L1 Processor Cluster
Process Variation → Variation-aware VDD-hopping
Dynamic Voltage Variation → Procedure hopping
Methodology of PLV
Design time characterization
Compile time PLV metadata generation
Runtime preventive compensation
Experimental Results

14. Max Voltage Variation Across Corners and Procedures
Max voltage droop (%)
(Vol., Temp.)
a2tim
FIR
IFFT
bitmnp
cacheb
IDCT
matrix
pntrch
PWM
sspeed
tblook
ttsprk
0.99V, 125°C
5.39
4.46
6.34
5.03
4.62
6.26
5.89
5.36
5.23
5.05
3.84
5.41
0.90V, 25°C
3.65
2.98
4.63
3.47
3.11
4.41
4.09
3.63
3.48
2.44
4.99
0.81V, 125°C
3.45
2.8
3.7
3.43
2.92
3.77
3.39
3.27
3.33
2.29
0.81V, -40°C
3.34
2.72
3.66
2.84
3.53
3.26
3.24
2.22
Most of procedures running at cores with 0.99V have voltage emergencies.
At 0.9V, only four procedures (IFFT, IDCT, matrix, ttsprk) face the voltage emergencies.
No voltage emergency at 0.81V.
Procedure hopping avoids the voltage emergency for all procedures by hopping them form a high-voltage core to a low-voltage core.

15. Cost of Procedure Hopping
Caller hopping
Caller not hopping
Callee service
Callee no service
Latency
218 cycles
88 cycles
575 cycles
342 cycles
Voltage droop
1.3%
0.6%
2.9%
1.8%
The total roundtrip overhead of the hopping a procedure from the caller core and returning the results from the callee core is less than 800 cycles.
This overhead is less than 1% of the total cycles needed to execute any of the characterized procedures in EEMBC benchmark.
During the procedure hopping no voltage emergency can occur even at (0.99V,125˚C), neither in the caller nor the callee core.

16. Conclusion
The notion of procedure-level vulnerability to fast dynamic voltage variation is defined.
Based on PLV metadata, a fully-software low-cost procedure hopping technique is proposed which guarantees the voltage emergency-free migration of all procedures, fast and proactively enough within a shared-L1 processor cluster.
Full post-P&R results in 45nm TSMC technology confirms that the procedure hopping avoids the voltage emergency across a variability-affected cluster, while imposing only an amortized cost of less than 1% latency for any of the characterized embedded procedures.

17. Thank you! http://mesl.ucsd.edu http:// micrel.deis.unibo.it

18. HW/SW Collaborative Architecture to Support Intra-cluster Procedure Hopping
The code is easily accessible via the shared-L1 I$.
The data and parameters are passed through the shared stack in TCDM.
A procedure hopping information table (PHIT) keeps the status for a migrated procedure.

19. Intra-procedure Peak Power Variation
Maximum of 1.28× intra-corner peak power variation occurs between IFFT and tblook procedures at (0.81V,125C).
Maximum inter-corner peak power variation is 3.5× for FIR.
Maximum of 4.1× peak power variation across corners and procedures, a2time at (0.81V,-40C), and IFFT at (0.99V,125C).