2. A Uni-bus Data Path Implementation for the SRC
The Data Path
A Uni-bus Data Path
Timing step Generator

3. Review

4. CS501 Advanced Computer Architecture
Lecture12
Dr.Noor Muhammad Sheikh

5. Data
Path
CONTROL

6. 1. The Data Path
The data path is the arithmetic organ of the von Neumann organization
It consists of registers, internal buses, arithmetic units and shifters

7. 2. A Unibus Data Path Implementation
General purpose registers
(32-bits each)
ALSU C A R0
R31 PC IR
32 lines
<31..0>
2. A Unibus Data Path Implementation
MAR
MBR …
ADD
SUB
SHL
Other ALSU functions
Internal processor bus R1
To external CPU bus

8. 3. Timing Step Generator
In the next few slides, we will assume that there exists a “timing step generator” which provides mutually exclusive and sequential timing intervals
These intervals will be called T0, T1, T2, …..

9. Timing Step Generator A possible implementation
A 3-to-8 decoder T0 T1
A 3-bit
binary counter T2 T3 1 T4 2 T5 T6 T7
clear

10. Timing Step Generator Waveforms
Eight mutually exclusive time steps

11. Timing Step Generator Waveforms
If more time steps are required, then a counter with more bits and a larger decoder can be used, eg., a 4-bit counter along with a 4-to-16 decoder can produce up to 16 time steps

12. Structural RTL
Describes how an operation is performed using a particular hardware implementation

13. Structural RTL for the sub instruction
Syntax: sub ra, rb, rc
Step
RTL T0
MAR PC, C PC + 4; T1
MBR M[MAR], PC C; T2
IR MBR; T3
A R[rb]; T4
C A - R[rc]; T5
R[ra] C;
Instruction Fetch
Instruction
Execute
At the end of each sequence, the timing step generator is initialized to T0

14. A Unibus Data Path Implementation
General purpose registers
(32-bits each)
ALSU C A R0
R31 PC IR
32 lines
<31..0>
A Unibus Data Path Implementation
MAR
MBR …
ADD
SUB
SHL
Other ALSU functions
Internal processor bus R1
Recall from previous slide
To external CPU bus

15. Needed for the following instructions/operations
ALSU Functions Needed
ALSU Function
Needed for the following instructions/operations
ADD
add, addi, address calculation for disp and rel
SUB
sub
NEG
neg; applies to the B input of the ALSU
AND
and, andi OR
or, ori
NOT
not; applies to the B input of the ALSU
SHL
shl
SHR
shr
SHC
shc
SHRA
shra
C=B
to load from the bus directly into C
INC4
to increment the PC by 4; applies to the B input;
assuming a barrel shifter with five n<4..0> signals available as well
Use uppercase for control signals, because lowercase was used for mnemonics

16. A Unibus Data Path Implementation
General purpose registers
(32-bits each)
ALSU C A R0
R31 PC IR
32 lines
<31..0>
A Unibus Data Path Implementation
MAR
MBR …
ADD
SUB
SHL
Other ALSU functions
Internal processor bus R1
Question:
What will be the implications if the connection between register C and the internal processor bus is bi-directional ?
(one would like to have such a connection to avoid loading C through the ALSU)
Recall from previous slide
To external CPU bus

17. Structural RTL for the add instruction
Syntax: add ra, rb, rc
Step
RTL
T0-T2
Instruction fetch T3
A R[rb]; T4
C A + R[rc]; T5
R[ra] C;
other instructions that will have similar tables are:
and, or, sub

18. Structural RTL for the not instruction
Syntax: not ra, rb
Step
RTL
T0-T2
Instruction fetch T3
C !(R[rb]); T4
R[ra] C;
another instruction that will have similar table is:
neg

19. Structural RTL for the addi instruction
Syntax: addi ra, rb, c2
Step
RTL
T0-T2
Instruction fetch T3
A R[rb]; T4
C A + c2(sign extend); T5
R[ra] C;
Sign extension for 17-bit c2 is the same as : (15αIR<16> ©IR<16..0>)
Sign extension for 22-bit c1 is the same as : (10αIR<21> ©IR<21..0>)
other instructions that will have similar tables are:
andi, ori

20. RTL for the ld and st instructions
Syntax: ld ra, c2(rb)
Syntax: st ra, c2(rb)
Step
RTL for Id
RTL for st
T0-T2
Instruction fetch T3
A ((rb = 0) : 0, (rb ≠ 0): R[rb]);
A ((rb = 0): 0, (rb ≠ 0): R[rb]); T4
C A + (15αIR<16> ©IR<16..0>);
C A + (15αIR<16> ©IR<16..0>); T5
MAR C;
MAR C; T6
MBR M[MAR];
MBR R [ra]; T7
R[ra] MBR;
M[MAR] MBR;
ld and st are the same up to step T5
sign extension
Note that (15αIR<16> ©IR<16..0>) is the same as (16αIR<16> ©IR<15..0>)