1. Interesting Points of the SPARC Processor
Saunders Roesser
Summer 2002
CS-585-2

2. Outline Quick History Register Windowing Processor Traps Memory Model
Conclusion

3. Quick History
Processor Design based off of the RISC I and II designs as the University of California, Berkeley
First SPARC Processor appeared in 1987 in a SUN MS SUN-4 Computer
1989 – SPARC International Organization Setup

4. Processor Timeline Date Name MIPS MFLOPS 1987 SUN 4 1989
SPARCstation 1
12.5
1.4
1990
SPARCstation2
28.5
4.2
1991
SPARCserver 600MP
1992
SPARCstation 10
1993
SuperServer 6400 – Crap computer
1995
SPARC bit Computer
SuperSparcII is released
1996
UltraSPARC is released
1998
UltraSPARC IIi, Ultra5, Ultra10, Ultra30
1999
Ultra 60, Ultra 80 Processor Release

5. Register Windowing Technique for handling register management
Only a small amount of the total physical register are available at any one time.
Virtual Window slides up and down the register stack to show groups of registers.

6. Register Windowing Two types of registers
General Purpose Registers
Control/Status Registers
Each Processor Part has it’s own set of registers:
Instruction Unit (IU)
Co-Processor (CP)
Floating Point Unit (FPU)

7. Instruction Unit May have between 40-520 Registers 8 Global registers
Divide the rest into Sets
Set contains:
8 local registers
8 in registers
Window Contains:
1 Set (8 local and 8 in)
Plus 8 Out Registers which equal the 8 In Registers of the Next Window

8. Windowing

9. Windowing

10. Traps Error Handling Mechanism in the SPARC architecture
Handle errors, such as overflow, I/O, and instruction errors.

11. Handling Traps Current Window Point is decremented
Information on the trap is stored in the local registers of the window.

12. Types of Traps Precise trap Deferred Trap Interrupting Traps
Error occurs before the instruction is executed
Deferred Trap
Error occurs after the instruction has executed
Can occur after several more instruction have occurred
Interrupting Traps
Error occurred from an event, such as I/O

13. Memory Model Total Store Ordering Partial Store Ordering
Store, Flush, and Load happen in order they were issued
Partial Store Ordering
Issuing order can happen out of order to increase speed.
Hardware Implementation dependent
As long as it appears correct to software
Same model for one processor or mutiprocessor

14. Memory Memory is stored in: Half Word – 2 byte boundaries
Double Word – 8 byte boundaries
Big Endian Architecture

15. Memory Model

16. Conclusion
SPARC has been the most successful implementation of a RISC architecture
Closest competitors have 10 years less experience
Processor is hardwired
PC is read by the CALL or JMPL instructions, not by numbers.