1. CS 352 Introduction to Logic Design
Lecture 8
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Deviation of State Graphs and Tables
Ch-14

2. Outline Alphanumeric State Graph Notation Design of Sequence Detector
More Complex Design Problems
Guidelines for Construction of State Graphs
Serial Data Code Conversion
Alphanumeric State Graph Notation
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3. Design of Sequence Detector (1)
Illustrate design of clocked Mealy sequential circuit (sequence detector):
The circuit examines sequence of 0s and 1s and only when input sequence ending in “101,” it will produce an output Z =1 coincident with the last 1
X = Z = time:
We don’t know how many F/Fs are needed? So we assume two states: S0, S1. Initially circuit is in S0, when input is 1 the circuit go to S1 (as matching string starts with 1) Symbols used are X/Z (input/output)
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4. Design of Sequence Detector (2)
When in S1, if we received input 0, the circuit must change to S2 (last 2 inputs are “10.” If 1 is received in S2 output Z  1
After Z = 1 (circuit do not reset), we should go to S1 as the last input =1 is also first input =1 in the next string match
We do not have complete state diagram yet!
If input =1 in S1, we should stay in S1
If input = 0 in S2, we should go to S0
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5. Design of Sequence Detector (3)
Now we are ready to design a circuit:
Each F/F can have only 2 states, we will need 2 F/Fs (say A and B)
Assume S0: A= 0, B = 0
Assume S1: A = 0, B = 1
Assume S2: A = 1, B = 1
A+ = X’B B+ = X Z = XA
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6. Design of Sequence Detector (4)
From last table  state map for each F/F and Output
If D F/F are used, DA = A+ = X’B DB = B+ = X
Always read Z after the input has changed but before the clock pulse to avoid reading false outputs
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7. Design of Sequence Detector (5)
The derived inputs from last page leads to the following circuit design
The procedure for finding the state graph for a Moore machine is similar to that used for a Mealy machine, except output is written with the state (input) instead of with the transition between states.
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8. More Complex Design Problems (1)
Derive a state graph for a more complex sequential circuit
Output Z = 1 if input sequence ends with “010” or “1001”, otherwise Z = 0
X =
Z =
We start with the 2 sequences that result in Z = 1, then adjust to ensure output is correct for other cases       a b c d e f
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9. More Complex Design Problems (2)
Sequence “010”. If received 1 in S3 (01), that sends back to S2.
Sequence “1001” is added. Start at S0, on receiving 1 go to S4.
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10. More Complex Design Problems (3)
Last page, if received 1 in S5, that should take us back to S2.
Last page, if received 0 in S5, that should take us back to S1.
The procedure for finding the state graph for a Moore machine is similar to that used for a Mealy machine.
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11. Guidelines for Construction of State Graphs (1)
Construct some sample input & output sequence.
Determine under what conditions, if any, the circuit must reset to initial state.
If only 1 or 2 sequences lead to nonzero output, construct a partial state graph for those sequences.
Alternative model: determine what sequences or groups of sequences must be remembered by the circuit and set states accordingly.
Each time you add an arrow, remember if it can go to an existing state or do you need to create a new state?
Verify there is only one path leaving each state for each input combination.
When done, verify set of input sequences
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12. Guidelines for Construction of State Graphs (2)
Find Mealy state graph for a sequential circuit with one input (X) and one output (Z). The circuit examines set of input sequences (“0101”, “1001”) and produce 1 when any occurs. Circuit reset after every 4 inputs. X = Z =
The vertical arrow represents points where the circuit reset.
Input sequence of “01” or “10” followed by “01”  Z = 1   
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13. Guidelines for Construction of State Graphs (3)
Partial state graph leading to state 1 is:
Notice circuit reset on receiving 4th input.
Now we need to add arrows and labels to the graph to take care of sequences which do not give a 1 output, as shown below.
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14. Guidelines for Construction of State Graphs (4)
The addition of S5, S6 were necessary so circuit can reset to S0 before 4 inputs.
Notice that once a “00” or “11” is received (S5), no output 1 is possible till reset happen.
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15. Serial Data Code Conversion (1)
Design a converter for serial data. Clock can be transmitted with the data or we can use Phase-locked loop to regenerate the clock at the receiver.
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16. Serial Data Code Conversion (2)
Coding schemes for Serial Data Transmission:
NRZ: each bit is transmitted for one bit w/o change.
NRZI: For each 0 in the original sequence, bit is transmitted as is. For each 1 in the original sequence, bit is transmitted as the complement of the previous bit transmitted.
Manchester coding: a “0” is transmitted as a 0 for ½ of the bit and 1 for the second1/2. A “1” is the other way around.
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17. Serial Data Code Conversion (3)
Design a sequential circuit which converts NRZ to Manchester coding:
Clock2 is twice the frequency of the basic clock. All changes happen on Clock2 edges. NRZ =1 takes 2 Clock2 cycles.
The above Mealy circuit shows some possible glitches (false outputs). Due to input waveform is not exactly synchronized with clock.
Conversion Network
Timing Chart
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18. Serial Data Code Conversion (4)
Assume Clock2 as our basis, then input is 00 or 11.
Dash in the state table means not specified (don’t care as input never happens).
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19. Alphanumeric State Graph Notation (1)
When a state sequential circuit has several inputs, it is convenient to label the arcs with alphanumeric variable names instead of 0’s and 1’s.
Assume 2 inputs (F: Forward, R: Reverse), and 3 outputs (Z1, Z2, Z3).
If input sequence is all F’s  output is Z1Z2Z3Z1Z2Z3…
If input sequence is all R’s  output is Z3Z2Z1Z3Z2Z1….
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20. Alphanumeric State Graph Notation (2)
Below is the Moore state graph. Arc F means this transition happens when F =1. Z1 state means that output Z1 is 1 and the others (Z2 and Z3) are 0.
When R =1, the state and output sequence occur in reverse order.
We still need to deal with the cases when both inputs are 0 or both are 1?
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21. Alphanumeric State Graph Notation (3)
Solution is to assign priority to inputs!
Assume input F takes priority over input R.
Graph (b) on page (20) implements the priority scheme:
Replace R with F’R, i.e., transition happens when R =1 and F = 0.
Assume F= R = 0, means output will not change (loop F’R’).
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22. Alphanumeric State Graph Notation (4)
We should check if our labeling is properly specified:
If you OR all arc labels, the result should be 1.
F + F’R + F’R’ = F + F’ = 1
If we AND all possible pair of arc labels emanating from S0, we get 0 except one arc label can have value of 1.
F.F’R = 0
F.F’R’ = 0
F’R.F’R’ = 0
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23. Alphanumeric State Graph Notation (5)
A completely specified graph has the following properties:
When we OR all input labels emanating from a state, the result reduces to 1.
When we AND any pair of input labels on arcs emanating from a state, the result is 0.
Prperty-1: ensure that for every input combination, at least one next state is defined.
Property-2: ensure that for every input combination, no more than one next is defined.
In other words, exactly only one next state is defined  graph is properly specified.
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24. END
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