1. Project Custom Designed Integrated Circuits
The purpose of the project is:
To use VHDL to do a circuit design that is suitable to implement in a FPGA.
To use structured design methods.
To use simulations to verify the design. (Test benches).
To synthesize the VHDL code.
To test the designed circuit (FPGA) in a microcontroller environment.
joal 2005 HT:1
Custom Designed Integrated Circuits Em3

2. Custom Designed Integrated Circuits Em3
Project
The students can choose between these alternatives:
UART (Universal Asynchronous Receiver Transmitter) interfaced to a PIC16F84 microcontroller (later to MIPS).
VGA controller interfaced to PIC16F628 (later to MIPS)
If you are not a student from Em3 you can make your own choice of a project
The interface between the microcontroller and the project circuit is specified.
The program in the microcontroller is specified and implemented.
joal 2005 HT:1
Custom Designed Integrated Circuits Em3

3. Custom Designed Integrated Circuits Em3
Project, Test hard ware
FPGA XCS10
OSC
MAX232
PIC16F84
DSUB9
JTAG
IO-port
REG
+ -
DSUB15
joal 2005 HT:1
Custom Designed Integrated Circuits Em3

4. Custom Designed Integrated Circuits Em3
Project, Test hardware
Hyperterminal >?
FPGA XCS10
OSC
MAX232
PIC16F84
DSUB9
JTAG
IO-port
REG
+ -
DSUB15
VGA-monitor
I2C slave
joal 2005 HT:1
Custom Designed Integrated Circuits Em3

5. Custom Designed Integrated Circuits Em3
Project
Design steps:
Design the selected circuit.
Design a test bench.
Verify the design.
Demonstrate the test bench simulations for the supervisor.
Synthesize the circuit and implement it in the test hardware.
Test the design.
Demonstrate the implemented design for the supervisor.
Write a project report and hand it over to the supervisor.
joal 2005 HT:1
Custom Designed Integrated Circuits Em3

6. Custom Designed Integrated Circuits Em3
Project
Assignment reports:
Demonstrate the test bench simulations for the supervisor. Every student must be prepared to demonstrate and explain the simulations and to describe the circuit design and the test bench.
Demonstrate the implemented design for the supervisor.
Write a project report and hand it over to the supervisor.
Passed exam for the project
Gate
Gate
Gate
joal 2005 HT:1
Custom Designed Integrated Circuits Em3

7. Custom Designed Integrated Circuits Em3
Project UART
--*************************************************************
-- Project: uart
-- clk: input clock 4 MHz. The same clock is used for FPGA and
microcontroller.
-- reset: internal signal in FPGA
-- wr: write signal from micro.
-- rd: read signal from the micro. dbus direction from FPGA to micro when
’1’. Statusreg or datareg on dbus when rd=’1’.
-- a0-a1: register selection address lines
-- dbus: bidirectonal data bus. (D0 to D7 in schematics)
entity uart is
port(clk, reset, wr, rd, a0, a1: in std_logic;
dbus: inout std_logic_vector(7 downto 0);
end;
joal 2005 HT:1
Custom Designed Integrated Circuits Em3

8. Custom Designed Integrated Circuits Em3
Project
--*************************************************************
-- Project: uart
-- duplex: full
-- Bitrate: bits/s. Fix baudrate generator 4 MHz to 9600.
-- Data bits: 8
-- Parity: even
-- Stop bits: 2
-- Receiver: Oversampling 16 times
-- Clock: 4 Mhz
-- Address 0: Data register
-- Address 1: Statusregister
-- Address X: address 2-7 not used.
-- Buffers: Only single buffers => write directly to transmit
-- shift register and read directly from receive shift register.
joal 2005 HT:1
Custom Designed Integrated Circuits Em3

9. Custom Designed Integrated Circuits Em3
Project
start
d0 lsb d1 d2 d3 d4 d5 d6
d7 msb
par
stop
stop
Micro
FSM
Receive
Status
Transmit
joal 2005 HT:1
Custom Designed Integrated Circuits Em3

10. Custom Designed Integrated Circuits Em3
Project
statusreg(0) (a0=’1’,a1=’0’)
Receiver ready
reset when data is read from receive-register
statusreg(1) (a0=’1’,a1=’0’)
Transmitter ready
reset when data is put into transmit-register
statusreg(2) (a0=’1’,a1=’0’)
Parity error
reset when correct parity received
Receivereg (a0-a1=’0’)
8 bit data register
Transmitreg (a0-a1=’0’)
joal 2005 HT:1
Custom Designed Integrated Circuits Em3

11. Custom Designed Integrated Circuits Em3
Project
clk
data wr
joal 2005 HT:1
Custom Designed Integrated Circuits Em3

12. Project clk (micro and UART) WR synchronized WR
data is latched in transmitter
joal 2005 HT:1
Custom Designed Integrated Circuits Em3

13. Custom Designed Integrated Circuits Em3
Project
clk (micro and UART) RD
dbus<=receivereg when rd=’1’ and a0=’0’ else statusreg when rd=’1’ and a0=’1’ else (others=>’Z’);
joal 2005 HT:1
Custom Designed Integrated Circuits Em3

14. Pattern and style in Project
Design methodology for project
Don’t build too small or too big entities. (In the project ca 3-5)
Max 4 levels in hierarchy. Structural VHDL is not so easy to understand.
Use state machines (required). Make models with ASM (Algorithmic State Machine)
Use variables only for temporary storage e.g. in algorithms.
Never use variables for e.g. registers.
Use patterns. Look for design examples. A state machine template is an example of a pattern that can improve the design and the readability.
joal 2005 HT:1
Custom Designed Integrated Circuits Em3

15. Project VGA Controller
HSYNC x y
VSYNC
Cursor-sprite 8*8
Cursorpos (xc, yc)
joal 2005 HT:1
Custom Designed Integrated Circuits Em3

16. Project VGA Controller
HSync
Timing control
clk
VSync
reset
Blanking
X(9 downto 0)
Y(8 downto 0)
Xbs(2 downto 0)
Sprite control
Background sprite
PIC16F628
Ybs(2 downto 0) 6 DA
3 VGA
C interface
Xcs(2 downto 0)
Cursor sprite
Ycs(2 downto 0)
joal 2005 HT:1
Custom Designed Integrated Circuits Em3