1. מבנה מחשב
תרגול 3

2. Boolean AND Operation 1 Truth Table Equivalent Gate
Different notations:

3. Boolean OR Operation 1 Truth Table Equivalent Gate
Different notations:

4. Boolean NOT Operation 1 Truth Table Equivalent Gate
Different notations:

5. Boolean NAND Operation
Equivalent Gate
Truth Table 1

6. Boolean NOR Operation
Equivalent Gate
Truth Table 1

7. Boolean XOR Operation 1 Truth Table Equivalent Gate
Different notations:

8. How to implement XOR?
Which is Better?

9. Boolean Equalities (1) Rules of Associativity, Commutation.
Other rules:

10. Boolean Equalities (2)
Distribution
deMorgan

11. Example (1): Simplify the expression
Compare number of gates

12. Example (2): Simplify the expression

13. Evaluating an Expression (1)
Let’s look at the first expression: 1 1 1 1 1

14. Evaluating an Expression (2)
Let’s look at the first expression: 1 1 1 1 =1

15. Truth Table 1
We get Different Notation for 1 1 1 2 1 3 1 1 4 1 1 5 1 1 1 6 1 1 7 1 1 1 1

16. Disjunctive Normal Form1
It’s easy to transform a DNF formula to its equivalent gates’ representation 1 1 1 4 1 1 5 1 1 1 7 1 1 1 1

17. Disjunctive Normal Form
Notation Notice

18. Flip-Flops
What happens if we create a circle in the logic gates diagram?
Consider the following diagram:
This is a
S-R Flip-Flop

19. S-R Flip-Flop
S-R Flip Flop truth table:
Save 1

20. S-R Flip-Flop With a Clock
The CPU is timed by the pulses of a clock.
Maintaining the FF contents when the clock is between pulses (i.e. outputting 0) using the S-R FF:

21. D-Flip-Flop (1) On each clock pulse the FF should be meaningful
Therefore the R and S lines should be opposite
If so do we still need both of them?

22. D Flip-Flop (2)
D Flip-Flop when the clock is pulsing: 1

23. Edge Triggered "D" flip-flop
Clock Q
Latch C
The first latch is called the master, the second latch is called the slave
When the clock goes high, the first D latch (master) accepts the change in input
Because of the inverter, the change is blocked from moving on the second D latch (slave).
When the clock goes low, the slave latch accepts the change in input

24. New Components
Two major components of combinational logic are – multiplexors & decoders.
2-input multiplexor (or selector) is implemented with gates below a b a b c c s s
symbol
gate implementation

25. Multiplexors (MUXes) s
Multiplexors can have any number of inputs (in theory)
Multiplexors can apply to buses  multiplied for many lines.
Example: 1 x 2 multiplexor on 32 bits bus. 1 2 3 4 5 6 7
a31
b31 M
c31 c
a30
b30
3 X 8 multiplexor M
c30 s2 s1 s0 . . 32 a b 32 c a0 b0 M c0 32
symbol s

26. Decoders Each combination of the inputs enables exactly one output
Outputs
Inputs O0 O1 O2 O3 O4 O5 O6 O7 I0 I1 I2 1 1 2 3 4 5 6 7
DECODER
3 X 8 Decoder
Each combination of the inputs enables exactly one output

27. Registers
Registers can be built from a series of ET D latches connected to the same clock
Clock
ET-D
Latch D C Q
. . . D0 D1 D2
D(n-1) Q0 Q1 Q2
Q(n-1)

28. Register File Implementation of double read port read reg 1 reg 2
5 bits
read
reg 1
reg 2
32 bits
M U X
register 0
data 1 2
5 bits
32 bits
read reg 1
read reg 2
write reg
write data
read
data 1
data 2
32 bits
register 1
32 bits
32 bits
5 bits
32 bits
register 30
5 bits
32 bits
32 bits
register 31
32 bits
5 bits
write enable
1 bit
M U X
32 bits

29. Write Port Implementation
write enable
1 bit
1 bit
1 bit
n-to-1
decoder
Clock 1 . 30 31 C D
register 0
5 bits .
register 1
Reg # C D . C D C D
register 30
register 31 C D
write data
32 bits