1. 1 Chapter 5: Datapath and Control CS 447 Jason Bakos

2. 2 Review of Digital Logic Review AND, OR, NOT, and XOR gates Review negative-logic (inverted) inputs and outputs –NAND, NOR, XNOR –Sum-of-products with NAND gates –Product-of-sums with NOR gates “Double-bubble” cancellation DeMorgan’s Law –Completeness of NAND and NOR gates Review of muxes and decoders Boolean algebra equations vs. digital logic gate schematics Review of truth tables –Product-of-sums

3. 3 Review of Digital Logic Logic minimization –Boolean algebra Identity Law –A+0=A and A*1=A Zero and One Laws –A+1=1 and A*0=0 Inverse Laws –A + (not A)=1 and A*(not A)=0 Commutative Laws –A+B=B+A and A*B=B*A Associative Laws –A+(B+C)=(A+B)+C and A*(B*C)=(A*B)*C Distributive Laws –A*(B+C)=AB+AC and A+(B*C)=(A+B)*(A+C) DeMorgan’s Law –not (A+B)=(not A)*(not B) and not(A*B)=(not A)+(not B)

4. 4 Review of Digital Logic –Review Karnaugh Map logic minimization mux2 example –Review “don’t care” logic minimization mux2 example –Review Boolean algebra logic minimization mux2 example

5. 5 Memory Devices Consider cross-coupled NOR gates –This is the most simple memory device, called an SR-flip-flop RSQ+Qb+comment 00QbbQbhold 01100 10011 1100“invalid” Let’s eliminate the S input and provide a clock input In this configuration, the clock acts as an “enable” and is a level sensitive clock

6. 6 Memory Devices Clocked memory devices are divided into two categories: –Latches are level-sensitive devices where the output samples the input the entire time the clock signal is high: Latches are “transparent”, they are open whenever the clock is asserted –Flip-flips only sample the input on the rising or falling edge of the clock We only want state changes on one of the edges of the clock

7. 7 Memory Devices Here’s a master-slave approach to designing a falling-edge triggered FF Here’s a timing diagram for this device

8. 8 Memory Devices Flip flops, depending on their design and technology, have set-up and hold times –Set-up time is the amount of time the input signal (D) must be stable prior to the clock edge that samples it –Hold time is the amount of time the input signal (D) must be stable after the clock edge

9. 9 Memory Devices For the master-slave design, the set-up time was very long, which is why we need a better design –We won’t get into other ways to design edge- triggered flip-flips, but there are many with varying numbers of gates Usually the classic SR-latch acts as a building block for such devices –Flip-flips also have asynchronous sets/resets and sometimes enables –Some textbooks refer to the last design as a “pulse”-trigger flip-flip, since the input must be stable for the entire clock pulse

10. 10 Finite State Machines (FSM) So far we’ve mainly did circuit design with combinational logic systems –Combinational logic circuits have an output that is some function of the inputs Next we’re going to start using sequential systems –Sequential circuits have an output that is some function of the inputs and its input history The first example of these are state machines

11. 11 Finite State Machines (FSM) State machines can be either synchronous or asynchronous –Synchronous state machines only change state with a clock event (edge) –Asynchronous state machines do not have this restriction –We’ll start by building a synchronous state machine We’ll assume we have access to good positive edge triggered D flip-flip cells

12. 12 Finite State Machines Here’s two different representations of the FSM in digital logic:

13. 13 Finite State Machines There are two different ways of designing state machines: Mealy and Moore –In all state machines, the next state (which will be the current state after the next clock edge) is computed as a combinational function of the current state and the inputs –The outputs, on the other hand, are computed either as a function of the current state or as a function of the current state AND the inputs (hence Moore vs. Mealy) Note: Moore is less, because Moore machines are restricted to synchronous outputs (outputs that only change on a clock edge) Mealy machines do not have this restriction

14. 14 Finite State Machines In order to build a state machine, we must first have our input signals and output signals Then we start adding states and transitions –For a Mealy machine, the outputs will be on the transitions –For a Moore machine, the outputs will be in the states

15. 15 Finite State Machines Next, we need to encode state values for each of our states –Try to minimize bit changes on state transitions –Recall: We’ll need lg n flip-flops if we have n states –Then, use Karnaugh maps to minimize our next-state and output logic –Note: we could use a state machine table (truth table)

16. 16 Finite State Machine Examples First, let’s tackle an example –3 bit counter –Outputs: 3 counter bits (no inputs) Here’s another example –Let’s design a combination lock with 2-bit combination inputs and an enter key –The output will be an “unlock” signal Next, let’s do a Coke machine example (where a coke is 35 cents) –Inputs: quarter, dime, nickel –Output: release_coke

17. 17 Registers A register is simply an array of D-flip- flops (8-bit, 32-bit, etc.) The important distinction between flip-flips and registers is that it is VERY important for registers to have enable inputs

18. 18 Wide Multiplexors Wide multiplexors (not an official name) are simply an array of single muxes –For example, if we want a 32 bit 4-to-1 mux, we need to array 32 4-to-1 muxes Using state machine controllers, registers, and muxes, we can very easily implement control for a digital system

19. 19 Example: Checksummer You are to design a device that accepts a data packet comprised of a series of 8-bit words. The packet format is the following: Each 8-bit word is valid on the falling edge of each clock. The synch. characters signal the beginning of a new packet. Synch. character 1 is “00110011” and synch. character 2 is “11001100”. The length field specifies how many words are contained in the data portion of the packet. The data payload is the actual data payload of the packet (which can be anything). Your device will keep a running modulo 256 sum of these data words and compare that value to the value of the checksum field at the end of the packet. synch. character 1synch. character 2lengthdata payloadchecksum 8-bits ‘length’-bytes8-bits

20. 20 Example: Checksummer Your device has the following input signals: –Clock – clock input –DataIn – 8-bit bus that puts a new character out on every falling edge of the clock –Reset – active-high reset The device will have the following output signals: –ChecksumError – this signal will be asserted for one clock cycle following the data input if there is a checksum error in the data packet. I must be valid on the rising edge that defines the end of the checksum word. –DataValid – this signal goes high at the on the rising edge that defines the beginning of the payload and goes low on the rising edge the defines the beginning of the checksum word.

21. 21 Example: Checksummer First, what type of components do we need for this device? How do we design the state machine control? –There’s too many signals to actually implement the controller on the board How do we interconnect this device?