1. RIBF DAQ
Hidetada Baba

2. Topics
FPGA
Time stamp
Dead time
Cluster storage

3. Basic concept Multi crate (multi FEC)
- Parallel readout = dead-time reduction
- Online full event building
(for common trigger)
Common trigger (as far as possible) +
Individual trigger (with time-stamp)

4. BigRIPS FEC (10xFEC) Common trigger B2F B3F Isomer F11 dE, E CAMAC
F7 Ge
CAMAC
CC/7700
F7 dE
CAMAC
CC/7700
F3 dE
CAMAC
CC/7700
B2F
F1-F4,F6 Pl/PPAC
CAMAC
CC/NET
F9-F11 Pl/PPAC T
CAMAC
CC/NET
Master Event Builder
d02
F5 Pl/PPAC
CAMAC
CC/NET
F7 Pl/PPAC
CAMAC
CC/NET
F9-F11 Pl/PPAC Q
CAMAC
CC/NET
F8 Pl/PPAC
CAMAC
CC/NET
B3F
Analysis server
a02
SSM
Scaler
VME CPU

5. BigRIPS+DALI DAQ Common trigger B2F B3F Isomer F11 dE, E CAMAC CC/7700
F8 DALI
VME
F7 Ge
CAMAC
CC/7700
F7 dE
CAMAC
CC/7700
F3 dE
CAMAC
CC/7700
B2F
F1-F4,F6 Pl/PPAC
CAMAC
CC/NET
F9-F11 Pl/PPAC T
CAMAC
CC/NET
Master Event Builder
d02
F5 Pl/PPAC
CAMAC
CC/NET
F7 Pl/PPAC
CAMAC
CC/NET
F9-F11 Pl/PPAC Q
CAMAC
CC/NET
F8 Pl/PPAC
CAMAC
CC/NET
B3F

6. Dead Time (BigRIPS) 150 -- 170 us/event for CC/NET Gate = 0.1 -- 10 us
Conversion = 25 us
Interrupt = 30 us
Readout ~ 100 us
(CAMAC 80 us)

7. with SHARAQ (Nov. 09) Timestamp-based Event building SHARAQ Beam
shvmif6
VMIVME (FEC)
CC/NET (FEC)
Server
shvmif3
shssm
+ TSM
shvmih7
shd01
CCEB
CC Domain
Ethernet
shvmihx
shvmih9
d01
AUEB
SAN
ccnet01
+ TSM
ccnet02
GFS
a02
TSEB
ANAPAW
d02
CCEB
shvmis2
+ TSM
Timestamp-based
Event building
ssm
SHARAQ S2
BigRIPS

8. for beta-decay (Nov. 2009) BGO BigRIPS + RI Beta Ge Ge(DSP) TSEB+
Ext3
Ext3
GFS
TSEB+
Analysis
TSEB+
Analysis
TSEB+
Analysis

9. For you I don’t want to tune the fine timing for each experiment
I need second/minutes range TDC
I don’t need coincident with beam
Measure Isomer without disturbing other trigger
Connect with other facility's DAQ system

10. Time stamp event build (in progress)
Detector section
Group B
Detector section
Group A
Trigger B
From here , I introduce the time stamp based event building.
Each detector section has its event builder.
Trigger is not common for all. Self trigger is available.
To assemble event data, 48 bits 100 MHz Time stamp will be used.
Trigger A
Time stamp
100 MHz, 48bits 10

11. Time stamp event build (in progress)
Gamma DAQ
BigRIPS DAQ
FEC
FEC EB
FEC EB
Gamma
single trigger
From here , I introduce the time stamp based event building.
Each detector section has its event builder.
Trigger is not common for all. Self trigger is available.
To assemble event data, 48 bits 100 MHz Time stamp will be used.
Beam trigger
Time stamp
100 MHz, 48bits 11

12. Time stamp based event build
Timing histogram relative to Beam timing
Coincidence window (Offset and Width) is set by human hands
= Software coincidence
Beam
Gamma
Neutron
To construct event data based on the time stamp.
We make timing histogram relative to beam timing.
This coincidence window is set by human hands.
Offset Width
Time difference
We can change the coincidence configuration after experiments 12

13. Example (Beta decay) T0 = beta beta and veto beta and techno
beta and beam

14. Example (Beta decay) beam and beta beam and veto beam and techno
T0 = beam

15. Example (Beta decay) T0 = beta beta and veto and beam beta and techno
beta and beam

16. Example (Beta decay) T0 = beta beta and veto not beam beta and techno
beta and beam

17. Time stamp module CAMAC and VME Based on FPGA
Not only for the time stamp
Output, Interrupt, Coincidence register
G.G., Scaler, and so on…

18. FPGA + CAMAC/VME Interface
8 LED
CAMAC Interface
(CPLD)
4 NIM IN
Internal
Oscillator
(50 MHz)
CAMAC Bus
16 LVDS /
32 LVTTL
IN/OUT
User FPGA
(Spartan 3E)
This is a picture of this module. CAMAC version.
This large chip is user FPGA.
To simplify CAMAC and VME communication, we installed this auxiliary chip.
Thanks to this auxiliary chip, we can forget the data transfer protocol of CAMAC and VME.
This small chip is interface of CAMAC and VME bus.
4 NIM OUT 18

19. VME module VME Interface (CPLD) 8 LED 4 NIM IN 16 LVDS / 32 LVTTL
IN/OUT
User FPGA
(Spartan 3E)
4 NIM OUT

20. Time Stamp: Clock synchronization
FPGA
25 MHz Clock
DLL
100 MHz clock
25 MHz Clock
Through out
Counter
48 bits depth
Clear
This is a scheme of time stamp module.
We distribute 25 MHz clock for all time stamp module.
And to make 100 MHz clock from this 25 MHz clock, we use delay locked loop circuit in FPGA.
This counter counts this 100 MHz clock.
And according to external trigger, this time value is stored into FIFO memory.
Trigger
FIFO
Memory
VME/CAMAC
Oct. 14, 2009
Hawaii Hidetada RIKEN 20 20

21. Time stamp stability Counting loss = 0 For the moment
Error monitoring mechanism would be better to implement...
Power off, Cable remove...

22. Time Stamp Event Builder
FEC
FEC
FEC
FEC
FEC EB EB
Ether
Shared storage
= SAN + Redhat GFS EB
SAN
off-line
analysis
Raw
Data
Raw
Data TS
Table
TSEB
Data
Raw
Data
Analyzer
This is a design of on-line time-stamp event building.
But I skip details.
TSEB
on-line
analysis 22

23. Not only for time-stamp
Already done
Programmable G.G. (clock sync.)
Trigger selector with VETO
Coincidence register
Output register (clock sync.)
Interrupt register with delay (clock sync.)
NIM <-> LVDS converter
Timestamp with FIFO
Next try
Scaler, preset scaler, rate divider
DMA
TDC !
Time stamp
Output register
Interrupt register
20 man en, CAMAC, VME

24. Development span March decided to develop April-May specification
May-June order
from IT division, 240 man en
other labs, 20 man en / module
End of September delivery
End of October First experiment
BigRIPS + SHARAQ
End of November Second experiment
Beta decay

25. Dead Time (SHARAQ) BigRIPS 200? us/event SHARAQ BLD < 100 us/event
SHARAQ S ? us/event
Trigger rate = << 100 cps
For physics = S2 only (> 90%)
For beam profile = BigRIPS + BLD + S2
<< 10%

26. Good example (Beam trigger)
BigRIPS
SHARAQ BLD
SHARAQ S2
Time stamp

27. Good example (Beam trigger)/
BigRIPS
60000 / 85000
SHARAQ BLD
60 / 2000
Coincidence
= Accepted 3%
SHARAQ S2
Time stamp

28. Dead time simulation 2 DAQ system (CAMAC)
Common trigger, non dead-time sharing

29. Dead time simulation 2 DAQ system
Beam DAQ = Beam x gamma trigger = 1kcps fix (CAMAC)
Gamma DAQ = Gamma trigger = 0 to 100 kcps
V792 + V775 (Event by event readout vs Multi event buffer)

30. Dead time simulation 2 DAQ system
Beam DAQ = Beam x gamma trigger = 1kcps fix
Gamma DAQ = Gamma trigger = 0 to 100 kcps
QTC + CAEN V1190

31. Dead time monitor 1 dead time free system Off-line analysis
Collect all trigger time-stamp
Off-line analysis
Dead time = depends on DAQ combination
BigRIPS
Beta
BGO
Clover

32. Time stamp Short dead time ! Dead time Low trigger rate Fast readout
Simulation
Dead time monitor

33. To do / in progress list Software Hardware Performance measurement
Bug fix (device driver / DAQ controller)
CBLT (VME)
GUI DAQ controller
On-line time stamp event building
Hardware
Monitor/correction mechanism for time stamp
Precise time stamp timing (<< 10ns)
Performance measurement

34. Collaboration MUST2 DAQ + RIBF DAQ Munchen group (beta decay)
with GANIL engineer
Common trigger
Data format + run command translator
Munchen group (beta decay)
Time stamp
Data format ?
New analysis software
Ota (CNS), Takeuchi, Ohnishi, Isobe, Baba

35. Future / more man power DSP de PID Level 2? trigger
Data reduction
Trigger via Ethernet
Absolute time stamp ?

36. Discussion Organization ? Budget Detector DAQ hardware DAQ software
Analysis
Infrastructure
User support
Budget
Infrastructure
Maintenance fee
Development
Short range
Long term