1. Mon. Oct 2 Announcements
Quiz Postponed to Wednesday – still only on 2.a + 2.b
Video lecture for 2.a posted
Lab 6 experiment extension
You must come to lab and demo what you have this week.
If you don’t get it all done, have issues etc… You can demo again during TA office hours next week, without penalty.

2. Module 2.D
Interrupt Handling
Tim Rogers 2017

3. Learning Outcome #2 Bus Timing Analysis
“An ability to interface a microcontroller to various devices”
Bus Timing Analysis
9S12C Multiplexed Bus Expansion
General-Purpose I/O Ports
Interrupt Handling
Buffered I/O
Buffered, Interrupt-Driven Printer Design Example
How?

4. Objective Why? “Interrupt handling”
Polling device drivers waste CPU cycles with polling
transfer data
Much more efficient to just handle the device when it is ready.

5. Basics
Interrupt (definition): An unexpected (asynchronous) hardware-induced subroutine call (may also be referred to as an event or as an exception)
Some circuitry (and/or microcode) – independent of the application - software triggers interrupts

6. Basics
Each Vector is 2 bytes:
Contains function pointer for that interrupt
Vector: Locations in memory that “point to where to go” in order to service an interrupt request, i.e., a pointer to an interrupt service routine (“ISR”)
Off-chip interrupts hook into these vectors
Interrupts can come from on-chip or off chip

7. Context Switching For the 9S12 – the context is our CPU registers.
N equ ?
org $800
main
pshb ; (2)
pshx ; (2)
pshy ; (2)
ldx #XA ; (2)
ldy #YA ; (2)
movw #0,ACM ; rts ; (5)
Context switch to ISR: Stack Registers
interrupt_handler
; some stuff
rti
Context switch to main program: unstack Registers

8. 9S12 stacking order SP HW automatically stacks registers this way
rti will unstack them assuming this order

9. Maskable vs. non-maskable interrupts
Maskable (IRQ or INT)
Non-maskable (NMI)
Can be temporarily ignored by the CPU (aka masked out)
Cannot be ignored by the CPU
Most application interrupts are this way
Usually reserved for catostrophic failures.
Some processors have a hierarchy of these interrupts

10. Prioritization Highest Priority
If more than one interrupt happens at the same time – somebody wins
For 9S12 the address of the vector determines the winner.
Bigger = Higher Priority
Lowest Priority

11. Preemption
Ability of a higher priority interrupt to interrupt a lower priority interrupt
On the 9S12 – the unmaskable and XIRQ interrupts can interrupt the normal user interrupt (IRQ)
More complex application-based preemption requires more interrupt bits beyond the scope of the 9S12

12. Level-Sensitive vs. Edge Sensitive
Interrupt is only active when signal is asserted
Interrupt just needs the signal to pulse
If the device controlling the interrupt only provides a pulse – an external latch must be used.
This latch is called the device flag.
No external latching necessary
Most CPU interrupts are level-sensitive. 9S12’s IRQ line is configurable. We will use it in level-sensitive mode

13. Maskable Interrupt Device Flag
CLR Q D Q

14. Maskable Interrupt Device Flag
Edge-triggered “D” flip flop with asynchronous clear input
CLR Q D Q

15. Maskable Interrupt Device Flag
Edge-triggered “D” flip flop with asynchronous clear input
CLR Q 1 D Q

16. Maskable Interrupt Device Flag
Edge-triggered “D” flip flop with asynchronous clear input
CLR Q 1 D Q
Interrupt Request
(From Device)

17. Maskable Interrupt Device Flag
Edge-triggered “D” flip flop with asynchronous clear input
Flag Clear
(From CPU)
CLR Q 1 D Q
Interrupt Request
(From Device)

18. Maskable Interrupt Device Flag
Edge-triggered “D” flip flop with asynchronous clear input
Interrupt Enable Bit (from CPU)
This is the mask
Flag Clear
(From CPU)
CLR Q
IRQ
(to CPU) 1 D Q
Be able to specify this logic in ABEL or Verilog and realize it on a PLD
Interrupt Request
(From Device)

19. HC(S)12 Interrupt Handling Specifics
Interrupt sources
two interrupt request inputs
IRQ – standard application interrupt
XIRQ – pseudo-non-maskable interrupt
total of over 20 on-chip sources
separate vector for each interrupt and reset source

20. Interrupt CPU bits

21. HC(S)12 Interrupt Handling Specifics
Interrupt control
IRQCR (interrupt control) register
IRQE (bit 7)
“0” – IRQ input pin is (active low) level sensitive
“1” – IRQ input is (negative) edge sensitive
IRQEN (bit 6)
“0” – external IRQ pin disconnected
“1” – external IRQ pin connected
indicates default state after reset

22. 9S12C32 External Interrupt Pins
External interrupt pins are on Port E

23. HC(S)12 Interrupt Handling Specifics
Interrupt masking
application interrupts (including IRQ interrupt input) masked by “I” bit in CC register
“0” – “not masked” (i.e., enabled)
“1” – “masked” (i.e., not enabled)
XIRQ input (non-maskable interrupt input) is masked after system reset by “X” bit in CC register – once enabled, it remains enabled (i.e., the X bit cannot be set by software) until the CPU is reset

24. HC(S)12 Interrupt Handling Specifics
Interrupt masking
most of the HC(S)12 on-chip peripherals have their own interrupt enable/disable bits (control registers with IRQ “mask” or “enable” bits)
external application interrupts may require external device flags and mask registers

25. HC(S)12 Interrupt Handling Microsequence Done Automatically
Hardware
Interrupt
Software
Exception
Mask Bit Set
in CC Register?
Continue
Fetch
Cycle N Y
Stack CPU
Registers
Set “I” (and “X”) Bit(s)
in CC Register
Load Interrupt Vector
into PC
Execute Interrupt
Service Routine

26. HC(S)12 Interrupt Service Routine Structure
Vector to ISR
(CPU microcode – NOT WRITTEN BY YOU)
Start
Clear Device Flag
These are written by you
Service Request
RTI

27. Interrupt Latencies Interrupt Service Latency Time
Interrupt Servicing latency
Time that expires between device asserting and the CPU fetching 1st instruction of the interrupt service routine (ISR).
interrupt_handler
; the first instruction
rti
Instruction completion latency
Processor latency
Device sets flag to “1”
The first instruction of ISR is fetched
Interrupt Service Latency
Time

28. Instruction completion latency
Amount of time it takes the CPU to complete instruction in progress
Most simple CPUs cannot be interrupted mid-instruction
Non-deterministic
Instructions have different time lengths
Interrupts asynchronous with the clock (don’t know when in the clock cycle the interrupt occurs)
However, we can estimate the bound on this value. How?
Instruction completion latency
Device sets flag to “1”
The first instruction of ISR is fetched
Interrupt Service Latency
Time

29. The first instruction of ISR is fetched
Processor Latency
Time between when CPU recognizes interrupt (i.e. after instruction completion latency) and when the first instruction is fetched
Also referred to as the “context switch” overhead
Deterministic – since the context switch always take the same number of cycles
Processor latency
Device sets flag to “1”
The first instruction of ISR is fetched
Interrupt Service Latency
Time