1. Memory and IO Addressing
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2. Contents Memory addressing IO addressing Start address
During memory burst
Linear(Sequential) mode
Cache line wrap mode
Target doesn’t support setting AD[1:0]
IO addressing
General
Decode by device that owns entire IO dword
Decode by device with 8-bit or 16-bit ports
IO address management
When IO target doesn’t support multi-data phase transaction

3. Memory addressing 1/3 Start address During memory burst
dword-aligned address AD[31:2]
During memory burst
On memory access, memory target check AD[1:0].
And determine the policy to use when updating its address counter at the conclusion of each data phase.

4. Memory addressing 2/3 Linear(Sequential) mode Cache Line Wrap Mode
Addressing sequence
Linear, or sequential 1
Reserved. Intel Toggle Mode Addressing
Cache Line Wrap
Reserved
Linear(Sequential) mode
Support multiple data phase
At the completion of each data phase, increments address counter.
Cache Line Wrap Mode
Optional, only used memory read.

5. Memory addressing 3/3 Target doesn’t support setting AD[1:0]
May not implement addressing sequence.
Must respond as follows:
Disconnect with data transfer on the transfer of the first data item.
Disconnect without data transfer during the second data phase.

6. PCI IO addressing 1/5 : identify the target dword of IO space.
General
AD[31:2]
: identify the target dword of IO space.
AD[1:0]
: identify the least-significant byte within th e target dword that the initiator wishes to perform a transfer with.
Decode by device that owns entire IO dword
IO device that implements 32-bit IO port can ignore AD[1:0].
Examples the byte enables in the first data phase.

7. PCI IO addressing 2/5 Decode by device with 8-bit or 16-bit ports
IO target claims the transaction based on the byte-specific start address.
Target must decode full 32-bit IO address.
Byte enable identify
Least-significant byte within the dword
Additional bytes that the initiator wishes to transfer.
Initiator to assert any byte enables of lesser significance than the one indicated by the AD[1:0] setting => illegal
Illegal byte patterns, target must terminates transaction with Target Abort.
(STOP#, TRDY#, DEVSEL#)

8. PCI IO addressing 3/5 AD[31:0] C/BE3# C/BE2# C/BE1# C/BE0# descriptionh 1
Just location 1000h
000095A2h
95A2h and 95A3h h
1510h – 1513h
1267AE21h
1267AE21h – 1267AE23h

9. PCI IO addressing 4/5 IO address management
X86 processor cannot perform IO burst
IN, OUT instruction specifies the AL, AH, AX register as source or destination IO read/write.
Transfer byte, word, dword in each IO instruction
INS, OUTS instruction is burst transaction
A series of back-to-back IO read/memory write or memory read/IO write transaction pairs
Burst IO address counter management
Unlike memory, in PCI there is no explicit or implicit IO address sequencing from one data phase to the next.

10. PCI IO addressing 5/5
When IO target doesn’t support multi-data phase transactions
Target check FRAME#, IRDY# in the first data phase.
=> can detect multi-data phase.
Must respond in one of two ways
Terminate the first data phase with a disconnect with data transfer(STOP# and TRDY# asserted)
Terminate the second data phase with a disconnect without data transfer(STOP# asserted, TRDY# deasserted)