1. Simulation of Power Electronic Systems Using PSpice
Presented by Nik Din Muhamad

2. Presentation Outlines
In order to use Pspice for power electronic systems, we have to:
Know background of SPICE
Understand Power Electronics Circuits/Systems
Know how to use VPULSE to generate useful waveforms
Know how to make simple models using ABM

3. Scope This presentation covers: PSpice System/Circuit Level Simulation
Power Electronic Circuits/Systems
Simulation

4. SPICE/PSpice Did you know? SPICE turns 38 years old this year
I Knew SPICE when she was 17 years old
I love PSpice because she can do almost anything I need with FOC.
I like to talk about her.

5. Why simulation?
Simulations are essential ingredients of the analysis and design process in power electronics:
Saving of development time
Saving of costs (‘burnt power circuits tend to be expensive’)
Better understanding of the function

6. … continued
Testing and finding of critical states and regions of operation (Worst Case Analysis)
Stress test (Smoke Analysis)
Optimization of system
Testing new ideas

7. Overview
Simulation of analog circuits normally uses three basic tools:
SPICE simulator,
Mathematical analysis package,
and Microsoft Excel.

8. SPICE Simulation Program for Integrated Circuit Emphasis
Intended for ICs, not for power electronics.
Uses iterative Newton-Raphson Algorithm
to solve a set of nonlinear equations.

9. SPICE LIMITATIONS
The Newton-Raphson algorithm is guaranteed to converge if the equations is continuous.
The transient analysis has the additional possibility of unable to converge because of the discontinuity in time.

10. SPICE LIMITATIONS Computer Hardware Limitation:
Voltage and currents are limited to +/-1e10.
Derivatives in PSpice are limited to 1e14.
The arithmetic used in PSpice is double
precision and has 15 digits of accuracy.

11. Power Electronic Circuit
Power electronic circuits are characterized by switching on and off of power semiconductor switches; the generated waveform is passed through inductors and capacitors for filtering.

12. Power Electronic Circuit
Due to switching action of the switch, discontinuity (in circuit variables and in time) can easily occur during simulation, which leads to convergence problem.
“Avoid discontinuity”

13. Discontinuity Analogy: A Bump on the Road
Unacceptable Bump
Acceptable Bump
“Whole car shakes when I hit a bump on the road”
PSpice doesn’t like discontinuity as we don’t like a bump on the road.

14. Avoid Discontinuity VGS VGS t t
All signals must be made ‘less discontinuous’
All relationships must be continuous

15. VPULSE Waveform generator
SAWTOOTH
TRIANGULAR

16. VPULSE Waveform generator
In order to use PSpice for power electronic circuits, the first thing you have to know is to program VPULSE to produce these waveforms:
PULSE
Sawtooth
Triangular

17. VPULSE Waveform Generator Part
has 7 parameters to set
TD can be zero, others can not!
V1=
V2=
TD=
TR=
TF=
PW=
PER= PW V2 TR TF TD V1
PER
know what parameters to adjust and to fix.

18. VPULSE To Generate Pulse Waveform
Very small values for TR and TF
Duty cycle = PW/PER PW
V1=0
V2=12
TD=0
TR=10n
TF=10n
PW=10u
PER=20u V2 V1
TR ≈ 0
TF ≈ 0
PER

19. A Typical application Buck Converter (Open Loop)
A Pulse waveform is used to drive a MOSFET ON and OFF.

20. Its Pulse (I)
V1=0
V2=12
TD=0
TR=10n
TF=10n
PW=10u
PER=20u
Duty Cycle,

21. Its Pulse (II) V1=0 V2=12 TD=0 TR=10n TF=10n PW=5u PER=20u
Duty cycle of the waveform is adjusted by adjusting PW

22. VPULSE To Generate Sawtooth
Very small values for TF and PW
TR≈PER
V1=0
V2=12
TD=0
TR={20u-20n}
TF=10n
PW=10n
PER=20u TR PW TF
PER

23. A Typical application Buck Converter (Closed Loop)
Gate Driver
Comparator -
Sawtooth
Gen. +
For Closed-loop, the control signal is compared with a sawtooth waveform to produce the pulse waveform.
Control
Signal

24. PSpice Implementation
Comparator
Control
Signal
Gate Driver
Gate Driver  E
Comparator  ETABLE
Sawtooth VPULSE
Control  VDC
Vpulse

25. Its Waveform (I)
Sawtooth
Control
Pulse
D = 50 %

26. Its Waveform (II)
Sawtooth
Control
Pulse
D = 33%
Duty Cycle of the Pulse is adjusted by adjusting Control Signal.

27. VPULSE To Generate Triangular wave
Very small value for PW
TR≈TF ≈ PER/2 PW
V1= -1
V2= +1
TD=0
TR= {10u-10n}
TF= {10u-10n}
PW=20n
PER=20u TF TR
PER

28. VPULSE Its Triangular Wave

29. Triangular Wave Typical applications
Bipolar SPWM
Comparator

30. Triangular Wave Typical applications
Bipolar SPWM
1.0V 0V
-1.0V
V(TRI)
V(SINE)
100
-100
40ms
42ms
44ms
46ms
48ms
50ms
52ms
54ms
56ms
58ms
60ms
V(SPWM)
Time [ms]

31. Triangular Wave Typical applications
Unipolar SPWM
Comparator 1
Comparator 2

32. Triangular Wave Typical applications
Unipolar SPWM
Time [ms]
40ms
42ms
44ms
46ms
48ms
50ms
52ms
54ms
56ms
58ms
60ms
V(A)-V(B)
-100V 0V
100V
V(SINE1)
V(SINE2)
V(TRI)
-1.0V
1.0V

33. Analog Behavior Model (ABM) Makes the Circuit Simpler Use equations to model circuits
Comparator
Single Phase Rectifier
Three Phase Rectifier
Buck Converter in CCM
Single Phase Inverter

34. ABM Behavior Model of Comparator-
V(-)
V(out) +
V(+)
IF the voltage at the terminal V(+) is greater than the voltage at terminal V(-) the output V(out) is HIgh, otherwise the output is LOw.
IF(V(+)>V(-),HI, LO)
(1) Using IF-Then-Else function
(2) Using signum function
(V(+)-V(-))/ABS(V(+)-V(-))

35. ABM Behavior Model of Comparator-
V(-)
V(out) +
V(+)
(3) Using I/O graph
V(+)-V(-)
V(out)
(4) Using Op-amp alike
V(+)
V(-) + -
A*(V(+)-V(-))
V(out)

36. ABM Comparator in PSpice1 2 3
NO 2 is implemented using ETABLE
Others are implemented using ABM part
NO 2 & NO 4 are suitable for Op-amp (Error Amplifier) 4

37. ABM Behavior Model of Comparator
Time [ms]
40ms
42ms
44ms
46ms
48ms
50ms
52ms
54ms
56ms
58ms
60ms
V(OUT3)
V(OUT2)
V(OUT1)
V(OUT4)
-10V 0V
10V
V(TRI)
V(SINE)
-1.0V
1.0V
These waveforms come from the outputs of four comparators

38. ABM Behavior Model of Rectifier (I)
V(out)=ABS(V(IN))

39. ABM Behavior Model of Rectifier (II)+
Van
V(out) = 0.5*(ABS(V(an)-V(bn)
+ABS(V(bn)-V(cn))
+ABS(V(cn)-V(an)))
Vbn
Vcn -

40. ABM Behavior Model of Buck in CCM+ Vd
Vd = d*Vin - + - Vd
d is a PWM signal with 1V amplitude.

41. ABM Behavior Model of Inverter+
VDC
Vab -
Bipolar SPWM + - E1
VDC*(V(%IN+)-V( %IN-))/ABS(V(%IN+)-V( %IN-))
EVALUE
OUT+
OUT-
IN+
IN-
SINE
TRI
Vab b

42. #TIPS
There are many different ways to model the same thing. So, be creative!
Use a simple model wherever possible to reduce modeling time and make simulation run faster and converge better!

43. Quote about Model !
“Models are like shoes; there is no one-size- fits-all model.”

44. Our Case Study A Buck Converter with VMC
A Simple PWM Controller IC Model
A PWM IC Controller IC Model including Soft-start
A PWM IC Controller IC Model Including Soft-start, Duty Cycle Max and Current Limiter

45. Our Case Study A Buck Converter with VMC+ - + -
SG3525
PWM Controller IC

46. SG3525 PWM Controller IC Key Functions:
Oscillator (Sawtooth Generator)
PWM Comparator
and SR Flip-flop
Error Amplifier
5.1 V Reference
Pulse Steering Logic
Shutdown and Soft-start Circuitry

47. SG3525
We do not need to have SG3525 model in PSpice’s library to simulate buck converter with VMC.
To verify the controller design, all we need are functional models of these:
Error Amplifier
Comparator
Sawtooth generator

48. SG3525 A Simple Model Sawtooth To MOSFET + Driver - Comparator
Error Amp.
Comparator

49. A Buck Converter with VMC
Consider we know all circuit parameters.
Our interest is to simulate the system.
The controller is used to regulate the output voltage at 5 V.
Error Amp.
Comparator
Sawtooth

50. A Buck Converter with VMC
The controller is a linear controller and the design is based on a small-signal model.
So, the controller can not cope with large signal scenario such as start-up.
Initial values, which are equal to their steady state values, for the inductor current and the capacitor voltage must be set.

51. Load Disturbance How to set a load disturbance ?
Let the load disturbance is: 3A
1 A
R = 5 W
0 A
8 ms
8.5 ms
R = W
R = 5 W
R is changed from 5 W to W

52. 1 Our Case Study How to set load disturbance ? Using IPULSE
ILOAD 1
Allocate enough times for TR and TF

53. 2 Load Disturbance How to set load disturbance ?
Using SW_tclose and SW_topen 2
5//2.5 =1.666

54. Load Disturbance: PSpice

55. Load Disturbance: Results
Time [ms]
7.8ms
7.9ms
8.0ms
8.1ms
8.2ms
8.3ms
8.4ms
8.5ms
8.6ms
8.7ms
8.8ms
I(L1)
I(ILOAD) 0A
2.0A
4.0A
V(OUT)
4.8V
5.0V
5.2V
Inductor Current
Output Voltage

56. Input Disturbance How to set an input disturbance ?
Let the input disturbance is:
0 V
15 V
25 V
8 ms
8.5 ms

57. Input Disturbance How to set an input disturbance ?
Use VPWL (Piece-Wise Linear Voltage Source)
25 V
15 V
0 V
8 ms
9 ms
PWL(T1,V1)(T2,V2)(T3,V3)(T4,V4)(T5,V5)
PWL (0,15) (8m,15) (8.0001m,25) (9m,25) (9.0001m,15)

58. Input Disturbance Responses Input Voltage Output Voltage
Time [ms]
7.8ms
8.0ms
8.2ms
8.4ms
8.6ms
8.8ms
9.0ms
9.2ms
9.4ms
9.6ms
9.8ms
10.0ms
I(L1) 0A
1.0A
2.0A
V(OUT)
4.8V
4.9V
5.0V
5.1V
V(INPUT)
10V
20V
25V
30V
Input Voltage
Inductor Current
Output Voltage

59. Start-up Scenario Previous simulation skips start-up scenario.
To know how the controller handles start-up, set the initial values for iL and vc to zero. 20 15
Inductor Current 10
Output Voltage 5 0s
100us
200us
300us
400us
500us
600us
700us
800us
I(L1)
V(OUT)
Time [ms]

60. Start-up Scenario
A very large overshoot and undershoot occur in inductor current.
The duty cycle is at first at 1 for a long time and later at 0 for a long time too, then after that it gradually increases.
Convergence problem can easily occurs at this extreme condition.
Time 0s
100us
200us
300us
400us
500us
600us
700us
800us
I(L1)
V(OUT) 5 10 15 20
V(E1:1) 0V
2.5V
5.0V
Gate Signal

61. Start-up
In practical circuit, another auxiliary controller is required to handle start-up.
This circuit is known as soft-start.
Soft start
Controller
VMC
Controller
Time [ms] 0s
100us
200us
300us
400us
500us
600us
700us
800us
I(L1)
V(OUT) 5 10 15 20
V(E1:1) 0V
2.5V
5.0V
Gate Signal
Soft-start circuit works by gradually increasing the duty cycle. So do the inductor current and capacitor voltage.

62. Soft-start To add Soft-start
The previous PWM IC model is very useful and it is simple to set-up in PSpice.
It is enough to verify the design of controller based on small signal model.
However, to add soft-start controller and other protection circuits, we need a more flexible PWM IC model.

63. A Modified PWM IC Model R S
Oscillator - + Q
Sawtooth
Clock
Error Amp.
Comparator
SR Flip-flop
The output of SR flip-flop is set by the Clock.
The output of SR flip-flop is reset by Comparator.

64. A Modified PWM IC Model
Oscillator
Clock
Sawtooth
Error Amp.
SR Flip-flop
Comparator + + S - R - Q - R
Analog
Signals - R
Digital
Signals
Analog signals can be added at minus terminals of the comparator.
Digital signals can be added at the input Resets of FF.

65. Soft-start To add Soft-start Signal
Sawtooth +
Error Amp.
Output
To R of SR Flip-Flop -
Control Signal -
Soft-start
Sawtooth is still compared with the control signal.
But, Control Signal can be either Error Amp. output (EAO) or Soft-start signal (SS), whichever is lower.

66. Soft-start To add Soft-start SignalC
50 mA
Sawtooth +
Soft-start (SS)
To R of SR Flip-Flop -
Error Amp.
Output (EAO) -
The soft-start voltage is the capacitor voltage.
The capacitor C is charged by a constant current source of 50 mA. The result is a ramp voltage.
C determines the duration of soft-start.

67. Soft-start How Soft-start works?
Soft-start Voltage
4 V
Slope = C
50 m
C = 125 nF
10 ms t
Use PWL to emulate soft-start voltage
For the graph, PWL(0,0)(10ms,4V)

68. Soft-start To add Soft-start Signal
Sawtooth +
50 mA SS
To R of SR Flip-Flop
Control
Signal -
EAO C
Selector
We need a selector to select either SS or EAO, whichever is lower, to be Control Signal.
We can use IF-Then-Else function
IF(SS < EAO, SS, EAO)

69. Soft-start In PSpice Error Amplifier SELECTOR IF-Then-Else Vout
Comparator
Sawtooth
Generator

70. Soft-start Start-up Signals
Control = IF(SS < EAO, SS, EAO)
5.0V
Error Amplifier Output
2.5V 0V
5.0V
Soft-Start Signal
2.5V 0V
2.0V
Control Signal
1.0V 0V 0s
1.0ms
2.0ms
3.0ms
4.0ms
5.0ms
6.0ms
Time [ms]

71. Soft-start C = 125 nF (Too Small!)
7.5V
5.0V
tstart-up = 1ms
V(OUT)
2.5V 0V
4.0A
I(L1)
2.0A 0A 0s
1.0ms
2.0ms
3.0ms
4.0ms
5.0ms
6.0ms
Time [ms]
Soft-start signal ramps up too fast

72. Soft-start Start-up Current and Voltage
Time [ms] 0s
1.0ms
2.0ms
3.0ms
4.0ms
5.0ms
6.0ms
I(L1) 0A
1.0A
2.0A
V(OUT) 0V
2.5V
5.0V
7.5V
C = 25 nF
tstart-up = 3.2 ms
Still has a small overshoot and undershoot in inductor current
has a room for improvement by increasing C.

73. Soft-start Start-up Current and Voltage
Time 0s
5ms
10ms
15ms
20ms
25ms
30ms
35ms
I(L1) 0A
1.0A
2.0A
SEL>> 0V
2.0V
4.0V
6.0V
V(OUT)
V(OUT)
I(L1)
C = 125 nF ; Start-up time is 30 ms.

74. A Modified PWM IC Model To add digital signals for protection.
Oscillator
Clock
Sawtooth
Error Amp.
SR Flip-flop
Comparator + + S - R - Q - R
Analog
Signals - R
Digital
Signals
To add digital signals for protection.
For examples, Maximum Duty Cycle and Current Limiter
Flip-flop can be reset either by PWM comparator, or Maximum duty cycle, or Current Limiter.

75. To Add Digital Signals DutyMax and CurrentLimit
Maximum duty cycle limiter is in digital form. It can be applied directly to the Reset of FF.
The switch current (or inductor current) must be compared with its limit value to produce a digital signal.
RESET 3 (DMax)
RESET 2 (CL)
SET
RESET 1 (EAO)
Set only by one i. e. the clock
Reset can be done by three, whichever comes first.

76. To Add Digital Signals DutyMax and CurrentLimit
Time 0s
20us
40us
60us
80us
100us
120us
140us
160us
180us
200us
V(SAWTOOTH) 0V
2.0V
4.0V
V(DUTYMAX)
2.5V
5.0V
V(S)
DUTYMAX
CLOCK
SAWTOOTH
DUTYMAX signal will only reset FF if the duty cycle is more than 0.85
This DUTYMAX is to make sure that the MOSFET always turns-off for each cycle
CurrentLimit signal will only appear and reset FF if the peak switch is greater than pre-specified value.

77. To Add Digital Signals DutyMax and CurrentLimit
Time
5.6ms
5.7ms
5.8ms
5.9ms
6.0ms
6.1ms
6.2ms
6.3ms
6.4ms
6.5ms
6.6ms
V(OUT)
I(L1) 5 10
We want to limit this current at 8A
Output Voltage
Inductor Current

78. To Add Digital Signals DutyMax and CurrentLimit
What do we expect ?
5.6ms
5.7ms
5.8ms
5.9ms
6.0ms
6.1ms
6.2ms
6.3ms
6.4ms
6.5ms
6.6ms
V(OUT)
I(L1) 5 10
Output Voltage
Inductor Current
8A Limiter
Reset by EAO
Reset by
CurrentLimit
Reset by
DutyMax
Reset by EAO
Time

79. To Add Digital Signals DutyMax and CurrentLimit
5.0V
2.5V 0V
V(CLOCK)
5.0V
2.5V 0V
V(PWMCOMP)
V(Q)
5.0V
2.5V 0V
V(CURRENTLIM)
V(Q)
5.0V
2.5V 0V
5.90ms
5.95ms
6.00ms
6.05ms
6.10ms
6.15ms
6.20ms
V(DUTYMAX)
V(Q)
Time [ms]
A Load disturbance
at 6.0 ms

80. Knowing
“There is no substitute for knowing what we are doing”

81. CONCLUSION In order to simulate power electronic circuit:
Know how to program VPULSE for Pulse, Sawtooth, and Triangular waveforms.
Avoid discontinuity at any cost
Use the simplest model possible
Use a simple model first, and add complexity in stages.
No replacement for good understanding

82. Q & A