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Digital Design Jeff Kautzer Univ Wis Milw
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Review: Digital Information
Information is represented numerically using a binary number system An n bit number has digit weightings 2(n-1) 2(n-2) 2(n-3) …… Example: b = = 26 4 bit binary “nibbles” are abbreviated using hexidecimal 1001b = 9h, 1010b = Ah, 1011b = Bh, … b = Fh Logic 1: Represented by a high voltage level and/or forward current Logic 0: Represented by a low voltage level and/or reverse current Binary numbers are conveyed individually in time between two or more digital devices. Devices have electrical limitations in drive, speed, distance, & fanout Devices may share the same wires/nodes using time based multiplexing
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Review: Basic 2 Input Logic Operators
Gates and their Demorgan Equivalents Note: A Bubble implies logic inversion
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Review: Basic 2 Input X-OR Operators & Gates
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Review: Truth Tables, Karnaugh Maps
Grey Code
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Example: Binary-7Segment Display Decoder
2 Types of Display Configurations Vcc Common Cathode LEDS Active High Common Anode LEDS Active Low Gnd
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7- segment used to form digits 0-9
7 Segment Display 7- segment used to form digits 0-9
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Commercial TTL BCD-to-7-segment decoder/driver driving a common-anode 7-segment LED display; 7447 segment patterns for all possible input codes.
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Truth Table for Active High (Common Cathode Display Drive)
Hex Digits A-F not defined by this decoder. All Segments OFF
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Truth Tables and MIN Terms
Each line in the Truth Table is Represented by a “MIN” Term Each MIN Term is a Full Expression containing each input variable For Output “a” the following MIN Terms would be Logically “OR”d D C B A D C B A D C B A D C B A D C B A D C B A D C B A D C B A Note: X = NOT X Output a = D C B A + D C B A + D C B A + D C B A + D C B A + D C B A + D C B A + D C B A
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Truth Table Reduction Two MIN Terms can be combined if the same output is obtained but the input variable values differ in only 1 bit position. The variable for which the value differs with no effect on output is eliminated from the resulting expression. D C B D C B C B A D C B
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Combining Adjacent Cells (Min Terms) Reduces Logic Implementation
Output a = D C B A + D C B A + D C B A + D C B A + D C B A + D C B A + D C B A + D C B A 8 Min Terms …. 1 Eight Input OR Gate Four Input AND Gates Inverters Total of 9 Four Input Gates + 4 Inverters Karnaugh Map Combinations A C B D A C D Output a = B D + C D + A C + A C D 8 Min Terms …. 5 Four Input Gates Inverters Total of 8 Gates, Smaller Gates with Fewer Inputs C D
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Additional Segment Maps
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Liquid-Crystal Displays
Liquid-crystal display: (a) basic arrangement; (b) applying a switching voltage between the segment and the backplane turns ON the segment. Zero voltage turns the segment OFF.
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Commerical Logic devices for driving an LCD segments and full 7-segment displays
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Common XOR Reduction Patterns
(Alternating Columns, Quads, and Pairs, Checkerboards)
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Digital IC Technologies/Families
Bipolar: Utilizes BJT’s exclusively as switching elements. Originated by Fairchild/TI, families have included STD, L, H, LS, S, ALS, AS and F pp74xxx###P Standard Part Numbering Scheme Package Suffix (Plastic, Ceramic, DIP, SOJ, etc) Generic Device Function Number (Ex. 244 Octal Driver) Family Designation (Ex. ALS, AS, F, etc) 7 =Commercial (0-70C), 5 =Military (-55 to 125C or more) Mfg Prefix (Ex. SN = Texas Inst, DM = Fairchild, etc) Example Function/Family Package Options For Family Examples see:
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Active Bipolar Logic Families
ALS Advanced Low-Power Schottky Logic AS Advanced Schottky Logic F Fast Logic LS Low-Power Schottky Logic S Schottky Logic TTL Transistor-Transistor Logic (STD)
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Review: Schottky Diode
PN Junction Si Diode Similar to std diode Low Forward Voltage Drop (~0.3V) C B E Schottky Transistor Schottky Diode from Collector to Base of NPN switching transistor Vbc < Vf of Schottky Diode (~0.3V) Vce-sat (schottky) > Vce-sat (std BJT) Base-Collector Clamp prevents hard saturation Switches Faster as a result
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Digital IC Technologies/Families
CMOS: Utilizes C-MOSFETs exclusively as switching elements. Originated with 4000 series family (still produced) followed with C, HC, HCT, AC, ACT, FCT, LV, LVC and many others (see list) Devices follow Bipolar part numbering scheme (except for 4000 series) Characterized by Very low input current (leakage current) Symmetric Output drive currents Device size/process scales. Industry has moved from 5um channels to less than 75nm channels in < 30 yrs Example: HC, HCT Families Function/Family Package Options
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ACTIVE CMOS Logic Families
Advanced CMOS Logic (1.5 to 5.5V typ) ACT Advanced CMOS Logic AHC Advanced High-Speed CMOS (2.0 to 5.5V typ) AHCT Advanced High-Speed CMOS ALVC Advanced Low-Voltage CMOS Technology (2.3 to 3.6V typ) AUC Advanced Ultra-Low-Voltage CMOS Logic (0.8 to 2.7V typ) AUP Advanced Ultra-Low-Power CMOS Logic (0.8 to 2.7V typ) AVC Advanced Very-Low-Voltage CMOS Logic (0.8 to 2.7V typ) CB3Q Low-Voltage, High-Bandwidth Bus Switch Technology CB3T Low-Voltage, Translator Bus Switch Technology CBT Crossbar Technology CBT-C CBT with Undershoot Protection CBTLV Low-Voltage Crossbar Technology CD4000 CMOS Logic (4000 Series, 3 to 18V typ) FCT Fast CMOS Technology GTLP Gunning Transceiver Logic Plus HC High-Speed CMOS Logic (2.0 to 6.0V typ) HCT High-Speed CMOS Logic LV-A Low-Voltage CMOS Technology (2.0 to 5.5V typ) LV-AT Low-Voltage CMOS Technology LVC Low-Voltage CMOS Technology (1.6 to 3.6V typ) PCA Inter Integrated Circuit PCF SSTV Stub Series Terminated Low-Voltage Logic TVC Translation Voltage Clamp VME VME Bus Products
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Other Digital IC Semiconductor Technologies
BiCMOS: Combination CMOS/BJT. Can be implemented using Si but SiGe becoming popular for mixed signal applications. Families include: HSTL, BCT, FB, ABT, ALB, LVT and others (see list) ECL/LVDS: Emitter Coupled Logic / Low Voltage Differential Signaling. Si BJT or CMOS devices that utilize differential signaling with extremely low voltage swings. Typically seen on the output from A/D conversion circuits. Switching speeds > 60Mhz. GaAs: FET based devices with extremely fast switching and delay characteristics. Ft > 10Ghz easily achievable. Costs > 20X that of fast CMOS
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Active BiCMOS Logic Families
ABT Advanced BiCMOS Technology ABTE Advanced BiCMOS Technology / Enhanced Transceiver Logic ALB Advanced Low-Voltage BiCMOS (3.0 to 3.6V typ) ALVT Advanced Low-Voltage CMOS Technology (2.3 to 3.6V typ) BCT BiCMOS Technology FB Backplane Transceiver Logic GTL Gunning Transceiver Logic HSTL High-Speed Transceiver Logic JTAG JTAG Boundary Scan Support LVT Low-Voltage BiCMOS Technology (2.7V to 3.6V typ) SSTL Stub Series Terminated Logic
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Other Aspects of Technology: Component Life Cycle Phases
= Mean (Max) Sales of Unit Components per Unit Time s = One Standard Deviation in Sales/Time
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Life Cycle of a Component
Special Histogram of Production as Measure by Component Sales/Time (# shipped/time) Concept Assumes Component Sales follow monotonically increasing to peak, then monotonically decreasing to obsolesence Life Cycle is Measured Relative to Peak of Sales +/- 1s from Peak = Mature Product -1s to –2s from Peak = Growth Product -2s to –3s from Peak = Introductory Product +1s to +2s from Peak = Declining Product +2s to +3s from Peak = Phase Out Product +3s and higher from Peak = Obsolete Product
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Logic Signal Electrical Characteristics
Finite Transition Time Zone Driver must switch voltage thru this zone within specified time or risk causing linear operation of receiver ! Typically < 1uS but varies with logic family technology
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Logic Device Drive Parameters
Note: Sourced currents are always listed as a negative number by convention on data sheets
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Interpreting the Data Sheet
Vih, Vil Ioh, Iol Ioh (note max Ioh) Iol (note max Iol) Iih, Iil
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Device Output Structure Type 1: Totem Pole
Current Limiting Resistor (reduced in modern devices) Top Voh/Ioh Source Driver (Switch to Vcc) Bottom Vol/Iol Sink Driver (Switch to Gnd) Cross-over of Q4:Q5 – ON/OFF may result in high current spike from Vcc to Gnd Octal and larger devices rated for “Gnd Bounce” Volp. Measure of Static output disturbance when all other outputs switch simultaneously.
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Device Output Structure Type 2: Open Collector/Drain
Current Limiting Resistor Removed Top Voh/Ioh Source Driver Removed Bottom Vol/Iol Sink Driver Sink Trans Q5 acts as a switch to Gnd No inherent Logic 1 voltage drive Interface in 2 ways; Pullup resistor to Vcc to establish logic 1 voltage level Switch current through load device (Ex. Relay Coil, LED, Lamp, Solenoid, etc) Note OC/OD Datasheets: May list Vce-sat for Vol, Ic max for Iol max, Vce max (off). Will NOT list Voh, Ioh values ! OC/OD Outputs will have very slow Logic 0 to 1 transition times !
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OC/OD outputs may be tied together, Wire-OR
Determining Pullup Resistor Limits Maximum R - Limited by Logic 1 condition: R must supply Iih to receiver plus supply any leakage current to the driver OFF transistors. Finite Current of Io flows thru R dropping voltage. Usually use R < 100KW Minimum R - Limited by Logic 0 condition: Driver ON may cause Vol as low as 0V, Driver must sync Io from Vcc thru pullup resistor plus Iil source current from receiver. Total load current cannot exceed Driver Iol current capacity. Usually use R> 1KW
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Device Output Structure Type 3: Tristate-able
Current Limiting Resistor (reduced in modern devices) Top Voh/Ioh Source Driver (Switch to Vcc) Bottom Vol/Iol Sink Driver (Switch to Gnd) Q7/Q8 used to stop base current to Q3/Q4 darlington Turn off Source Driver Q2 used for same purpose but controls Sink Driver E turns OFF Q4 and Q5 simultaneously
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Interpreting the Data Sheet
Vcc Supply Voltage Range Normal Input Specs apply to Enable Input (G) Off State Output Leakage Currents Logic Level Dependent Icc Max Supply Current Note: Occurs when outputs in Hi Z
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Multiplexing Drivers for Bus Operation
Active Driver must provide Iih/Iil currents to ALL receivers plus all the OFF state leakage currents of the other inactive Drivers Must NOT have 2 or more Drivers Active simultaneously. Time Division multiplexing (timing) analysis critical to long term reliabililty of devices
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Standard vs Schmitt Trigger Input Functions
Single Input Threshold Vth, Eliminates Undefined Transition Zone Input should also have minimum “hysteresis” to provide noise immunity As Vin increases thru Vth, Vth decreases by DV (Vhyst) As Vin decreases thru Vth, Vth increases by DV (Vhyst) Vth is typically 1.0 – 2.0 V, Vhyst should be > 200mV Schmitt Trigger should always follow OC/OD outputs or other slow rise or fall time signals (Ex. Optocoupler Outputs, RC Reset Circuits, etc )
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Basic Combinatorial Timing Parameters
TpHL(TpLH): Propagation Delay from High to Low (Low to High) Logic Level Usually measured between the 10% and 90% total voltage transition points. Tpd or Tp: Propagation Delay usually stated as worst case of TpHL and TpLH. Tott or Tout: Output Transition Time. For many families (HC, HCT, etc), gate delays are stated with separate specifications for logical output value generation (Tpd) plus physical output voltage transition (Tott). Need to sum these for total prop delay !! TpzH(TpzL): Propagation Delay from High Impedance to High (Low) Logic Level TpHz(TpLz): Propagation Delay from High (Low) Logic Level to High Impedance
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Review of Medium Scale Integration (MSI) Logic Circuits
Common digital system tasks are commercially available as MSI logic devices in many different TTL and CMOS families Functions such as decoding/encoding, multiplexing, demultiplexing, comparison, arithmetic, code converting, and data busing
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General decoder diagram
Decoders A decoder accepts a set of inputs that represents a binary number and activates only the output that corresponds to that input number. General decoder diagram
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3-line-to-8-line (1-of-8) decoder, Active High
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Typically decoders have ENABLE inputs used to control operation
All ENABLE inputs must be satisfied for an output to be active
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Enables can be used to cascade into larger decoders Example: Four 74ALS138s forming a 1-of-32 decoder
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The 7442 style BCD-to-decimal decoder
One output is active based on the Binary Coded Decimal input value
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Counter/decoder combination can be used to provide timing and sequencing operations
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Encoders A encoder is a decoder in reverse, that is, it accepts a single active input from an input set, and delivers an N-Bit code corresponding to which input was active. General encoder diagram.
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Logic circuit for an octal-to-binary (8-to-3) active low encoder.
For proper operation, only one input should be active at one time.
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A priority encoder has special logic to ensure that when two or more inputs are activated, the output code will correspond to the highest-numbered input. 74147 style decimal-to-BCD priority encoder.
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Priority encoder application as a switch encoder.
NOTE: Switches must be debounced (not shown)!
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Priority Encoder Application: Keyboard entry of 3-digit number into storage registers with proper debounce and clear function
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Functional diagram of a digital multiplexer (MUX)
Multiplexers A multiplexer (MUX) is a circuit that selects 1 input from a set based on the selection code input. Functional diagram of a digital multiplexer (MUX)
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Simple Two-input multiplexer gate level design
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Four-input multiplexer
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74151 Style 8-input multiplexer with complementary output
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Two 74HC151s combined to form a 16-input multiplexer.
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74157 Style Quad Two-Input MUX
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Data Routing MUX Application
System for displaying two multidigit BCD counters one at a time.
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Parallel-to-Serial MUX Application
Parallel-to-serial converter; waveforms for X7X6X5X4X3X2X1X0 = JK’s used as Toggle Flip-flop Ripple Counter
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MUX/Decoder Application
Operation Sequencing MUX/Decoder Application Seven-step control sequence Starts by filling tank1, when full it toggles to fill tank 2, etc.
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Logic Function Generation MUX Application
MUX used to implement a canonical SOP logic function
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Review of Medium Scale Integration (MSI) Logic Circuits
Common digital system tasks are commercially available as MSI logic devices in many different TTL and CMOS families Functions such as decoding/encoding, multiplexing, demultiplexing, comparison, arithmetic, code converting, and data busing
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De-Multiplexers A Demultiplexer (DEMUX) takes a single input & distributes it over several outputs.
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1-line-to-8-line demux
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74138 style decoder can function as a demultiplexer with E1 used as the data input. Typical waveforms shown for a select code of A2 A 1 A 0 = 000 show that O0 is identical to the data input I on E1.
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Security monitoring system MUX/DEMUX Application
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Synchronous data transmission system
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One 16 bit transmission cycle
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74HC85 4-bit magnitude comparator
Comparators A Comparator takes two inputs numbers and yields a result to indicate <, =, > 74HC85 4-bit magnitude comparator
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74HC85 wired as a single 4-bit comparator
Two 74HC85s cascaded to perform an 8-bit comparison
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Magnitude comparator used in a simple controller application
Set Point Magnitude comparator used in a simple controller application
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Basic idea of a two-digit BCD(hex)-to-binary converter.
Code Converters A code converter changes data presented in one type of binary code to another type of binary code Basic idea of a two-digit BCD(hex)-to-binary converter.
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BCD-to-binary Conversion
Compute the binary sum of the binary equivalents of all bits in the BCD representation that are 1s. Example (BCD) = (2) (10) (40) = (52)
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BCD-to-binary converter with 74HC83 4-bit parallel adders.
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Data Bus Interface These circuits include tristate-able buffers and latches Time Division Multiplexing 3 different devices can transmit 8-bit data over an 8-line data bus to a µ-processor; only one device at a time is enabled so that bus contention is avoided.
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Truth table and logic diagram for the 74ALS173 tristate register
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Tristate registers connected to a data bus.
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Signal activity during the transfer of the data 1011 from register A to register C
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Simplified way to show signal activity on data bus lines.
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Simplified representation of bus arrangement.
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Bundle method for simplified representation of data bus connections
Bundle method for simplified representation of data bus connections. The “/8” denotes an 8 bit data bus.
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Basic Combinatorial Timing Parameters
TpHL(TpLH): Propagation Delay from High to Low (Low to High) Logic Level Usually measured between the 10% and 90% total voltage transition points. Tpd or Tp: Propagation Delay usually stated as worst case of TpHL and TpLH. Tott or Tout: Output Transition Time. For many families (HC, HCT, etc), gate delays are stated with separate specifications for logical output value generation (Tpd) plus physical output voltage transition (Tott). Need to sum these for total prop delay !! TpzH(TpzL): Propagation Delay from High Impedance to High (Low) Logic Level TpHz(TpLz): Propagation Delay from High (Low) Logic Level to High Impedance
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Review: Sequential Logic Building Blocks
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Basic Sequential Timing Parameters
Tsu: Setup Time, Data must be stable this min time prior to CLK edge Th: Hold Time, Data must remain stable this min time after CLK edge Td: CLK to Q or Output Delay, Time for Data Propagation to Q Tset/Treset: Control Input to Output Change delay Tw: Min Control Input Width (active low) Tclk: Min Logic 1 (high) + Min Logic 0 (low) time for CLK signal. May be stated separately or as Max Frequency (Fmax). Note: Tclk – (Tsu + Th) = Worst Case usable time to change data.
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Missing Tsu or Th ….. Possible Results
FF latches the data normally as if Tsu and Th were satisfied FF misses the intended data but clocks data at next opportunity FF misses the intended data completely, lost FF latches the correct data but with extended Td FF latches the correct data but exhibits many output transitions FF misses the intended data and exhibits many output transitions FF misses the data and causes other spurious affects Metastable Behaviour
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Characterizing Metastable Likelyhood
Fd can be estimated using a worst case assumption based on clock frequency To and t: Technology (family) specific, usually published in a separate metastability characterization report from the Mfg. Tw: Walkout time allowable within a given application (1/Fc – Tsu – Th) in many cases
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Examples: To & t, Metastability Constants
Worst Case Metastability Analysis Clearly this device is not well suited for the intended application ! Metastability MTBFs Need to Be >> 100 years
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Improvement Using Better (faster) Device
Using Metastable hardened Device Enormous difference in Metastability Performance of Device Technologies
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Same Example Using Multistage Synchronization
Synchronization also used to improve “System” Immunity to Metastability Same Example Using Multistage Synchronization Synchronization Causes System Response Time Penalty
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Simple Data Transfer Example: 10Mhz CPU Memory Read Cycle
Using Timing Parameters, Timing Analysis Simple Data Transfer Example: 10Mhz CPU Memory Read Cycle Timing Diagram notation uses binary signals (CLK, Controls) and bussed signals (Address and Data) CPU Generates System Timing relative to a master CLK. Sends out Address and Control Signals, Expects Data in T3 Basic Memory Read Cycle is 3 CLKs long but can be extended using the DTACK (Wait State) signal CPU Samples DTACK in T2, if non-active, T2 is repeated (Wait State); if active, T2 ends followed by T3 CPU Expects Data at midpoint of T3, Note Data Setup Time and Data Hold Time Requirements Timing Analysis Determines if Target Memory Device is Fast Enough or if it requires Wait States
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Using the “Target” device as viewpoint
Timing Analysis Using the “Target” device as viewpoint Read-Only-Memory is Target Device Target Device Timing Parameters Target has 3 basic input signals Address: Specifies 1 storage location in device to be read CE (active low): Disables entire device including selector system and output driver OE (active low): Disable output driver only
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Timing Analysis… To Get the Data
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Timing Analysis… To Get the Data
Possible Improvements: Use Faster FPGA with lower Tpd Exercise 1 wait state using DTACK
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Timing Analysis… To Finish the Cycle
Can Memory disable output drive in time?
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General State Machine Architecture
Inputs Next State Comb Logic State Variables (FF) Array Output Decoder Logic Possible Outputs Outputs Present State Info CLK Mealy Architecture Requires Output Decoder Logic Block
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Review: State Machine Design
Typical “Bubble Diagram” Important to “Account” for ALL possible states
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2 Classes of State Machines:
Moore Architecture Mealy Architecture Mealy type may utilize fewer FFs, more compact Moore type offers possibility for state variables to be outputs (no glitch) Both types can be implemented with either D or JK type FFs. D used in PLDs
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General State Machine Architecture
Inputs Next State Comb Logic State Variables (FF) Array Output Decoder Logic Possible Outputs Outputs Present State Info CLK Mealy Architecture Requires Output Decoder Logic Block
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Example 1 Design a state machine which is capable of detecting an input signal and adding a 2 clock delay on the trailing (falling) edge of the input. All paths (arrows) which terminate in a logic 1 for Qa, Qb or OUT generate a MIN term in their respective K-Map
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Schematic Implementation
IN Qa OUT Qb CLK Set & Reset inputs unused, terminated with pullup resistors to logic 1
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Example 2 Design a state machine which arbitrates between 2 CPUs sharing a common memory system. Each CPU has a separate request and grant signal. In the event of simultaneous request, give preference to CPU A. Grant 2 Grant 1 Q2Q1 R2R1 R1 Q1 R2 Q2 Preference is given to CPU A with don’t care condition for R2 when R1 is active Moore Implementation Allow state variables to be used directly as outputs
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2 Maps for Q2Q1 D-Input Logic
R2R1 Q2Q1 Q1= R1* Q2 Grant 2 Grant 1 Map for Q1 R2R1 Q2Q1 Q2Q1 Q2= (R2* Q2* Q1) + (R2* R1* Q1) R2R1 R1 Q1 Map for Q2 R2 Q2 CLK
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Machine Partitions
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Equivalence Partition
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State Reduction
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Symmetric Logic Functions
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Properties of Symmetric Logic Functions
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Properties of Symmetric Logic Functions
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