1. Digital Design
Jeff Kautzer
Univ Wis Milw

2. Review: Digital Information
Information is represented numerically using a binary number system
An n bit number has digit weightings 2(n-1) 2(n-2) 2(n-3) ……
Example: b = = 26
4 bit binary “nibbles” are abbreviated using hexidecimal
1001b = 9h, 1010b = Ah, 1011b = Bh, … b = Fh
Logic 1: Represented by a high voltage level and/or forward current
Logic 0: Represented by a low voltage level and/or reverse current
Binary numbers are conveyed individually in time between two or more digital devices.
Devices have electrical limitations in drive, speed, distance, & fanout
Devices may share the same wires/nodes using time based multiplexing

3. Review: Basic 2 Input Logic Operators
Gates and their Demorgan Equivalents
Note: A Bubble implies logic inversion

4. Review: Basic 2 Input X-OR Operators & Gates

5. Review: Truth Tables, Karnaugh Maps
Grey Code

6. Example: Binary-7Segment Display Decoder
2 Types of Display Configurations
Vcc
Common Cathode LEDS
Active High
Common Anode LEDS
Active Low
Gnd

7. 7- segment used to form digits 0-9
7 Segment Display
7- segment used to form digits 0-9

8. Commercial TTL BCD-to-7-segment decoder/driver driving a common-anode 7-segment LED display; 7447 segment patterns for all possible input codes.

9. Truth Table for Active High (Common Cathode Display Drive)
Hex Digits A-F not defined by this decoder.
All Segments OFF

10. Truth Tables and MIN Terms
Each line in the Truth Table is Represented by a “MIN” Term
Each MIN Term is a Full Expression containing each input variable
For Output “a” the following MIN Terms would be Logically “OR”d
D C B A
D C B A
D C B A
D C B A
D C B A
D C B A
D C B A
D C B A
Note: X = NOT X
Output a = D C B A + D C B A + D C B A + D C B A + D C B A + D C B A + D C B A + D C B A

11. Truth Table Reduction
Two MIN Terms can be combined if the same output is obtained but the input variable values differ in only 1 bit position.
The variable for which the value differs with no effect on output is eliminated from the resulting expression.
D C B
D C B
C B A
D C B

12. Combining Adjacent Cells (Min Terms) Reduces Logic Implementation
Output a = D C B A + D C B A + D C B A + D C B A
+ D C B A + D C B A + D C B A + D C B A
8 Min Terms …. 1 Eight Input OR Gate Four Input AND Gates Inverters
Total of 9 Four Input Gates + 4 Inverters
Karnaugh Map Combinations
A C
B D
A C D
Output a = B D + C D + A C + A C D
8 Min Terms …. 5 Four Input Gates Inverters
Total of 8 Gates, Smaller Gates with Fewer Inputs
C D

13. Additional Segment Maps

14. Liquid-Crystal Displays
Liquid-crystal display: (a) basic arrangement; (b) applying a switching voltage between the segment and the backplane turns ON the segment. Zero voltage turns the segment OFF.

15. Commerical Logic devices for driving an LCD segments and full 7-segment displays

16. Common XOR Reduction Patterns
(Alternating Columns, Quads, and Pairs, Checkerboards)

17. Digital IC Technologies/Families
Bipolar: Utilizes BJT’s exclusively as switching elements. Originated by Fairchild/TI, families have included STD, L, H, LS, S, ALS, AS and F
pp74xxx###P Standard Part Numbering Scheme
Package Suffix (Plastic, Ceramic, DIP, SOJ, etc)
Generic Device Function Number (Ex. 244 Octal Driver)
Family Designation (Ex. ALS, AS, F, etc)
7 =Commercial (0-70C), 5 =Military (-55 to 125C or more)
Mfg Prefix (Ex. SN = Texas Inst, DM = Fairchild, etc)
Example
Function/Family
Package Options
For Family Examples see:

18. Active Bipolar Logic Families
ALS
Advanced Low-Power Schottky Logic AS
Advanced Schottky Logic F
Fast Logic LS
Low-Power Schottky Logic S
Schottky Logic
TTL
Transistor-Transistor Logic (STD)

19. Review: Schottky Diode
PN Junction Si Diode Similar to std diode
Low Forward Voltage Drop (~0.3V) C B E
Schottky Transistor
Schottky Diode from Collector to Base of NPN switching transistor
Vbc < Vf of Schottky Diode (~0.3V)
Vce-sat (schottky) > Vce-sat (std BJT)
Base-Collector Clamp prevents hard saturation
Switches Faster as a result

20. Digital IC Technologies/Families
CMOS: Utilizes C-MOSFETs exclusively as switching elements. Originated with 4000 series family (still produced) followed with C, HC, HCT, AC, ACT, FCT, LV, LVC and many others (see list)
Devices follow Bipolar part numbering scheme (except for 4000 series)
Characterized by
Very low input current (leakage current)
Symmetric Output drive currents
Device size/process scales. Industry has moved from 5um channels to less than 75nm channels in < 30 yrs
Example: HC, HCT Families
Function/Family
Package Options

21. ACTIVE CMOS Logic Families
Advanced CMOS Logic (1.5 to 5.5V typ)
ACT
Advanced CMOS Logic
AHC
Advanced High-Speed CMOS (2.0 to 5.5V typ)
AHCT
Advanced High-Speed CMOS
ALVC
Advanced Low-Voltage CMOS Technology (2.3 to 3.6V typ)
AUC
Advanced Ultra-Low-Voltage CMOS Logic (0.8 to 2.7V typ)
AUP
Advanced Ultra-Low-Power CMOS Logic (0.8 to 2.7V typ)
AVC
Advanced Very-Low-Voltage CMOS Logic (0.8 to 2.7V typ)
CB3Q
Low-Voltage, High-Bandwidth Bus Switch Technology
CB3T
Low-Voltage, Translator Bus Switch Technology
CBT
Crossbar Technology
CBT-C
CBT with Undershoot Protection
CBTLV
Low-Voltage Crossbar Technology
CD4000
CMOS Logic (4000 Series, 3 to 18V typ)
FCT
Fast CMOS Technology
GTLP
Gunning Transceiver Logic Plus HC
High-Speed CMOS Logic (2.0 to 6.0V typ)
HCT
High-Speed CMOS Logic
LV-A
Low-Voltage CMOS Technology (2.0 to 5.5V typ)
LV-AT
Low-Voltage CMOS Technology
LVC
Low-Voltage CMOS Technology (1.6 to 3.6V typ)
PCA
Inter Integrated Circuit
PCF
SSTV
Stub Series Terminated Low-Voltage Logic
TVC
Translation Voltage Clamp
VME
VME Bus Products

22. Other Digital IC Semiconductor Technologies
BiCMOS: Combination CMOS/BJT. Can be implemented using Si but SiGe becoming popular for mixed signal applications. Families include: HSTL, BCT, FB, ABT, ALB, LVT and others (see list)
ECL/LVDS: Emitter Coupled Logic / Low Voltage Differential Signaling. Si BJT or CMOS devices that utilize differential signaling with extremely low voltage swings. Typically seen on the output from A/D conversion circuits. Switching speeds > 60Mhz.
GaAs: FET based devices with extremely fast switching and delay characteristics. Ft > 10Ghz easily achievable. Costs > 20X that of fast CMOS

23. Active BiCMOS Logic Families
ABT
Advanced BiCMOS Technology
ABTE
Advanced BiCMOS Technology / Enhanced Transceiver Logic
ALB
Advanced Low-Voltage BiCMOS (3.0 to 3.6V typ)
ALVT
Advanced Low-Voltage CMOS Technology (2.3 to 3.6V typ)
BCT
BiCMOS Technology FB
Backplane Transceiver Logic
GTL
Gunning Transceiver Logic
HSTL
High-Speed Transceiver Logic
JTAG
JTAG Boundary Scan Support
LVT
Low-Voltage BiCMOS Technology (2.7V to 3.6V typ)
SSTL
Stub Series Terminated Logic

24. Other Aspects of Technology: Component Life Cycle Phases
= Mean (Max) Sales of Unit Components per Unit Time
s = One Standard Deviation in Sales/Time

25. Life Cycle of a Component
Special Histogram of Production as Measure by Component Sales/Time (# shipped/time)
Concept Assumes Component Sales follow monotonically increasing to peak, then monotonically decreasing to obsolesence
Life Cycle is Measured Relative to Peak of Sales
+/- 1s from Peak = Mature Product
-1s to –2s from Peak = Growth Product
-2s to –3s from Peak = Introductory Product
+1s to +2s from Peak = Declining Product
+2s to +3s from Peak = Phase Out Product
+3s and higher from Peak = Obsolete Product

26. Logic Signal Electrical Characteristics
Finite Transition Time Zone
Driver must switch voltage thru this zone within specified time or risk causing linear operation of receiver !
Typically < 1uS but varies with logic family technology

27. Logic Device Drive Parameters
Note: Sourced currents are always listed as a negative number by convention on data sheets

28. Interpreting the Data Sheet
Vih, Vil
Ioh, Iol
Ioh (note max Ioh)
Iol (note max Iol)
Iih, Iil

29. Device Output Structure Type 1: Totem Pole
Current Limiting Resistor (reduced in modern devices)
Top Voh/Ioh Source Driver
(Switch to Vcc)
Bottom Vol/Iol Sink Driver
(Switch to Gnd)
Cross-over of Q4:Q5 – ON/OFF may result in high current spike from Vcc to Gnd
Octal and larger devices rated for “Gnd Bounce” Volp. Measure of Static output disturbance when all other outputs switch simultaneously.

30. Device Output Structure Type 2: Open Collector/Drain
Current Limiting Resistor Removed
Top Voh/Ioh Source Driver Removed
Bottom Vol/Iol Sink Driver
Sink Trans Q5 acts as a switch to Gnd
No inherent Logic 1 voltage drive
Interface in 2 ways;
Pullup resistor to Vcc to establish logic 1 voltage level
Switch current through load device (Ex. Relay Coil, LED, Lamp, Solenoid, etc)
Note OC/OD Datasheets:
May list Vce-sat for Vol, Ic max for Iol max, Vce max (off).
Will NOT list Voh, Ioh values !
OC/OD Outputs will have very slow Logic 0 to 1 transition times !

31. OC/OD outputs may be tied together, Wire-OR
Determining Pullup Resistor Limits
Maximum R - Limited by Logic 1 condition: R must supply Iih to receiver plus supply any leakage current to the driver OFF transistors. Finite Current of Io flows thru R dropping voltage. Usually use R < 100KW
Minimum R - Limited by Logic 0 condition: Driver ON may cause Vol as low as 0V, Driver must sync Io from Vcc thru pullup resistor plus Iil source current from receiver. Total load current cannot exceed Driver Iol current capacity. Usually use R> 1KW

32. Device Output Structure Type 3: Tristate-able
Current Limiting Resistor (reduced in modern devices)
Top Voh/Ioh Source Driver
(Switch to Vcc)
Bottom Vol/Iol Sink Driver
(Switch to Gnd)
Q7/Q8 used to stop base current to Q3/Q4 darlington
Turn off Source Driver
Q2 used for same purpose but controls Sink Driver
E turns OFF Q4 and Q5 simultaneously

33. Interpreting the Data Sheet
Vcc Supply Voltage Range
Normal Input Specs apply to Enable Input (G)
Off State Output Leakage Currents
Logic Level Dependent
Icc Max Supply Current
Note: Occurs when outputs in Hi Z

34. Multiplexing Drivers for Bus Operation
Active Driver must provide Iih/Iil currents to ALL receivers plus all the OFF state leakage currents of the other inactive Drivers
Must NOT have 2 or more Drivers Active simultaneously. Time Division multiplexing (timing) analysis critical to long term reliabililty of devices

35. Standard vs Schmitt Trigger Input Functions
Single Input Threshold Vth, Eliminates Undefined Transition Zone
Input should also have minimum “hysteresis” to provide noise immunity
As Vin increases thru Vth, Vth decreases by DV (Vhyst)
As Vin decreases thru Vth, Vth increases by DV (Vhyst)
Vth is typically 1.0 – 2.0 V, Vhyst should be > 200mV
Schmitt Trigger should always follow OC/OD outputs or other slow rise or fall time signals (Ex. Optocoupler Outputs, RC Reset Circuits, etc )

36. Basic Combinatorial Timing Parameters
TpHL(TpLH): Propagation Delay from High to Low (Low to High) Logic Level Usually measured between the 10% and 90% total voltage transition points.
Tpd or Tp: Propagation Delay usually stated as worst case of TpHL and TpLH.
Tott or Tout: Output Transition Time. For many families (HC, HCT, etc), gate delays are stated with separate specifications for logical output value generation (Tpd) plus physical output voltage transition (Tott). Need to sum these for total prop delay !!
TpzH(TpzL): Propagation Delay from High Impedance to High (Low) Logic Level
TpHz(TpLz): Propagation Delay from High (Low) Logic Level to High Impedance

37. Review of Medium Scale Integration (MSI) Logic Circuits
Common digital system tasks are commercially available as MSI logic devices in many different TTL and CMOS families
Functions such as decoding/encoding, multiplexing, demultiplexing, comparison, arithmetic, code converting, and data busing

38. General decoder diagram
Decoders
A decoder accepts a set of inputs that represents a binary number and activates only the output that corresponds to that input number.
General decoder diagram

39. 3-line-to-8-line (1-of-8) decoder, Active High

40. Typically decoders have ENABLE inputs used to control operation
All ENABLE inputs must be satisfied for an output to be active

41. Enables can be used to cascade into larger decoders Example: Four 74ALS138s forming a 1-of-32 decoder

42. The 7442 style BCD-to-decimal decoder
One output is active based on the Binary Coded Decimal input value

43. Counter/decoder combination can be used to provide timing and sequencing operations

44. Encoders
A encoder is a decoder in reverse, that is, it accepts a single active input from an input set, and delivers an N-Bit code corresponding to which input was active.
General encoder diagram.

45. Logic circuit for an octal-to-binary (8-to-3) active low encoder.
For proper operation, only one input should be active at one time.

46. A priority encoder has special logic to ensure that when two or more inputs are activated, the output code will correspond to the highest-numbered input.
74147 style decimal-to-BCD priority encoder.

47. Priority encoder application as a switch encoder.
NOTE: Switches must be debounced (not shown)!

48. Priority Encoder Application: Keyboard entry of 3-digit number into storage registers with proper debounce and clear function

49. Functional diagram of a digital multiplexer (MUX)
Multiplexers
A multiplexer (MUX) is a circuit that selects 1 input from a set based on the selection code input.
Functional diagram of a digital multiplexer (MUX)

50. Simple Two-input multiplexer gate level design

51. Four-input multiplexer

52. 74151 Style 8-input multiplexer with complementary output

53. Two 74HC151s combined to form a 16-input multiplexer.

54. 74157 Style Quad Two-Input MUX

55. Data Routing MUX Application
System for displaying two multidigit BCD counters one at a time.

56. Parallel-to-Serial MUX Application
Parallel-to-serial converter; waveforms for X7X6X5X4X3X2X1X0 =
JK’s used as
Toggle Flip-flop
Ripple Counter

57. MUX/Decoder Application
Operation Sequencing
MUX/Decoder Application
Seven-step control sequence
Starts by filling tank1, when full it toggles to fill tank 2, etc.

58. Logic Function Generation MUX Application
MUX used to implement a canonical SOP logic function

59. Review of Medium Scale Integration (MSI) Logic Circuits
Common digital system tasks are commercially available as MSI logic devices in many different TTL and CMOS families
Functions such as decoding/encoding, multiplexing, demultiplexing, comparison, arithmetic, code converting, and data busing

60. De-Multiplexers
A Demultiplexer (DEMUX) takes a single input & distributes it over several outputs.

61. 1-line-to-8-line demux

62. 74138 style decoder can function as a demultiplexer with E1 used as the data input. Typical waveforms shown for a select code of A2 A 1 A 0 = 000 show that O0 is identical to the data input I on E1.

63. Security monitoring system MUX/DEMUX Application

64. Synchronous data transmission system

65. One 16 bit transmission cycle

66. 74HC85 4-bit magnitude comparator
Comparators
A Comparator takes two inputs numbers and yields a result to indicate <, =, >
74HC85 4-bit magnitude comparator

67. 74HC85 wired as a single 4-bit comparator
Two 74HC85s cascaded to perform an 8-bit comparison

68. Magnitude comparator used in a simple controller application
Set Point
Magnitude comparator used in a simple controller application

69. Basic idea of a two-digit BCD(hex)-to-binary converter.
Code Converters
A code converter changes data presented in one type of binary code to another type of binary code
Basic idea of a two-digit BCD(hex)-to-binary converter.

70. BCD-to-binary Conversion
Compute the binary sum of the binary equivalents of all bits in the BCD representation that are 1s.
Example
(BCD)
= (2) (10) (40)
= (52)

71. BCD-to-binary converter with 74HC83 4-bit parallel adders.

72. Data Bus Interface
These circuits include tristate-able buffers and latches
Time Division Multiplexing
3 different devices can transmit 8-bit data over an 8-line data bus to a µ-processor; only one device at a time is enabled so that bus contention is avoided.

73. Truth table and logic diagram for the 74ALS173 tristate register

74. Tristate registers connected to a data bus.

75. Signal activity during the transfer of the data 1011 from register A to register C

76. Simplified way to show signal activity on data bus lines.

77. Simplified representation of bus arrangement.

78. Bundle method for simplified representation of data bus connections
Bundle method for simplified representation of data bus connections. The “/8” denotes an 8 bit data bus.

79. Basic Combinatorial Timing Parameters
TpHL(TpLH): Propagation Delay from High to Low (Low to High) Logic Level Usually measured between the 10% and 90% total voltage transition points.
Tpd or Tp: Propagation Delay usually stated as worst case of TpHL and TpLH.
Tott or Tout: Output Transition Time. For many families (HC, HCT, etc), gate delays are stated with separate specifications for logical output value generation (Tpd) plus physical output voltage transition (Tott). Need to sum these for total prop delay !!
TpzH(TpzL): Propagation Delay from High Impedance to High (Low) Logic Level
TpHz(TpLz): Propagation Delay from High (Low) Logic Level to High Impedance

80. Review: Sequential Logic Building Blocks

81. Basic Sequential Timing Parameters
Tsu: Setup Time, Data must be stable this min time prior to CLK edge
Th: Hold Time, Data must remain stable this min time after CLK edge
Td: CLK to Q or Output Delay, Time for Data Propagation to Q
Tset/Treset: Control Input to Output Change delay
Tw: Min Control Input Width (active low)
Tclk: Min Logic 1 (high) + Min Logic 0 (low) time for CLK signal. May be stated separately or as Max Frequency (Fmax).
Note: Tclk – (Tsu + Th) = Worst Case usable time to change data.

82. Missing Tsu or Th ….. Possible Results
FF latches the data normally as if Tsu and Th were satisfied
FF misses the intended data but clocks data at next opportunity
FF misses the intended data completely, lost
FF latches the correct data but with extended Td
FF latches the correct data but exhibits many output transitions
FF misses the intended data and exhibits many output transitions
FF misses the data and causes other spurious affects
Metastable Behaviour

83. Characterizing Metastable Likelyhood
Fd can be estimated using a worst case assumption based on clock frequency
To and t: Technology (family) specific, usually published in a separate metastability characterization report from the Mfg.
Tw: Walkout time allowable within a given application (1/Fc – Tsu – Th) in many cases

84. Examples: To & t, Metastability Constants
Worst Case Metastability Analysis
Clearly this device is not well suited for the intended application ! Metastability MTBFs Need to Be >> 100 years

85. Improvement Using Better (faster) Device
Using Metastable hardened Device
Enormous difference in Metastability Performance of Device Technologies

86. Same Example Using Multistage Synchronization
Synchronization also used to improve “System” Immunity to Metastability
Same Example Using Multistage Synchronization
Synchronization Causes System Response Time Penalty

87. Simple Data Transfer Example: 10Mhz CPU Memory Read Cycle
Using Timing Parameters, Timing Analysis
Simple Data Transfer Example: 10Mhz CPU Memory Read Cycle
Timing Diagram notation uses binary signals (CLK, Controls) and bussed signals (Address and Data)
CPU Generates System Timing relative to a master CLK. Sends out Address and Control Signals, Expects Data in T3
Basic Memory Read Cycle is 3 CLKs long but can be extended using the DTACK (Wait State) signal
CPU Samples DTACK in T2, if non-active, T2 is repeated (Wait State); if active, T2 ends followed by T3
CPU Expects Data at midpoint of T3, Note Data Setup Time and Data Hold Time Requirements
Timing Analysis Determines if Target Memory Device is Fast Enough or if it requires Wait States

88. Using the “Target” device as viewpoint
Timing Analysis
Using the “Target” device as viewpoint
Read-Only-Memory is Target Device
Target Device Timing Parameters
Target has 3 basic input signals
Address: Specifies 1 storage location in device to be read
CE (active low): Disables entire device including selector system and output driver
OE (active low): Disable output driver only

89. Timing Analysis… To Get the Data

90. Timing Analysis… To Get the Data
Possible Improvements:
Use Faster FPGA with lower Tpd
Exercise 1 wait state using DTACK

91. Timing Analysis… To Finish the Cycle
Can Memory disable output drive in time?

92. General State Machine Architecture
Inputs
Next
State
Comb
Logic
State
Variables
(FF) Array
Output
Decoder
Logic
Possible
Outputs
Outputs
Present State Info
CLK
Mealy Architecture Requires Output Decoder Logic Block

93. Review: State Machine Design
Typical “Bubble Diagram”
Important to “Account” for ALL possible states

94. 2 Classes of State Machines:
Moore Architecture
Mealy Architecture
Mealy type may utilize fewer FFs, more compact
Moore type offers possibility for state variables to be outputs (no glitch)
Both types can be implemented with either D or JK type FFs. D used in PLDs

95. General State Machine Architecture
Inputs
Next
State
Comb
Logic
State
Variables
(FF) Array
Output
Decoder
Logic
Possible
Outputs
Outputs
Present State Info
CLK
Mealy Architecture Requires Output Decoder Logic Block

96. Example 1
Design a state machine which is capable of detecting an input signal and adding a 2 clock delay on the trailing (falling) edge of the input.
All paths (arrows) which terminate in a logic 1 for Qa, Qb or OUT generate a MIN term in their respective K-Map

97. Schematic ImplementationIN Qa
OUT Qb
CLK
Set & Reset inputs unused, terminated with pullup resistors to logic 1

98. Example 2
Design a state machine which arbitrates between 2 CPUs sharing a common memory system. Each CPU has a separate request and grant signal. In the event of simultaneous request, give preference to CPU A.
Grant 2
Grant 1
Q2Q1
R2R1 R1 Q1 R2 Q2
Preference is given to CPU A with don’t care condition for R2 when R1 is active
Moore Implementation Allow state variables to be used directly as outputs

99. 2 Maps for Q2Q1 D-Input Logic
R2R1
Q2Q1
Q1= R1* Q2
Grant 2
Grant 1
Map for Q1
R2R1
Q2Q1
Q2Q1
Q2= (R2* Q2* Q1) +
(R2* R1* Q1)
R2R1 R1 Q1
Map for Q2 R2 Q2
CLK

100. Machine Partitions

101. Equivalence Partition

102. State Reduction

103. Symmetric Logic Functions

104. Properties of Symmetric Logic Functions

105. Properties of Symmetric Logic Functions