1. Solid State Devices EE 3311 SMU
Chapter 2
Lithography
Revised 9 September 2015

2. Photolithographic Process
Substrate covered with silicon dioxide barrier layer
Positive photoresist applied to wafer surface
Mask in close proximity to surface
Substrate following resist exposure and development
Substrate after etching of oxide layer
Oxide barrier on surface after resist removal
View of substrate with silicon dioxide pattern on the surface

3. Photolithographic Process
Each mask step requires many individual process steps
Number of masks is a common measure of overall process complexity

4. Photomasks CAD Layout
Composite drawing of the masks for a simple integrated circuit using a four-mask process
Drawn with computer layout system
Complex state-of-the-art CMOS processes may use 25 masks or more

5. 3311 MOSFET Metal Level

6. List of Test Structures on 3311 Chip This chip is a metal-gate, thick-oxide, PMOS process with boron diffused junctions
 1-3. Wide thin-oxide devices of various L’s.
 4-6. Narrow thin-oxide devices of various L’s.
 7-9. Narrowest thin-oxide devices of various L’s.
 10. Short field device.
 11. Longer field device.
 12. Longest field device.
 13. Super-tiny thin-oxide device. Probably won’t work.
 14. Bond pad on field oxide.
 15. Larger-area metal on field oxide.
 16. Metal-to-diffusion thin-oxide capacitor.
 17. Diffusion capacitor.
 18. Diffusion serpentine with four (Kelvin) contacts for diffusion sheet resistance.
  Vertical and horizontal contact-to-diffusion alignment measurement device.
 21. Metal-diffusion contact string. Use to check contact integrity.
 22. Thin metal serpentine with four (Kelvin) contacts for metal sheet resistance. This device is probably too narrow to be etched without breaking the connections.
 23. Metal serpentine over diffusion serpentine. Use to check metal continuity and diffusion sheet resistance.
 24. Metal to diffusion alignment measurement device without gate oxide: use to automatically measurement metal to diffusion alignment.
 25. Metal to diffusion alignment measurement device with gate oxide: use to automatically measurement metal to diffusion alignment, or gate oxide to diffusion alignment.

7. List of Test Structures on 3311 Chip, cont’d
  Diffusion-to-diffusion spacing, going from widest on left to narrowest on right. Use to check if diffusions are touching, or to measure punch-through.
 31. Metal-to-diffusion capacitor. Metal to the left; diffusion to the right.
 32. Enhancement-load ratioed inverter: Bond pads, going clockwise and starting at 12 o’clock: VDD; output; VSS; input; VGG.
 33. Sample-and-hold gate. Bond pads, going clockwise and starting at 2 o’clock: Sense transistor source or drain; sense transistor drain or source; sample gate; input.
 34. Alignment cross: thin oxide to diffusion.
 35. Alignment cross: contact to thin oxide.
 36. Alignment cross; metal to contact.
 37. A lateral grounded-base PNP transistor. The emitter is at the top, and the collector is at the bottom. The n-type substrate is the base.
 38. A sixteen-stage shift-register. Bond pads, going clockwise and starting at 12 o’clock: VDD, VSS Phase 2 Clock, Output, VGG, VDD, VSS, Input, Phase 1 Clock.
 39. A ring oscillator with fifteen inverters and a buffer. Bond pads, going clockwise and starting at 1 o’clock: VDD; output from buffer; VSS; VGG.
 40. Ring oscillator with thirty-five inverters plus output buffer connected to, but not in the ring. Bond pads, going clockwise and starting at 1 o’clock: VDD; output from buffer; VSS; gate to provide input for 25 inverter ring; gate to provide input for 15 inverter ring; gate to provide input for 35 inverter ring; VGG. The intermediate taps for inputs likely will not work since the input will be contending with the fixed output of the previous stage.
Circuits 38, 39, and 40 may not work due to design-rule violations in the metal leads which results in many of the circuit connections being not connected.
 Note: many years ago we made some changes to the mask set so that circuits 38, 39 and 40 would have a better chance of working. However, we just noticed that we are still using the old mask set for EE 3311.

8. Photo Masks 10X Reticle
Example of 10X reticle for the metal mask - this particular mask is ten times final size (10 mm minimum feature size - huge!)
Used in step-and-repeat operation
One mask for each lithography level in process

9. Photomasks Final Mask
Mask after reduction and “step-and-repeat” operation
Final size emulsion mask with 400 copies of the metal level for the integrated circuit

10. ITRS Lithography Projections

11. Contamination
Human hair (~100 microns) at the same scale as the integrated circuit with 10 mm feature size
Today’s feature size 100 nm times smaller!

12. Clean Room Specifications

13. Common Wafer Surface Orientations

14. Wafer Cleaning
Wafers must be cleaned of chemical and particulate contamination before photo processing
Example of “RCA” cleaning procedure in table below

15. Photoresist Deposition Automated Production Systems
Rite Track 88e wafer processing system (Courtesy of Rite Track Services, Inc.

16. Mask Alignment
Each mask must be carefully aligned to the previous levels
Some form of alignment marks are used
Automated alignment and exposure in production lines

17. Resists for Lithography
Positive
Negative
Exposure Sources
Light
Electron beams
Xray sensitive

18. Oxide Etching Profiles
Isotropic etching - wet chemistry - mask undercutting
Anisotropic etching - dry etching in plasma or reactive ion etching system
Mask Undercut

19. Etching Approaches

20. Dry Plasma Systems
Conceptual drawing for a parallel plate plasma etching system
Asymmetrical reactive ion etching (RIE) system

21. Plasma Etching Characteristics
Anisotropic etching
Minimizes chemical waste
Etching
Cleaning
Resist removal “ashing”
1 atm = 760 mm Hg = 760 torr = x 105 Pa Pa = 1 N/m2 = torr

22. Mask Fabrication Masking processes Direct step on wafer
Contact printing
Proximity printing
Projection printing

23. Printing Techniques
Contact printing damages the reticle and limits the number of times the reticle can be used
Proximity printing eliminates damage
Projection printing can operate in reduction mode with direct step-on-wafer, eliminating the need for the reduction step presented earlier

24. Photoresist and Pattern Transfer

25. Resist Sensitivity

26. Typical Photoresist Cycle
9/9

27. Wafer Steppers Wafer stepping systems widely used
Must be completely isolated from sources of vibration
High degree of environmental control needed
Often in their own clean room
Figure 2.13 The true complexity of a wafer stepper is apparent in this system drawing. (Courtesy of ASM Lithography, Inc.

28. Wafer Steppers (cont.) i-line g-line Lens System Figure 2.15
Spectral Content of Xe-Hg lamp (Courtesy of SVG)
Lens System

29. Minimum Feature Size and Depth of Field
Microscopy etc…

30. ITRS Lithography Projections

31. End of Lithography Slides for EE 3311

32. Phase Shifting Masks Pattern transfer of two closely spaced lines
Conventional mask technology - lines not resolved
Lines can be resolved with phase-shift technology

33. Inspection SEM, TEM, STM “A picture is worth a thousand words”
Optical microscopy
Scanning electron microscopy (SEM)
Transmission electron microscopy (TEM)
Scanning tunneling microscopy (STM)
SEM images of a three-dimensional micro-electro-mechanical system (MEMS) structure (Courtesy of Sandia National Laboratories).

34. Inspection TEM
Figure 2.18
Cross-sectional high-resolution TEM images for MOS structures with (a) 27-Å and (b) 24-Å Image. Polysilicon grains are easily noticeable in (a); the Si/SiO2 and poly-Si/SiO2 interfaces are shown in part (b). On a local atomic scale, thickness variations of 2-3 Å are found which are a direct result of atomic steps at both interfaces. Copyright 1969 by International Business Machines Corporation; reprinted with permission from Ref. [9].

35. Layout of a Class Chip Basic 4-Mask Process PMOS Metal-Gate Process
1. p-diffusion
2. Thin oxide
3. Contacts
4. Metal

36. Four Mask Class Process
p-diffusion
Thin oxide
Metal
Contacts

37. Layout of Class Chip A B C D E F G I H J Metal Gate PMOS Process
A. Thick oxide capacitor
B. Thin Oxide Capacitor
C. Van der Pauw structure
D. Resistor 1
E. Resistor 2
F. Diode
G. PMOS transistors
H. PMOS logic inverter
I. Lateral pnp transistor
J. Kelvin contact structure

38. Our Class Process Diode & Resistor Fabrication
Top view of an integrated pn diode.

39. Our Class Process Diode Fabrication (cont.)
(a) First mask exposure (b) Post-exposure and development of photoresist
(c) After SiO2 etch (d) After implantation/diffusion of acceptor dopant.

40. Our Class Process Diode Fabrication (cont.)
(e) Exposure of contact opening mask, (f) after resist development and etching of contact openings, (g) exposure of metal mask, and (h) After etching of aluminum and resist removal.

41. Layout of Class Chip A B C D E F G I H J Metal Gate PMOS Process
A. Thick oxide capacitor
B. Thin Oxide Capacitor
C. Van der Pauw structure
D. Resistor 1
E. Resistor 2
F. Diode
G. PMOS transistors
H. PMOS logic inverter
I. Lateral pnp transistor
J. Kelvin contact structure

42. References

43. End of Lithography Section