1. LLRF Research and Development at STF-KEK
LCWS 2016
December 7th, 2016
Sigit B. Wibowo

2. Outline STF Overview STF LLRF System
Feedback Control with Master-slave Configuration
Filling on Resonance
Feedback Control with IF mixture
Summary

3. Superconducting rf Test Facility (STF)
Purpose: Research and development for the realization of International Linear Collider (ILC)
5 MW klystron
(1.3 GHz, 5 Hz, 1.65 ms)
LLRF system
STF
Control Center
RF system in ILC main linac
International Linear Collider (ILC)
・ Planned electron-positron linear accelerator
・ Length : 31 km
・ Energy : s = 500 GeV
One klystron drives 39 SC cavities.
Positron main linac
Each main linac is 11 km long.
Electron main linac

4. Feedback Control with Master-slave Configuration

5. STF-2 : Prototype of ILC-TDR（2015- ）
Configuration of ILC LLRF system
39 SC cavities are operated under cavity-field vector-sum feedback control.
In STF-2, two digital boards connected with optical communication are configured.
→ minimal combination of ILC LLRF system.
Digital board for STF-2 accelerator
STF-2 accelerator
CM-2a (4 SCs)*
CM-1 (8 SCs)*
NC RF gun*, CCM(2 SCs)*
*operated using digital LLRF
control techniques

6. Master and Slave Unit
STF2-LLRF (Master Unit)
ADC
VS1
FB/ FF
O/E VS
DAC
E/O
VS3
CLK
DIV
STF2-LLRF (Slave Unit)
OPTICAL COMMUNICATION
LINK  Introduce Delay
Input
Output
Master board calculates the total vector sum form itself and from slave board.
Optical delay communication must be considered whether it affects the stability
RJ-45 connector,
2ch SFP connectors
MTCA.4 Standard
Zynq-7000(XC7Z045):
ARM (Cortex-A9) → EPICS-IOC
14ch ADCs (AD9650, 16bit)
2ch DACs (AD9783, 16bit)
Spartan6(XC6SLX)
MTCA.4 standard board

7. Conditioning of 8 SC cavities (Oct.-Nov., 2016)
Cavity-field vector-sum in digital board #1
VS3
VS1
Cavity-field vector-sum in digital board #2
VS3
8 SC cavities were operated with average 30.5 MV/m under vector-sum feedback control.
Two digital boards connected by optical communication were demonstrated and the performance fulfilled ILC stability requirements (ΔA/A = 0.07%, Δφ = 0.35°).
0.03%
ΔA/A =0.006%rms
Δφ = 0.03deg.rms

8. One board (master board) operation
8 SC cavities were operated with average 30.5 MV/m under vector-sum feedback control.
Only master board was operated and the performance fulfilled ILC stability requirements (ΔA/A = 0.07%, Δφ = 0.35°).
The optical delay does not affect the stability.
A/A = %.rms
(0.07
 = deg.rms
(0.35

9. Filling on Resonance

10. Klystron Operation in ILC
As in TDR, LLRF tuning overhead is only 7% in power.
Problem in the filling stage  In order to fill the cavities to dedicated gradient, usually large RF power is required in the filling stage.
In order to reduce the required RF power in the filling stage the filling on resonance is adopted.
ILC TDR Volume 3.I: Accelerator R&D
OPERATION:  9.5 MW
LLRF Overhead: 7%

11. Filling on Resonance During the filling time the cavity is detuning.
In detuning condition, more power is required to get the same cavity field as on resonance condition.
If in the filling time the cavity can be on resonance, the required klystron power can be lower.
Detuning in the filling time:
Estimated
filling time:
From the detuning pattern (in frequency), the phase pattern can be obtained by integrating it.
The phase pattern is used to rotate the feedforward table.

12. Feedforward Table Rotation:
To compensate the detuning during filling time, feedforward table is rotated corresponding to detuning during the filling time.
During the filling time, only feedforward control is operated.
Rotated

13. Result
With the same forward power, in the case with filling on resonance , higher cavity field can be achieved compare with the case without filling on resonance.
This confirms that by adopting filling on resonance method, the klystron power can be reduced.

14. Feedback Control with IF-Mixture

15. Simplified LLRF System
Before being fed to the analog to digital converter (ADC), high frequency signal is down-converted into the intermediate frequency (IF).
In this typical system, one IF signal requires one ADC.
down
converter
ILC Case:
One klystron drives 39 cavities
For vector-sum feedback control the information (amplitude and phase ) of all cavities must be measured.
The required ADC number is significanlty high.
One way to reduce the ADC number  IF mixture 15

16. IF-Mixture Concept (cont.)
Motherboard:
uTCA Hardware
FPGA, Virtex 5 FX
Power PC with Linux.
EPICS-IOC
Mitsubishi Electric TOKKI
Typical System with single IF
4 x 16-bit ADC
(LTC2208)
4 x 16-bit DAC
(AD9783)
IF Mixture:
No. of LO = No. of IFs.
No. of ADCs = 1/4 of signal
IF-mixture Technique
IF1
IF2
IF3
By digital processing, this combined signal can be separated into corresponding IFs
IF4 16
Sigit Basuki WIBOWO | Digital LLRF Control System Development for ILC | 2015/7/21

17. IF Mixture Performance
During the period of 8 SC cavities conditioning, the operation of vector-sum feedback control with IF mixture algorithm.
Vector Sum:
8 SC cavities were operated with average MV/m under vector-sum feedback control.
IF-mixture with 4 IFs were demonstrated and the performance fulfilled ILC stability requirements
(ΔA/A = 0.07%, Δφ = 0.35°).
A/A
= %.rms
(0.07 
= deg.rms
(0.35

18. Summary Digital LLRF control system was constructed for STF.
Master-slave configuration with MTCA.4 standard board was developed and the performance was estimated.
MTCA.4 standard board can achieve the stability %.rms and 0.03 deg.rms in amplitude and phase, respectively, which can fulfill the ILC requirement.
Optical link delay in the master-slave configuration does not affect the performance.
Filling on resonance by rotating the feedforward table was demonstrated and this method can effectively reduced required klystron power.
IF-mixture can achieve the stability %.rms and deg.rms in amplitude and phase, respectively, which can fulfill the ILC requirement.

19. Thank you for your attention

20. Backup

21. Optical Link Delay Estimation
The same signal is fed to cavity input 1 and 2.
MSE is calculated from 750us to 100 us.
After fitting the minimum is 88 clock  540 ns.
1 clock = 1/162.5 MHz.
MSE