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Published byClifton Riley Modified over 7 years ago
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Example Addiu $t1 $r0 3 Addiu $t1 $t1 5 Addiu $t1 $t1 7
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Example 2 tal 3 La $t0 tal Lw $t1 0($t0) Lw $t2 4($t0) Lw $t3 8($t0)
Addu $t4 $t1 $t2 Addu $t4 $t4 $t3 Sw $t4 12($t0) 5 7
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The Branch Instruction
B label “label” is an instruction address. Instruction addresses are 32 bits. But branch instructions are immediate format, ONLY 16 BITS !?
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How It’s Done! x B z x, y, z all have y ! absolute values. !
! But the quantity z ! z - y is an offset ! (a relative value). If the offset z - y can be represented in 16 bits, then it will fit.
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But There’s One More Trick....
z and y are valid byte addresses, both word aligned! That means that: z = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00 y = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00 so z - y = xxxxxxxxxxxxxx00 Why waste space representing two bits which are always zero?
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But there’s one more trick....
So, shift the difference (z - y) right two bits. That way, if (z - y) fits in 18 bits we can save the offset in 16 bits!
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How does the structure work?
x B z When we fetch B z, y ! the program counter ! contains the value x. ! z ! That means y = PC + 4. Since offset = (z - y), then PC offset = y + z - y, an absolute address!
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To calculate the branch address
Instruction memory Program counter B Imm z - y shifted right twice Imm 00 Restore the two zeroes 18 bits 14 18 Sign extend to 32 bits PC + 4 4 + Absolute branch address
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Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend B label
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Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend B label
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Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend B label
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Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Beq rs rt label
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Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Beq rs rt label
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Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Beq rs rt label
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Beq rs rt label ? Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze
A ALU 4 B ? + 31 + Sgn/Ze extend Beq rs rt label
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Procedure call Suppose we have a program that “rings the bell” at 10 different locations in the code. This sort of thing is usually complicated! many, many instructions..... That’s a waste of space can’t we write the “bell code” once and share it?
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Procedure call B bell back ! ! B bell Problem: The
back ! return address! Bell ! ! Branch is not ! enough. B back
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Return address A We need to tell the subroutine where it should branch back to, i.e., the return address, each time we call it! That means: The return address must be changeable.
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Return address B We can’t use B x; X is not changeable
we can’t write to the instruction memory... But we can write to: register file data memory So we can write the return address there.
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Return address C Suppose we use $31 for example: Jump register $31:
Bell ! ! Jr $31 Jump register $31: Read the register file and stores the value into the PC
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Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Jr $31
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Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Jr $31
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This works (not the best way):
! bell: ! ! ! La $31 x ! B bell ! x: ! Jr $31 ! La $31 y B bell y: !
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What’s done?? We just want to get the address
La $31 x 2 instructions B bell 1 instruction x: need a label We just want to get the address following the “call” into $31.
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La $31 x B bell x: save return reg $31 address in Return address
Zero ext. save return address in reg $31 Return address when B bell is fetched Branch logic A ALU 4 B + 31 + Sgn/Ze extend La $31 x B bell x:
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The return address The “call” is at “PC”.
So, the return address must be PC + 4. But we compute PC + 4. Can we cause PC + 4 to be written to the register file ($31). Yes. Use BAL bell (branch and link) .
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Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Bal label
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Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Bal label
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Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Bal label
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Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Bal label
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B label … next instr Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze
A ALU 4 B + 31 + Sgn/Ze extend B label … next instr
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