1. Created by Tim Green, Art Kay Presented by Peggy Liska
Building the SAR ADC Simulation Model TIPL TI Precision Labs – ADCs
Hello, and welcome to the TI Precision Lab covering component selection for SAR ADCs. In this video we will learn how to use SAR data sheet specifications to develop a TINA SPICE model.
Created by Tim Green, Art Kay
Presented by Peggy Liska

2. Agenda SAR Operation Overview Select the data converter
Use the Calculator to find amplifier and RC filter
Find the Op Amp
Verify the Op Amp Model
Building the SAR Model
Refine the Rfilt and Cfilt values
Final simulations
Measured Results
SAR Drive Calculator Algorithm
This video covers step 6 of the process for selecting the external components for a SAR ADC, building the SAR model.

3. Equivalent Circuit: Translate to TINA
59pF = 55pF + 4pF
The goal of this video is to develop a custom ADC model based on data sheet specifications. Many ADC data sheets have an equivalent input circuit schematic. This is a good starting point for the model development. If this circuit isn’t provided the sample and hold capacitance is normally given in the data sheet table. The sample and hold resistance, Rsh, can be estimated if needed using the formula given here.
𝑅 𝑠ℎ ≈ 𝑡 𝑎𝑐𝑞_𝑚𝑖𝑛 100∙ 𝐶 𝑠ℎ
𝑅 𝑠ℎ ≈ 290𝑛𝑠 100∙55𝑝𝐹 =53Ω

4. Simplifying the input model
This slide shows how the data sheet equivalent input circuit can be translated into a TINA spice model. The first figure shown here gives the input circuit taken directly from the data sheet. The second circuit adds a circuit to re-set the sample and hold capacitor to zero volts at the end of the conversion cycle. Strictly speaking, this doesn’t explicitly happen in all ADCs. However, the final charge on the sample and hold will be changed by the conversion and the magnitude of this change will differ for different ADC models. Thus, resetting at the end of the conversion cycle creates a conservative model that will provide margin for potential process variation. In the third circuit the diodes are eliminated. This is a reasonable simplification as they are reverse biased under normal operating conditions and will not impact simulation results. In the final circuit we replace the switches with voltage controlled switches. Later we will show how we can control these switches to model ADC conversion.

5. TINA SPICE Equivalent Model
This is the schematic of the ADC model and op amp drive circuit for our example design. Let’s do a brief high level overview. On the left hand side is the OPA320 op amp and RC charge bucket circuit. The calculator helped us select the Op Amp for this example, and provided a range of values for the RC circuit. The ADS8860 resistor and capacitor values are based on the data sheet input circuit. Vacq and Vconv are signal sources that will be used to control the timing of the switches. We will provide details on configuring the switches shortly. The voltage controlled voltage source VCVS1 translates the voltage across the sample and hold capacitors from differential to single ended. This voltage is compared to a steady state voltage source to compute settling error.

6. Configure the voltage controlled switch
Set all parameters as shown.
Default Roff=1GΩ and Ron=0Ω will impact accuracy.
First let’s look at how to configure the switches. Double click on the switch symbol and you can set the switch parameters. The default parameters can have some impact on performance, so you need to change them as shown. Specifically, Roff should be a 1T ohm and Ron should be 1u ohm. The default is Roff = 1G ohm, and Ron = 0 ohm. Von and Voff set the voltage level that will cause the switch to close or open. We will use square wave signals from the source tacq to open and close the switch. In this case the switch will open with a 0V input and will close with a 1V input.

7. Configure the signal source to control the switch
1. Click on source to select and edit switch control signal
3. Select “Piecewise linear”
First, double click on the signal source to configure the control signal. Second, under “signal”, press the button with the three dots. This will open the “signal editor”. Third, select the piecewise linear function type. This waveform type will allow us to generate a square wave that will control switch operation.
2. Under signal, click here to edit.

8. Configure the signal source to control the switch
Voltage levels
On: V ≥ 1V
Off: V ≤ 0V
Time
In the piecewise linear function we can create any waveform shape or timing. In this case we are simply creating a square wave that will turn the switch on when it is at 1V and turn it off when it is at 0V. The pattern will always start with the command “REPEAT FOREVER” end with “ENDREPEAT”. This will repeat the waveform between the two commands forever. Each pattern corresponds to one conversion cycle. This example shows the pattern used to control the switch for the acquisition period. The switch will be closed for the first 290ns period and will remain open for the reminder of the cycle. Note that the rise and fall time of the waveform is limited to 1ns. The left hand side of the waveform corresponds to the time and the right hand side corresponds to the voltage. In this example, at 0 seconds the voltage level is 0V. At 1ns the voltage is changed to 1V. TINA will connect any two points in the list with a straight line, so the first two points transition the input from 0V to 1V in 1ns. The third point keeps the voltage at 1V from 1ns to 291ns. The forth point transitions the voltage from 1V to 0V in 1ns and the final point extends the period to 1us.
SW on
SW off

9. Timing diagram 1/fsample= 1µs tconv-max = 710ns tACQ = 290ns
This slide shows the timing diagram for the data converter acquisition and conversion. For this example we will run the converter at maximum data rate so we will use the minimum acquisition time and the maximum conversation time. This timing will be used to control the switch for the acquisition switch and the reset switch.
Parameter
MIN
TYP
MAX
UNIT
tacq
Acquisition time
290 ns
tconv
Conversion time
500
710
1/fsample= 290ns + 710ns
1/fsample= 1µs
fsample = 1MHz

10. Example simulation: simulator settings
Here we show the timing that was used for both the acquisition and switch control and the end of conversion reset switch. The throughput time is 1000ns for this converter example, so both waveforms are 1000ns long. The top waveform closes the acquisition time switch 290ns at the start of the conversion cycle. The bottom waveform closes the reset switches at the end of the conversion cycle. Notice that all waveforms maintain a 1ns rise and fall time.

11. Optimizing Simulation Results
TR excitation subdivisions = 1000
TR time intrv. subdivisions = 10k
This increases the number of points vs time so that transient behaviors aren’t obscured.
SAR drive transient simulations require fine time increments to avoid obscuring important waveform information . Using the default settings in TINA may result in errors, as the number of points, or time resolution, are optimized for fast simulation time. The “Set Analysis Parameters” feature allows you to optimize the way the SPICE math engine works. Increasing the “TR excitation subdivisions” to 1000 and the “TR time intrv. Subdivisions” to 10k will increase the number of points versus time so that we don’t obscure fast transient behaviors. Make sure you make this change before running SAR simulations. Note that you will need to press the finger button at the bottom to expand the list so that you can edit these parameters.
“Set Analysis Parameters” adjusts how the simulator math engine operates.
Press this button to expand the list.

12. Optimizing Simulation Results
Another change you should make before running spice simulations is to increase the numeric precision to six digits under the “options” menu. This will allow us to see the dc operating point to six digits. This is needed to set up the error measurement circuit as we will see in the next slide.
Set the “numeric precision” to 6 digits. This will allow us to see dc operating points to six digits. The importance of this is highlighted on the next slide.

13. Steady State Simulation Results
Set the output source to match the steady state ADC input.
In this slide we will configure the error measurement meter. The meter needs to be configured to read zero error when the voltage across the sample and hold capacitor is settled to the steady state output of the amplifier. In other words, when the sample and hold capacitor voltage is fully settled, the error should read zero volts. This is achieved by setting the voltage source Voa_SS on the left side of the meter to a dc voltage equal to the steady state amplifier output. It is important that this voltage is accurate to the microvolt level as we will settle to microvolts of error. This is why we increased the simulation numeric precision to six digits in the last slide. The right side of the meter is driven by the total voltage across the sample and hold capacitors. In this case the voltage controlled voltage source VCVS1 is used to translate the differential voltage across the sample and hold capacitors to a single ended voltage. This voltage is then compared to the dc steady state voltage source Voa_SS and when the voltage across the sample and hold capacitors is fully settled the error meter reads zero volts.
The steady state input to the ADC includes amplifier offset an gain errors.

14. Example simulation: simulator results
Input to ADC across Charge bucket filter
Internal ADC sample and hold capacitor
Error in ADC settling sampled signal
Op amp output
Now we are prepared to look at ADC settling using transient analysis. To do this select “Analysis>Transient” in the TINA SPICE menu. Next select a time range that allows you to examine a few conversions. For this example the sampling rate is 1MHz, so we run the transient for 2us for two full cycles. The transient results for this example include the voltage across the charge bucket filter, VCfilt, the voltage on the internal ADC sampling capacitor, VCsh, the error in ADC settling ,Verror, the Op Amp output, Voa, the acquisition control signal, tacq, and the conversion reset signal, tconv.
Acquisition switch control
Conversion switch control

15. Key Result: Error Signal
The most important signal that is monitored in this type of simulation is the error signal, Verror. This signal compares the voltage across the sample and hold capacitor to a steady state voltage source, Voa_SS. The dc voltage on Voa_SS is set equal to the normal dc output of the amplifier when it is fully settled. The goal is to get a zero Verror signal when the voltage across the sample and hold capacitor is equal to the steady state amplifier output. In other words, the error will read zero when the ADC is fully settled.
Note that the acquisition switch is only closed during the acquisition period which is when tacq is high. For proper SAR settling, we will look at the error signal at the end of the acquisition period. Also notice that the internal sample and hold capacitor is reset at the end of the conversion period or when tconv transitions high.

16. Zoom in on Error Signal N=16 Number of bits
LSB= 𝐹𝑆𝑅 2 𝑁 = 5.0𝑉 =76.3μ𝑉
Resolution
0.5∙LSB=38.1μ𝑉
Target Error
A common trick used to better understand ADC settling is to adjust the scale on the error signal relative to the LSB value. In this example the LSB value is 76.3uV, so the error axis is adjusted to ±100uV. The goal here is to settle to half an LSB so this range allows us to confirm settling graphically. The axis scaling can be adjusted by double clicking on the axis and entering the appropriate lower and upper limit. Another TINA trick is to use the “View>Show/Hide curves” option to limit the number of curves.
Click on axis and adjust the scale relative to LSB resolution.
Use “view>show / hide curves” to focus on most important curves.

17. Agenda – next video… SAR Operation Overview Select the data converter
Use the Calculator to find amplifier and RC filter
Find the Op Amp
Verify the Op Amp Model
Building the SAR Model
Refine the Rfilt and Cfilt values
Final simulations
Measured Results
SAR Drive Calculator Algorithm
The next video will walk through step 7 of the process.

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