PRESENT AND FUTURE OF FEOL RELIABILITY

PRESENT AND FUTURE OF FEOL RELIABILITY
— FROM DIELECTRIC TRAP PROPERTIES TO RELIABLE CIRCUIT OPERATION BEN KACZER DEVICE RELIABILITY AND ELECTRICAL CHARACTERIZATION GROUP �15�� © 2016 imec, B. Kaczer / Nov 2, 2016 Taiwan ESD and Reliability Conference

IS RELIABILITY IMPORTANT? AND MOTIVATION
Typical marketing specs / buyer checklist: Network Display Memory Camera Battery Processor ... Reliability ?? Reliability is an essential aspect of all products and the underlying technologies BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

WHY RELIABILITY TESTING
As fabricated E.g., a month later ID ID VD Record performance! VD Performance degraded Insufficient reliability: field returns, loss of profit, credibility, market share... Excessive reliability: costly product, loss of profit, performance, market share... Devices cannot be tested for years (corresponding to field use)  accelerated testing needed! BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

ACCELERATED TESTING TYPICALLY DONE WITH V AND/OR T
10 years Log time-to-failure Operating conditions Accelerated conditions Correct projection to operating conditions only possible if same mechanism at accelerated and operating conditions acceleration laws understood! BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

STOCHASTIC NATURE OF RELIABILITY MECHANISMS: A FRACTION OF DEVICES WILL FAIL
10 years Log time-to-failure (courtesy of T. Grasser) As dimensions get smaller, distributions become wider Operating conditions Accelerated conditions Reliability is described in term of statistical distributions and probabilities BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

CORRECT STATISTICS IS NEEDED TO PREDICT THE FAILURE FRACTION
Typical number of test samples ? Failure at operating conditions Parameter X at operating conditions The fraction of failed devices can be correctly extrapolated only if underlying mechanism understood! Order of magnitude important if dealing with high volume, high device counts log probability BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

FAILURE IS CIRCUIT AND WORKLOAD SPECIFIC
F1(A,B) F2(A,B) A(t) F(X) Known workload X(A,B) F3(A,B) B(t) F4(A,B) Degradation probabilities of each device and the entire circuit F can be calculated BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

TRENDS IN VLSI Reliability has to be still ensured New materials
High-k dielectrics Metal gates High-mobility substrates New device architectures SOI FinFET Gate-All-Around Nanowires Tunnel FET Smaller devices Increasing variability Lower supply voltages Not always (“turbo” modes for QoS) Electric fields still increasing New integration schemes Reliability has to be still ensured BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

TRADE-OFFS AND DECISIONS...
e.g., Mission critical e.g., Redundancy P P A R C BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

OUTLINE Why reliability Gate-oxide defects SILC & TDDB RTN & BTI HCD
Self Heating Device reliability trends Variability and distributions Circuit simulation with aging BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

SPATIAL AND ENERGY POSITIONS TUNNELING COMPONENT
SiO2 Source: A. Shluger (UCL) BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

STRUCTURAL RELAXATION FROM FIRST PRINCIPLES CALCULATIONS
vibrations around ground states Source: Schanovsky & Grasser (TUW) Grasser, MR 52, 39 (2012) neutral state charged state BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

TRAPPING (CAPTURE) AND DETRAPPING (EMISSION): MULTI-STAGE PROCESS
Structural relaxation + phonon emission Capture Available carriers Tunneling into defect Energy release via phonon emission Emission Energy absorption via phonon capture Tunneling out of defect (into an availabl e state) Grasser, Microel. Reliab. (2012) BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

WHAT CAN A DEFECT DO? “NOT MUCH...” τc (V, T) τc (V, T) τ (V, T)
Charge & discharge back into same electrode Charge & discharge into the other electrode = leakage Subs Oxide τc (V, T) Metal Subs Oxide Metal τc (V, T) τ (V, T) e2 τe1 (V, T) A charged trap will be influencing device electrostatics (ΔVth, ...) and channel transport (Δμ, ...) BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

INTERFACE STATES Depassivated Si Dangling bond
SiO2 Positive Pb center Source: T. Grasser, IRPS 2013 Tutorial Neutral Pb center Negative Pb center States due to unsatisfied bonds at semiconductor/dielectric (Si/SiO2) interface Density depends on surface orientation Si/SiO2: H chemistry very important; H can both passivate and depassivate the bond, Si Source: Entner, Ph.D. Thesis e.g. Houssa et al., APL 2007 BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

DESCRIPTION OF DEFECTS
Rzepa et al., VLSI 2016 Defects characterized by distributions of: Energy Within band gap Structural Position in oxide (x, y, z) Capture and emission times Impact on device (ΔIDrain, ΔIGate, ΔVth, etc.) BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

http://ieeexplore. ieee. org/search/searchresult. jsp
search&sortType=&rowsPerPage=&searchField=Search_All &matchBoolean=true&queryText=(Rzepa)&refinements= &refinements= &ranges=2016_2017 _Year

OXIDE TRAPS MORE COMPLEX
Vastly different behavior of traps explained by 4-state model Metastable states explain: switching oxide traps via state 1‘ multistate frequency dependence anomalous RTN partly bias independent time constants For full description we need distributions of τc(V,T) and τe(V,T) Grasser et al., TED 58, 3652 (2011) BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

SUMMARY Gate oxide defects can
Exist in oxide bulk (Not, Dot) and at interfaces (Nit, Dit) Charge / Discharge as a f(V, T) Impact FET observables when charged Be generated and neutralized Migrate & Drift (not covered here  RRAM) Have more complex (2+ state) internal structure Have their properties distributed BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

OUTLINE Why reliability Gate-oxide defects SILC & TDDB RTN RTN & BTI
HCD Self Heating Device reliability trends Variability and distributions Circuit simulation with aging BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

TIME-DEPENDENT DIELECTRIC BREAKDOWN (TDDB)
D. R. Wolters, Ph.D. Thesis, 1985 40 nm SiO2 Gate V Si substrate I Gate oxide breakdown: abrupt increase of gate leakage t BD t BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

PHASES OF GATE DIELECTRIC BREAKDOWN
10-4 10-6 5 4 Oxide Crupi et al., TED 1998 Hard Breakdown (HBD) wear-out 3 10-8 Soft Breakdown (SBD) 2 10-10 Stress Induced Leakage Current (SILC) 10 -12 Fresh 1 10-14 1 2 3 Gate Voltage (V) 4 5 1 2 3 4 5 G G G G G S D S D S D S D S D W W W W W Electrical stress = Additional gate oxide leakage paths (TDDB) + FET intrinsic parameters change (“BTI”) BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

PHASES 1-3 IN DETAIL: MORE DEFECTS = MORE CURRENT
1 DEFECT  SILC Weibull =1xm Note trap “strategically placed” Tunneling current 2 DEFECTS  anomalous SILC Weibull =2xm  FLASH bit fails Tunneling current After R. Degraeve N DEFECTS  soft BD Weibull =Nxm  Analog circuit fails; many soft BDs: P ower consumption increases Percolation path more DEFECTS  HBD Local barrier lowering NOT Weibull 2 phases! Degradation+wearout Resistive path  Digital circuit fails Defect generation ~ fluencem (statistics discussed later) BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

OBSERVATION OF SILC IS AREA DEPENDENT
Large device: SILC or 2-trap SILC Or Soft BD till HBD Smooth increase Average effect current time Courtesy R. Degraeve Small device: SILC or 2-trap SILC Or Soft BD Step-wise increase Different magnitude Individual leakage spots current time Same concept (later): RTN and time-dependent variability BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

PHASES 4-5: SBD DEGRADATION AND WEAR OUT IN THIN OXIDES
Metal gate III. Runaway RS-limited HBD (not-Weibull unless wearout short) I. SBD: Weibull (βSBD,ηSBD) II. Wearout Kaczer et al., IEDM 2004 BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

TDDB SUMMARY SILC and TDDB are due to generation of (conductive) defects in gate oxide A handful of (“strategically placed”) defects can affect gate oxide leakage Breakdown due to defect “percolation path” between gate and substrate Soft breakdowns (low, high-nonlinear current) can occur during operation, will not typically affect FET or circuit performance Hard breakdowns (high current, near-ohmic behavior) should be avoided BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

BIAS TEMPERATURE INSTABILITY
25 Kerber et al., TED 55, 3175 (2008); Aoulaiche et al., IRPS 2009 Kaczer et al., SISC 2004, IRPS 2005 Mitani et al., ECS 2005 Zafar et al., VLSI 2006 Garros et al., ICICDT 2010 VDD 20 stress relaxation Vth (mV) 15 0V VDD 10 T = 125 oC VG,stress = -2 V 5 VG,relax = 0 V 500 1000 time (s) 1500 2000 Negative BTI (NBTI) Typically in pFETs Hole trapping, near substrate interface Interface states Positive BTI (PBTI) Typically in nFETs Electron trapping, high-k Interface states  ΔVth, ΔSS, Δμ, Δgm  ΔVth, ΔSS, Δμ, Δgm BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

THE CURSE AND THE BLESSING OF BTI: RELAXATION
= 0) Rangan et al., IRPS 2003 1.4 nm SiON pFET tstress = 100 s T = 125 oC 50 40 30 20 10 R(tstress, trelax (mV) Vth R(tstress, trelax) “Permanent” 10-3 10-1 105 relaxation time trelax (s) Major issue for measurements, interpretation, and lifetime projection Contains information about the mechanism; increases device lifetime BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

UNDERSTANDING BTI (Near) Interface defect generation (mostly NBTI)
“Reaction Diffusion” Jepsson & Svensson, JAP 48, 2004 (1977); Alam, IEDM 2003 “Gate-side H release” E. Cartier et al., ME 28, 3 (1995), Grasser et al., IEDM 2015 Bulk trap charging/discharging “Trap level misalignment” Kaczer et al., ME 86 (2009); Franco et al., TED 2013 Part II; VLSI PBTI NBTI Rare earths Dipole engineering Reference Reference With SiGe Si Si SiO2 InGaAs HfO2 MG SiO2 InGaAs HfO2 MG Si SiO2 HfO2 MG Si SiGe SiO2 HfO2 MG BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

DEEPLY-SCALED DEVICE OPERATION IS AFFECTED BY INDIVIDUAL DEFECTS
In deeply-downscaled technologies, only a handful of random defects will be present in each device Courtesy of M. Bina, TUWien Not = 1012 cm-2  NT ~ 10 if device area = 10 x 100 nm2 Number of charged defects will be increasing with operating time  time-dependent variability in addition to time-0 variability BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

ORIGIN OF ID AND IG RTN ID-RTN: intermittent trapped charge influencing channel conduction G S D IG-RTN: additional gate current due to intermittent trapped charge G Toledano et al., IRPS 2012 (Source) Kaczer et al., INFOS 2013 Goes et al., IPFA, SISPAD 2013 Andersson et al., PRB 1990 Chia-Yu et al., IRPS 2011 E. Bury et al., IPFA 2014 S D Note vastly different magnitudes of ∆ID and ∆IG correlation of ∆ID and ∆IG (other combinations possible) BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

BTI AND RTN IN SMALL DEVICES
|VG| time degradation (~total ΔVth) Large devices BTI stress BTI relaxation ~ time ~ log stress time ~ log relaxation time ~ time degradation (~total ΔVth) RTN Small devices RTN BTI stress BTI relaxation ~ log stress time ~ log relaxation time (size of bubble represents impact) τc(V,T) τc(V,T) τc(V,T) Wirth et al., IEDM 2009; Kaczer et al., IRPS 2011; Grasser et al., IRPS 2014 τe(V, T) τe(V, T) τe(V, T) BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

RTN AND BTI SUMMARY Two flavors of BTI: Negative BTI (PFET) and Positive BTI (NFET) BTI due to trapping of cold carriers in existing (bulk) and generated (interface) states Hydrogen chemistry crucial in defect generation BTI recovery due to defect discharging, complicates measurements, interpretation, reliability projections Same defects responsible for BTI recovery and RTN Only a handful of defects present in deeply scaled devices Depending on the position of an individual defect, its charging/discharging may result in RTN signal (in drain and/or gate current) “Bias Temperature Instability for Devices and Circuits”, Springer 2013, ISBN BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

CHANNEL HOT CARRIER DEGRADATION (HCD)
OSS (Off-State Stress) HCD Kaczer et al., WoDiM/JVSTB 2016 signed log10 (ΔVth) VD (V) Bravaix et al., IRPS 2009 Also e.g. Koyanagi et al., TED 1985 VG (V) BTI Carriers in the channel of a MOSFET gain high energy under influence of large electrical fields Opposite-polarity carriers are generated by Impact Ionization BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

IMPACT OF HOT CARRIERS Interface state generation
STM experiments: Persson and Avouris, Surf. Sci Lyding et al., Appl. Surf. Sci. 1998 Interface state generation Multiple-carrier process (scaled devices) Single-carrier process  Mixed mode (long devices) McMahon et al., ICMSM 2002 Laurent et al., VLSI 2016 Preferential charging of bulk states by primary and/or secondary carriers Local heat generation and T increase (“self-heating”)  All depend on local carrier energy distribution Schematics source: S. Tyaginov BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

CARRIER TRANSPORT AND ENERGY DISTRIBUTION FUNCTION
Source: S. Tyaginov Carrier energy distributions Distribution function (DF) along the channel affected by: Local electric field Scattering Carrier-Phonon (higher T  shorter MFP) Carrier-Carrier Surface roughness Interface and bulk states (feedback loop!) Impact Ionization... defect generation Total degradation: product of DF and defect generation rate BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

HCD SUMMARY Hot carrier degradation is due to generation and charging of gate oxide defects by hot carriers (at the drain) Single or multiple carriers are needed to generate interface states (depending on carrier energy) Severity increases as gate length is reduced Concomitant charging of defects by “cold” carriers (at the source) still takes place Heat generation accompanies the mechanism “Hot Carrier Degradation in Semiconductor Devices”, Springer 2014, ISBN BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

HEATING CAN BE MODELED AT MULTIPLE LEVELS
“Atomic” level ~1nm Optical phonon temperature (K) Transistor level ~10-100nm Metallization layers 1~100µm Die level ~ 1 mm Die-Package level ~ 10 mm die 1 450 400 350 300 die 2 Vasileska, ICWE2014 Bury, IRPS2014 “transistor ΔT” Jiang, IRPS2012 Prasad, IRPS2013 chip ΔT Source: H. Oprins package ΔT “junction ΔT” “interconnect ΔT” Local self-heating effects Global self-heating Thermal properties can be defined at every hierarchical level of the chip Thermal properties are propagated between levels as boundary conditions or material properties Courtesy: E. Bury BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

Gate Voltage [arb. units]
SELF-HEATING (SH) IMPACTS DEVICE PERFORMANCE AND RELIABILITY SH is due to joule heat generated by passing on-current Heat that cannot escape results in increased temperature T Increased T typically results in performance drop and acceleration of degradation Issue in small, closely packed, novel devices and materials Reduced drive current Increased HC degradation Temperature increase Courtesy: E. Bury FinFET drive current [arb. units] C. Prasad et al., IRPS 2013 T = 25C T = 40C T = 120C Gate Voltage [arb. units] Note: μ, Vth reductions BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

(SELF) HEATING ANALYSIS IS GETTING MORE COMPLEX
complexity Intrinsic q_ = kVT Fourier heat diffusion law Extrinsic ∆T = RTH.Q   Ohms law ∆V = R. I At nm dimensions, appreciable phonon scattering at interfaces, impurities Thermal conductivities strongly reduced Heat flow becomes anisotropic Reduced film thickness & J. Heat Transfer 2006 Liu et al., TED 2006 Bury et al., VLSI 2015 E.g., single fin: κxx κyy κzz Thermal conductivity [W/mK] 103  Thermal conductance tensor Bulk Si Fin Si 102 Bulk Ge Fin Ge 101 <110> 100 Bulk SiGe70 Fin SiGe70 y x x 10-1 z Temperature [K] BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

SUMMARY SH is due to joule heat generated by passing on-current Heat that cannot escape results in increased temperature T Bulk material thermal conductance values do not correspond to heat transfer mechanisms at modern FET dimensions (by orders of magnitude) Severity increases as more power per volume, lower thermal conductance materials are used Special structures need to be designed for SH evaluation SH complicates extrapolation of other degradation mechanisms to operating conditions (see Introduction) BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

LOGIC TECHNOLOGY ROADMAP
Charge transport devices only Steep SS FET Natural channel length Source: A. Steegen, G. Eneman, various I. Ferrain et al., Nature 2011 BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

TDDB IN HIGH-K AND NON-PLANAR ARCHITECTURES
Current injection more complex Gate injection  Substrate injection (high VG) Substrate injection (low VG)  HK IL Increased degradation in high-field regions Mei et al., IEDM 2016 Each layer has a different defect generation rate Probabilities of creating “percolation clusters” of traps in both layers HK IL Nigam et al., IRPS 2009 BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

BTI IN NARROW FINS AND NANOWIRES
1 V =1V, t =2000s, Franco et al., IRPS 2016 Substrate lowly doped and fully depleted ovstress stress T=125C Si ref. Vth [V] 0.1 SiGe 25% Example: SiGe fins SiGe 45% 0.01 Constant Vov Wfin [nm] 1.E+12 Quantization Alian et al., IEDM 2013 Franco et al., IRPS 2014 3nm 5nm 10nm 15nm ΔNeff [cm-2] 1.E+11 tch Example: InGaAs QW Cf. SiGe QW 1.E+10 Non-planar electrostatics 5.E+05 equivalent Eox ~Vov/Tinv [V/cm] 5.E+06 Chasin et al., submitted to IRPS 2017 4 2.2 Example: Si GAA NW FET  = 3.5 3.5 2 4nm diameter: Eox 23% higher than planar Eox 12% higher than 10nm NW Vth,NW/vth,planar 3 1.8 ENW/Eplanar 2.5 1.6 10nm diameter: Eox 10% higher than planar 2 1.4 1.5 1.2 1 1 5 10 NW diameter [nm] 15 20 BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

HCD IN FINFETS AND NANOWIRES
Source: M. Cho HCD degradation reported both increasing and decreasing as a function of fin width 1-3 Independent of width when plotted at same Vov = VG – Vth 4 Independent of NW width 5 [4] Lower density of Si bond sites at the Si/oxide interface in the rotated FinFET reduces HCD 4,6 [4] 1Ramey et al., IRPS 2013; 2Choi et al., IEDM 2003; 3Kim and Lee, EDL 2005; 4M.Cho et al., Hot Carrier Degradation in Semiconductor Devices, Chapter 10, Springer, 2015; 5Laurent et al., VLSI 2016; 6Tallarico et al., TDMR 2014 BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

SELF HEATING IN FIN AND GAA NW FETS
Pla nar FET F inFET G AA-NW FET Bury et al, VLSI 2015, IEDM 2016 T T T 300K 300K 300K FinFET w/ (Si)Ge GAA NW FET w/ InGaAs High-mobility alloys may strongly increase SH Good thermal contact can compensate even GAA NW SH BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

SUPERIOR SIGE PFET NBTI RELIABILITY
TiN (Si)Ge Si (a) HfO2 SiO2 IL 108 10Y Si cap=1.3nm QW=7nm Si cap Si cap=1.3nm Si0.45Ge0.55 QW=5nm Si0.45Ge0.55 Time to 30mV shift (s)  106 104 (a) (b) (c) Reduction of degradation with Ge content increase Wider quantum well Si cap thickness decrease Is explained by trap level “misalignment” 102 Si cap 0.65nm 1nm 1. 3nm 2n m Ge 0% 45% 55% QW 3nm 5nm 7nm 100 10-2 |VGstress-Vth0| (V) 2 |VGstress-Vth0| (V) |VGstress-Vth0| (V) 0.1 (a) NBTI power law prefactor = Vth(tstress=1s) [V] V  E  t  n (c) th ox stress 1 EF EVS   3 Max. |VG-Vth| [V] 0.8 J. Franco et al. TED 60(1), p , (2013) 0.01 Si0.45Ge0.55  ~ 4.4 0.6 Si SiGe Si SiO2 HfO2 MG Si 0.4 HKF NBTI optimized MIPS NBTI optimized (b) 0.001  ~ 5.8 EVS 0.2 E F Si ref. Sicap 1.3nm Sicap 0.65nm Sicap 2nm Sicap 1nm IBM SiGe NUS GeSn 0.0001 4 Tinv (≈EOT+4Å) [Å] Equivalent Eox~Vov /CET [MV/cm] Si SiGe Si SiO2 HfO2 MG BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

Ge NMOS: DEFECT BAND ENGINEERING
+ La * Unfavorable Ec at Ge/Si cap interface Minimized Si cap thic kness: improved mobi lity but impact on relia bility Engineered energy decoupling: Steeper Eox dependence* results in improved BTI reliability Best result: thin Si cap to form SiO2 IL + Interface dipole by inserting La H. Arimura et al., IEDM 2015, 2016 improved PBTI reliability BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

InGaAs NMOS: DEFECT BAND ENGINEERING (2)
0.4 InGaAs/Al2O3 InGaAs/HfO2 3 Al2O3 HfO2 2 [eV] 1 s) (InGaA 0 operation C E – -1 -2 (e) -3 1.E+18 1.E+19 1.E+20 Dot [cm-3 eV-1] 3 Al2O3 HfO2 HfO2+dipole Hysteresis [V] Vfb0 - VGstart Vfb0 - VGstart (model) Shallow defect band (PBTI) 2 E – EC (InGaAs) [eV] 1 Symbols: Measurements Lines: Calibrated defect (a) VGstop - Vfb0 [V] band model (c) operation 0.04 0.8 1.6 3.2 Deep defect band (NBTI) 0.3 -1 Hysteresis [V] VGstop-Vfb0=1.25V VGstop-Vfb0=1V -2 (b) (d) 0.03 -3 1.E+18 1.E+19 0.2 2 0.2 Vfb0 – VGstart [V] 2 4 1.E+20 Dot [cm-3 eV-1] Large hysteresis at both positive and negative VG’s due to wide “deep” and “shallow” defect distributions  poor BTI reliability HfO2 defect density minimum close to InGaAs Ec, can be further tuned by dipole insertion (cf. ) J. Franco et al., VLSI 2016; V. Putcha et al., submitted to IRPS 2017 BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

JUNCTIONLESS FET Inversion mode FET Junctionless (JL) FET
J. P. Colinge et al., Nature Nanotechnol. 5, (2010) In JL FET, the gate oxide field is distributed between on and off states Considerable reduction of degradation (BTI and HCD) Toledano et al., EDL 2014 Cho et al., IEDM 2015 BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

2D FET Graphene FET: gate oxide charging a major issue
Illarionov et al., TED 62, p (2015) MoS2 FET: charging reduced by Hexagonal Boron Nitride cladding Illarionov et al., IRPS 2016 BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

TUNNEL FET Ids Ltun Ltun
Band-To-Band Tunneling (BTBT): F-D distribution tail “clipped”  SS < 60 mV/dec ON-state gate InGaAs TFET Vds = 0.5 V WF = 4eV Smets et al., JAP 115, (2014) Source: A. Verhulst [1] source p i n drain [A/μm] SS = 60 mV/dec I60 [3] gate Ids Ec OFF sub-60 mV/dec point-swing E [eV] Ev Ltun Vgs [V] source channel drain Trap-Assisted-Tunneling in BTBT region1 BTI and HCD ΔId: oxide trap modifies E field, BTBT2 ΔVth: gate oxide charging3,6 ΔSS: reduced3-6 ΔDit: only narrow band in injection region matters6 1Sant et al., TED 2016; 2Jiao et al., IEDM 2009; 3Mizubayashi et al., IEDM 2014; 4Walke et al., TED 2013; 5Ding et al., TDMR 2015; 6Franco et al., EDL 2016 L [nm] Ec ON E [eV] Ev Ltun source channel drain L [nm] BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

top tier device processing
3D INTEGRATION Source: A. Vandooren, J. Franco What is sequential 3D? top tier device processing Top-tier anneals will impact bottom-tier stability and reliability Two options: Top tier Top-tier nFET PBTI reliability challenging without high-T anneal Top-tier (Si)Ge pFET reliable e ven without hi gh-T anneal Si pMOS trend Si nFET Si pFET 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 BTI max. |VG-Vth0| for 10Y [V] SiGe (Si cap) finFET SiGe (Si cap) r-Ge (Si cap) s-Ge SRB (Si cap) pMOS finFET s-Ge SRB (Si cap) BEOL r-Ge (GeOx) BEOL finFET s-Ge SRB (GeOx) Bottom tier Si nMOS trend r-Ge (Si cap) r-Ge (GeOx) InGaAs (Al2O3) Si pFET Si nFET nMOS 0.8 Tinv (≈EOT+0.4nm) [nm] 3. 6 BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

SUMMARY In addition to other metrics, reliability and in particular, gate oxide defects, determine the viability of future FET technologies (see Introduction) BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

NO TWO IDENTICALLY FABRICATED TRANSISTORS ARE ALIKE ANYMORE
VT ~ 1/(WL)1/2 100 The established simulation para digm Physical gate length 22nm Asenov et al., IEDM 2008 Physical gate length 9nm = 30x30x30 atoms These time-zero variations require adaptations in circuit design to account for statistical spread in device parameters BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

VARIABILITY SOURCES Random variation Systematic variation LER FER Tox
Source: K. Miyazaki, imec Random variation LER FER Tox (Line Edge Roughness) (Fin Edge Roughness) RDD (Random Discrete Dopant) Systematic variation MGG (Metal Gate Granularity) LDE (Layout Dependence Effect) BEOL (Back End Of Line) S/D Epi Stress BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

TIME-DEPENDENT DIELECTRIC BREAKDOWN VARIABILITY:WEIBULL “WEAKEST-LINK” STATISTICS
Thick oxide 1 -1 F)) (1 -2 - ln ( -3 t = 2.4 nm ln ox 4.6 11 -4 -5 normalized Q BD 1    t   F t   1 exp        ~1990 -1 -2 ln(-ln(1-F)) Thin oxide -3 t ox = 2.4 nm == nmnm oxox 3.4 3.43.4 4.6 4.64.6 11 7.5 -4 1111 ~2000 -5 0.01 2 0.1 4 6 8 1 normalized Q BD TDDB statistical (Weibull) distribution is linked to the number of traps in percolation path With oxide thickness scaling down the variability tends to increase (Weibull slope β decreases) Degraeve et al., IEDM 1995; Latest: Wu et al., IRPS 2016 BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

RTN: ΔVTH’S DUE TO SINGLE TRAPPED CHARGES ~EXPONENTIALLY DISTRIBUTED
Channel potential Source 2 B. Kaczer et al., IRPS 2010, EDL 2010 e.g. Ghetti et al., TED 2009  Vth 102 e  f1 (Vth , )  1 occurrence  1 101 η = 4.75 mV IDS Drain 2 100 t = 1900 s 10 stress Average single-step ΔVth: Asenov et al., TED 2003 20 30 40   CET N A -ΔVth (mV) LW Channel current non-uniform due to variability sources Impact of individual charges η reduced in MuGFETs (NA small) BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

BTI VARIABILITY: FULLY DESCRIBED BY EXPONENTIAL-
POISSON STATISTICS B. Kaczer et al., IRPS 2010; data: V. Huard et al., IRPS 2008 4 3 99.9 99 2 97 1 90 70 0 50 30 -1 10 3 -2 1 -3 0.1 0.01 99.99 99.9 99 97 90 70 NT = 1, 2, .., 20 50 30 10 3 1 0.1 0.01 3 2 ) N F ( it b pro - - Quantile percentile 1 2 ~total ΔVth NT = 6 NT = 9 η ≈ 4 mV -3 N = 14 80 T 40 120 160 ~ log stress time -ΔVth (mV) -ΔVth (mV) e N T  NT n  H (V )     n (n, V 1 /)  = single defect impact NT(t) = # of active defects per device    ,NT th n0 n!   n! th Known statistics  all moments can be derived Angot et al., IEDM 2013; Projections to high percentiles can be made BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016 Prasad et al., IRPS 2014

HCD STATISTICS: GENERATION OF DEFECTS CLOSE TO INTERFACE INCREASES VARIABILITY
Tail controlled by high-η distribution combined distribution (Monte Carlo) Liu et al., IEDM 2014; Kaczer et al., IRPS 2015; Bury et al., submitted to IRPS 2017; also: Weckx et al., IRPS 2015; Subirats et al., TED 2015 2 modes also in TFET: traps over junction and drift regions, Fiore et al., TDMR submitted BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

BOTH TIME-0 AND TIME-DEP’T VARIABILITY HAVE LOCAL AND GLOBAL COMPONENTS
Time-0 Time-dependent 1E-3 Threshold voltage variance (V2) 0.01 nFET nFET Logic, wide Logic, nominal SRAM, larger SRAM, smaller bulk SRAM 8x8 matrix 8x8 matrix local monitoring data Logic, wide Logic, nominal SRAM, larger SRAM, smaller bulk SRAM 8x8 matrix 8x8 matrix local monitoring data 1E-3 1E-4 1E-5 1E-4 Global Global BTI variance (V2) 1E-5 1E-6 Local var Local var V =50mV 1E-6 1E-7 T pFET pFET A. Kerber, EDL 2014 1E-3 1E-4 Global 1E-4 1E-5 1E-6 1E-7 Global 1E-5 1E-6 Local var ~ A-1 Local var ~ A-1 0.01 0.1 1 10 100 Normalized Area Time-0: Pelgrom et al., J. Solid State Circ Local variation Device-to-device (random) Time-dep’t: Matched-pairs: Rauch, TDMR 2002; Kaczer et al., EDL  A. Kerber, GF Local arrays: VLSI circuits can be also designed to measure degradation var TDDB: Roussel et al., IRPS RTN: Tega et al., VLSI 2009; Abe et al., IRPS  BTI: Kerber, EDL 2014; Weckx et al., IRPS 2015; Simicic et al., IRPS Global variation  HCD: Bury et al., submitted to IRPS Across-wafer (process) BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

tstress  V Avth t   2 total Vth distribution
TOTAL VARIABILITY = TIME-0 * TIME-DEPENDENT VARIABILITY VTH t   VTH 0  VTH t  Stress Time LxW = 35x90 nm2 tstress  K (VTH )   gVTH 0 ,TH 0 (VTH total Vth distribution Initial (time-0) VTH0 variability 2 V )H ,V / (V )dV TH Time-dependent VTH variability B   Kuhn et al., TED 2011 Avth t   2 VTH t  Kaczer et al., EDL 2015  V  TH 0 WL 2 2  V TH & WL Possible correlation between time-0 and time-dependent, see e.g. Kerber, EDL 2014 BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

SUMMARY As device dimensions reach nm length scales, all degradation mechanisms become distributed To keep up with this trend, statistical description of all major degradation mechanisms has been and is still being developed, based on deep understanding of gate-oxide defect properties Time-dependent variability is becoming comparable to time- zero (as-fabricated) variability and needs to be considered in addition to the latter BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

PRESENT STATUS OF CIRCUIT SIMULATIONS
BTI, HCI, ... T. Mizutani et al., IEDM 2013 25 20 mean Vth (mV) stress 15 10 T = 125 oC VG,stress = -2 V VG,relax = 0 V 5 500 time (s) 2000 Time-zero Reliability+Projection Combined effect P P V, T acceleration + = ΔP 0 operating time 0 operating time BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

CIRCUIT SIMULATIONS WITH VAR/REL
time-zero BTI, HCI,... variability T. Mizutani et al., IEDM 2013 15 10 5 -5 -10 -15 4 3 2 1 -1 -2 -3 quantile ΔVth (mV) tstress = 0 s -ΔVth (mV) time (s) Time-zero Rel/Var+Projection Combined effect P P BTI, HCI,... + = RTN 0 operating time 0 operating time BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

INTO CIRCUIT SIMULATIONS
DIFFERENT WAYS TO INTRODUCE DEGRADATION LEVEL 1 Constant <ΔVth> stress  Mean degradation VG ts,VG,T, DF, f t t LEVEL 2 Multi stress  Mean degradation complexity, accuracy <ΔVth> VG ts, VG, T, DF, f ts, VG, T, DF, f ts, VG, T, DF, f t t Multi stress  Mean degradation + variability  Variability + RTN LEVEL 3 ΔVth VG ts, VG, T, DF, f ts, VG, T, DF, f ts, VG, T, DF, f t t LEVEL 4 ΔVth VG t , V , T, t, VG, T, DF, f ts, VG, T, DF, f t, VG, T, DF, f s G DF, f t, VG, T, DF, f t , V , T, DF, f s G t t BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

REPRODUCES INDIVIDUAL DEFECT EVENTS
LEVEL 4:“ATOMISTIC” CIRCUIT SIMULATOR: Kaczer et al., IRPS 2011 BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

LEVEL 3: UNDERSTANDING BD IMPACT ON CIRCUIT
x G G RBD BS BD F FS FD S D S D W W 1.00 effective post-BD gate RG () 105 Kaczer et al., TED 2001 Post-BD nFET model calibrated V = 1.5 V SUPPLY cumulative fraction 0.75 VINP = 1.5 V 104 0.50 0.25 103 breakdown position x (m ) 0.00 f / f after 1st breakdown (%) Ring oscillator frequency change after 1st Hard BD reproduced, extension BDs have the largest impact BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

LEVEL 3: NON-MC PROPAGATION OF DISTRIBUTIONS TO OUTPUT PARAMETER VIA RESPONSE SURFACE
Projected total Vth distributions VDD WL WL PU1 PU2 g ξ f g f df Ci AC1 Qbar AC2 Q PD1 PD2 BLbar BL VSS Projections to ±7σ possible! VDD=90 % VDD=8 0% VDD= 70% VDD =60% VD D=50% V DD=40% VDD=30 % Ci VTH,2 VTH,1 SRAM SNM response surface SNM ξ Weckx et al., IRPS 2014 VTH,2 VTH,1 BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

IP BLOCK AGING FLOW Uses standard STA tools Courtesy P. Debacker
Aging-aware STA Custom scripts From gate level sim (Modelsim, NC-sim, or VCS) Cell netlist Voltage Temp Cell Activity Device level BTI model Custom scripts ∆Vth per instance ∆Vth per instance Trap Pc(t) ∆Vth per Cadence Tempus Or Synopsys Primetime instance Characterized by Cadence Liberate and Cadence Spectre (for various Vt shifts) ∆Vth per instance t0 Cell library Uniquif y ∆Vth per instance Aged Cell library Delay per instance t=f(slew, load) Courtesy P. Debacker Uniquify And Age Critical path timing Uniquified Design netlist Design netlist Traditional STA 75 BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

SUMMARY Examples show how understanding of gate-oxide defect physics can be propagated to transistor and logic-gate circuits BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

“DEFECT-CENTRIC” VIEW OF RELIABILITY
From individual defect properties to logic gate level and higher ESL HDL/RTL Gates ALU Circuits Compact models Device t ransport Trap k inetics 1st principles Understanding of degradation mechanisms at individual defect level is essential for simulations of time-dependent variability in circuits BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

ACKNOWLEDGEMENTS J. Franco, P.Weckx, Ph. Roussel, E. Bury, M. Cho, M.Toledano-Luque, M.Aoulaiche, R. Degraeve, G. Groeseneken, E. Simoen, H. Kukner, F. Catthoor, P. Raghavan,... T. Grasser,W. Goes, F. Schanovsky, S.Tyaginov, G. Rzepa, M. Bina,Yu. Illarionov, ... H. Reisinger, K. Rott,... A.Asenov, S.Amoroso, L. Gerrer, C. Millar, R. Hussin, F. Buchori... V.Afanas’ev,A. Stesmans, M. Houssa... G. Gielen, M. Simicic, S. Mahato, E. Maricau, P. De Wit, ... A. Kerber,T. Nigam, E. Cartier, E.Wu, J. Stathis ... J. Martin-Martinez, R. Fernandez, R. Rodriguez, M. Nafria... J. Zhang, Z. Ji, M. Duan, ... G.Wirth,V. V. de Almeida Camargo, M. B. da Silva, ... C. Chen, J.Watt, L. Li, K. Chanda,... V. Huard,... F. Crupi, L.Trojman, L. M. Procel,... A. Chaudhary, S. Mukhopadhyay, S. Mahapatra,A.Alam, ... P. Pfeifer, Z. Pliva, ... M. Karner, C. Kernstock, Z. Stanojevic, O. Baumgartner,... A. Kuo, P.Tseng BEN KACZER: PRESENT AND FUTURE OF FEOL RELIABILITY, IEDM, DEC 3, 2016

PRESENT AND FUTURE OF FEOL RELIABILITY

Similar presentations

Presentation on theme: "PRESENT AND FUTURE OF FEOL RELIABILITY"— Presentation transcript:

Similar presentations

About project

Feedback

Log in

Auth with social network:

PRESENT AND FUTURE OF FEOL RELIABILITY

Similar presentations

Presentation on theme: "PRESENT AND FUTURE OF FEOL RELIABILITY"— Presentation transcript:

Similar presentations

About project

Feedback