Altera Training Course

Altera Training Course

Agenda Introduction Device Architecture MAX+PLUS II Design Flow
MAX 7000 / MAX 9000 / MAX 3000 Family FLEX 8000 / FLEX 10K / FLEX 6000 Family APEX Family MAX+PLUS II Design Flow Design Compilation Simulation Timing Analysis Programming Others (Floorplan Editor)

Altera General-Purpose Logic Devices
FLEX FLEX10K FLEX8000 FLEX6000 CMOS PLDs Simple PLDs High-Density PLDs FPGAs MAX MAX 9000 MAX 7000 MAX 5000 Classic Xilinx Lucent Quicklogic Actel CMOS PLDs Simple PLDs High-Density PLDs FPGAs CPLDs FLEX FLEX10K FLEX8000 FLEX6000 APEX APEX 20K Xilinx Lucent Quicklogic Actel MAX 9000 MAX 7000 MAX 5000 Classic

Introduction to Altera
Inventor of the CPLD in 1983 Products Families Product Term-based (EPROM, EEPROM) MAX 7000 MAX 9000 Look-Up Table-based (SRAM) FLEX 10K FLEX 8000 FLEX 6000 LUT + P-Term + Memory(SRAM) System-on-a-Programmable-Chip APEX 20K

Altera Device Terminology
Logic Cell The basic building block of an Altera device Macrocell The basic building block of Product Term-based device MAX9000, MAX7000, MAX5000, Classic Logic Element The basic building block of Look-Up Table-based device FLEX10K, FLEX8000, FLEX6000 Logic Array Block(LAB) A collection or group of logic cells

Product Term-Based Building Blocks
Programmable-AND, Fixed-OR Array XOR Gate for Synthesis or Inversion Capacity Limited by Number of Product Terms High Number of Inputs Notes:

Look-Up Table-Based Building Blocks
An n-input LUT Can Implement Any Function of n Inputs (e.g., n-Input AND, n-Input XOR) Functions & Equations with More than n Inputs Are Split between LUTs Input 1 Black Box LUT Input 2 Output Input 3 Notes: Input 4

Which PLD Should I Use? Altera’s Solution Complex Combinatorial Logic
Product Term Architecture Look-Up Table Architecture Complex Combinatorial Logic Complex State Machines Control-Intensive Logic Fully Encoded State Machines High Fan-In Examples Memory Bus Controller Decode Logic Datapath Functions “Register-Rich” Designs Arithmetic Functions Adders, Counters, etc. “One Hot” Encoded State Machines Examples DSP Functions PCI Interface Notes: Altera’s Solution MAX FLEX

MAX 7000 Device Technology Multiple Array MatriX (MAX) devices :
programmable - AND / fixed - OR product term architecture Altera MAX 7000 devices include: MAX 7000 MAX 7000E MAX 7000S MAX 7000A MAX 7000B EPLDs fabricated on CMOS process EEPROM configuration elements (non-volatile)

MAX 7000(E)(S) Family Features ...
High-performance, mid-density EPLD standard 32 ~ 256 macrocells, 600 ~ 5,000 usable gates 5 V MAX 7000(E) devices and 5 V ISP MAX 7000S In-System Programmability(ISP) in MAX 7000S Built-in JTAG BST circuitry in MAX 7128S or above 5 ns pin-to-pin delays with up to MHz counter frequency PCI-compiliant devices available Open-drain output option in MAX 7000S Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable power-saving mode for a reduction of over 50 % in each macrocell

MAX 7000(E)(S) Family More Features ...
Allowing up to 32 product terms per macrocell using expander Programmable security bit for protection of designs 3.3 V or 5 V MultiVolt I/O interface operation(above 68-pin packages) Non-E Versions for Smaller Devices (7032,7064,7096) E Versions for Larger Devices (7128, 7160, 7192, 7256) S Versions for All Devices Enhanced features in MAX 7000E and MAX 7000S More Output Enable Control Signals(6 Pin/Logic Driven vs. 2 Pin) More Global Clock signals with optional inversion(2 Global Clocks vs. 1) Enhanced interconnect resources for improved routability Fast input registers Programmable output slew-rate control

MAX 7000 Family EPM7032 EPM7128E EPM7256E EPM7064 EPM7032V EPM7128S
EPM7384AE EPM7512AE Feature EPM7032S EPM7096 EPM7128A EPM7256A EPM7064AE EPM7160S EPM7192S EPM7384B EPM7512B EPM7032AE EPM7128AE EPM7256AE EPM7064B EPM7032B EPM7128B EPM7256B Macrocells 32 64 96 128 160 192 256 384 512 Usable Gates 600 1250 1800 2500 3200 3750 5000 7500 10000 Flipflops 32 64 96 128 160 192 256 384 512

Device Part Numbers EPM7128ATC144-6 Another Example: EPM7064SLC44-5
EPM = Family Signature (Erasable Programmable MAX device) 7128A = Device type (128 = number of macrocells) T = Package type (L = PLCC, T = TQFP...) C = Operating temperature (Commercial, Industrial) 144 = Pin count (number of pins on the package) -6 = Speed Grade (-5, -6, -7, -10, -12, -15) Suffix may follow speed grade (for special device features) Another Example: EPM7064SLC44-5 EPM7064S in a commercial-temp, 44 pin PLCC package with a 5 ns speed grade

Device Block Diagram P I A 4 dedicated inputs drive PIA, Macrocells,
I/O Control Block I/O Control Block 36 36 16 Macro- cells 16 Macro- cells 16 16 P I A 3 to 16 3 to 16 36 36 16 Macro- cells 16 Macro- cells 16 16 3 to 16 3 to 16 3 to 16 I/O pins 3 to 16 fast input paths MAX 7000E/S/A/B devices only Logic Array Block (LAB)

MAX 7000/E/S Macrocell LAB Local Array
Global Clock(s) MAX > MAX 7000E/S -> 2 LAB Local Array Global Clear Parallel Expanders from other macrocells From I/O Pin Fast Input Select -> MAX 7000E/S only Register Bypass To I/O Control Block PRN D Q Product-Term Select Matrix EN CLRN Clear Select Clock/ Enable Select Shareable Logic Expanders To PIA 16 shared expander product terms

Logic Array Block LAB Local Array
INPUT GCLK1 The dedicated inputs are shown here for MAX 7000E, MAX 7000S, MAX 7000A and MAX 7000B devices. See next slide for more information. INPUT GCLK2 INPUT GCLR GOE INPUT Programmable Interconnect Array (PIA) 36 3 to 16 fast input paths MAX 7000E/S/A/B devices only 16 Macrocell 1 Macrocell 2 I/O Control Block Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 LAB Local Array 3 to 16 Macrocell 8 Macrocell 9 Macrocell 10 Macrocell 11 3 to 16 I/O pins Macrocell 12 Macrocell 13 Macrocell 14 Macrocell 15 Macrocell 16 16 Shared Logic Expanders

MAX 7000E/S/A/B MAX 7000 4 Dedicated Inputs can drive
GCLK1 GCLK1 INPUT OE1n INPUT OE2/GCLK2 INPUT OE2n GCLRn INPUT INPUT OE1 GCLRn INPUT INPUT Programmable Interconnect Array (PIA) 4 Dedicated Inputs can drive any macrocell control signal (clock, clear, preset, enable) data any combination of above (if the input drives a control signal as well as different type of control signal or data then the control signal will be non-global) LAB Local Array 6 to 16 I/O pins Shared Logic Expanders

Parallel Expanders from other macrocells Shareable Logic Expanders
LAB Local Array Parallel Expanders from other macrocells Expanders are used to create logic functions requiring more resources than in a single macrocell Product-Term Select Matrix Shareable Logic Expanders When expanders are needed to implement a logic function, shared expanders are automatically used by default 16 shared expander product terms

Shareable Logic Expanders
} Each macrocell can donate one product term as a shared expander instead of using it as a standard product term Each LAB can have up to 16 shared expanders that can be used by any or all macrocells in the LAB LAB Local Array Macrocell Product- Term Logic ù } ù ù Macrocell Product- Term Logic ù ù ù

Parallel Expanders From previous
macrocell Parallel expanders are unused product terms that can be allocated to neighboring macrocells Preset Product-Term Select Matrix parallel expanders GND Clock Clear Parallel expanders implement faster complex logic functions Preset Product-Term Select Matrix GND To next macrocell LAB Local Array Clock Clear

Parallel Expanders vs. Shareable Expanders

MAX 7000 I/O Control Block VCC OE1 OE control OE2 GND from Macrocell
to PIA

MAX 7000E/S I/O Control Block
6 Global OEs P I A VCC OE control GND from Macrocell Open-Drain (MAX 7000S devices only) Slew-Rate Control Fast Input to Macrocell Register to PIA

Special Features Programmable Speed/Power Control Slew-Rate Control
Each Macrocell Can Be Programmed for Either High Speed (Turbo Bit on) or Low Power (Turbo Bit off) Slew-Rate Control MAX 7000E & MAX 7000S Output Buffers Have an Adjustable Output Slew Rate that Can Be Configured for Low-Noise or High-Speed Performance Open-Drain Output Option Each MAX 7000S I/O Pin Can Provide an Open-Drain Output Notes:

MAX7000A Features... 32 ~ 512 macrocell, 6000~ 10,000 usable gates
3.3V in-system programmability(ISP) - Built in JTAG boundary-scan test(BST) circuitry Enhanced ISP features in MAX 7000AE Enhanced ISP algorithm for faster programming ISP_Done bit to ensure complete programming Pull-up resistor on I/O pins during ISP 4.5 ns pin-to-pin delays with up to MHz counter freq. Hot-socketing in MAX 7000AE Programmable power-up states for macrocell register in MAX 7000AE Programmable power-saving mode

MAX7000A More Features... Programmable security bit
6 to 10 pin or logic driven output enable signals Two global clock signals with optional inversion Fast input registers Programmable output slew-rate control Programmable ground pins PCI compliant Open-drain output option MultiVolt I/O interface with 2.5V, 3.3V, 5V

MAX 9000 Family Features... High performance and high density EPLD
320 ~ 560 macrocells, 6,000 ~ 12,000 usable gates 5 V ISP via built-in JTAG interface Dual-output macrocell for independent use of combinatorial and registered logic FastTrack Interconnect Input/Output registers on all I/O pins 10 ns pin-to-pin delays up to 144 MHz counter frequency PCI compliant (-12 speed grade) 3.3V or 5 V I/O operation/MultiVolt I/O interface Programmable output slew-rate control

Note: Use Altera’s web site to check device and package availability
MAX 9000 Family EPM9320 EPM9560 Feature EPM9400 EPM9480 EPM9320A EPM9560A Macrocells 320 400 480 560 Usable 6,000 8,000 10,000 12,000 Gates Flipflops 484 580 676 772 Note: Use Altera’s web site to check device and package availability

MAX 9000 Device Block Diagram
IOC IOC IOC IOC 4 dedicated inputs drive FastTrack Interconnect, Macrocells, I/O Cells 10 IOCs at the end of each Column IOC IOC 8 IOCs at the end of each Row 16 macrocells 16 macrocells 16 macrocells 16 macrocells IOC IOC 16 macrocells 16 macrocells 16 macrocells 16 macrocells IOC IOC 16 macrocells 16 macrocells 16 macrocells 16 macrocells FastTrack Interconnect Logic Array Block (LAB) IOC IOC IOC IOC

MAX 9000 Logic Array Block LAB Local Array Row FastTrack Interconnect
DIN1 GCLK1 To peripheral control bus and other LABs in the device DIN2 GCLK2 GCLR DIN3 DIN4 GOE To peripheral control bus Row FastTrack Interconnect 33 16 16 Macrocell 1 Column FastTrack Interconnect 16 48 Macrocell 2 Macrocell 3 Each macrocell can drive both the Row and Column Interconnect at the same time Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 LAB Local Array Macrocell 8 16 48 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 Macrocell 13 Macrocell 14 Local feedback Macrocell 15 Macrocell 16 16 16 Shared Logic Expanders

} MAX 9000 Dedicated Inputs LAB Local Array
GCLK1 To peripheral control bus and other LABs in the device DIN2 GCLK2 DIN3 GCLR GOE DIN4 To peripheral control bus Row FastTrack Interconnect 33 16 16 Macrocell 1 16 48 Macrocell 2 Macrocell 3 Column FastTrack Interconnect Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 LAB Local Array Macrocell 8 16 48 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 Macrocell 13 Macrocell 14 Macrocell 15 Macrocell 16 16 16

MAX 9000 Dedicated Inputs 2 Dedicated Global Clock Inputs Can Drive:
Any Macrocell Control Signal (Clock, Clear, Preset, Enable) Clock Signals on Peripheral Control Bus* Data Any Combination of Above (Non-Global Signal Use May Result)** 1 Dedicated Global Clear Input Can Drive: Clear and Clock Enable Signals on Peripheral Control Bus* 1 Dedicated Global OE Input Can Drive: Output Enable, Clock Enable, and Clear Signals on Peripheral Control Bus* * Peripheral control bus signals drive I/O Cells (IOCs) ** Data loading on non-global signals will add delay

MAX 9000 Macrocell Parallel Expanders from other macrocells
33 Row FastTrack Interconnect inputs Global Clear Global Clocks LAB Local Array This path from P-Term Select Matrix supports register packing 2 To FastTrack Interconnect PRN Product-Term Select Matrix D Q EN CLRN Local Array Feedback Clear Select Clock/ Enable Select Shareable Logic Expanders 16 local feedbacks 16 shared expander product terms

Register Packing Combinatorial Function Registered Function
The macrocell’s combinatorial and registered functionality is used independently (dual output) This feature can be turned on or off through a Logic Option in MAX+plus II XOR p-term Clock XOR p-term Clear p-term Preset To FastTrack Interconnect Registered Function p-term Preset Single p-term Input D Q EN Global Clock CLRN p-term Clock To Local Feedback VCC p-term Clear

MAX 9000 I/O Cell Peripheral Control Bus [12..0] OE[7..0]
VCC OE[7..0] 8 to Row or Column FastTrack Interconnect 13 from Row or Column FastTrack Interconnect D Q CLK[3..0] Slew-Rate Control 4 VCC ENA CLRN ENA[5..0] 6 VCC CLR [1..0] 2

I/O Cell Register Peripheral Control Bus [12..0] VCC OE[7..0] to Row or Column FastTrack Interconnect 8 13 from Row or Column FastTrack Interconnect D Q CLK[3..0] The I/O cell register can be used for fast setup times (tSU) or fast clock to out times (tCO) 4 VCC ENA CLRN ENA[5..0] 6 VCC CLR [1..0] 2

Peripheral Control Bus [12..0]
Output Enables Peripheral Control Bus [12..0] VCC OE[7..0] 8 13 D Q Slew-Rate Control Available Output Enables Up to 8 OE signals (including the dedicated OE input) from the Peripheral Control Bus

Slew-Rate Control Peripheral Control Bus [12..0] VCC OE[7..0] 8 to Row or Column FastTrack Interconnect 13 from Row or Column FastTrack Interconnect D Q When Slow Slew Rate is selected, board-level noise is reduced and a timing delay is added to the output buffer delay parameter Compare tOD1, tOD2, tOD3 in the Data Book Slew-Rate Control

FLEX 8000 Family Features... Low-cost, high-density, register-rich(282 ~ 1,500) 208 ~ 1,296 Logic Elements, 2,500 ~ 16,000 usable gates In-Circuit Reconfigurability(ICR) Built-in JTAG BST circuitry PCI compliant Programmable output slew-rate control I/O registers for fast setup and clock-to-output delay 3.3V or 5.0V operation Four global inputs with inversion capability FastTrack Interconnect continous routing structure Dedicated carry and cascade chain

FLEX 8000 Devices All Devices Except The EPF8452A And EPF81188A
EPF8282AV 2,500 208 282 78 Yes EPF8452A 4,000 336 452 120 No EPF8636A 6,000 504 636 136 Yes EPF8820A 8,000 672 820 152 Yes EPF81188A 12,000 1,008 1,188 184 No EPF81500A 16,000 1,296 1,500 208 Yes Max. Usable Gates Logic Elements Registers Max. User I/O JTAG BST Packages Refer to for latest packaging information All Devices Except The EPF8452A And EPF81188A Have JTAG BST Circuitry

FLEX 8000 Block Diagram 4 Dedicated Inputs I/O Element (IOE)
Row FastTrack Interconnect Logic Array Block Logic Element Local Interconnect Column FastTrack Interconnect

FLEX 8000 Dedicated Inputs 4 Dedicated Inputs Drive 4 Global Control Nets that Can Drive: Any LE Register Control Signal (Clock, Clear) Any Signal (Clock, Clear, Output Enable) on “Peripheral Control Bus” Peripheral Control Bus Controls I/O Elements (IOE) Data Any Combination of Above

FLEX 8000 LAB Dedicated Inputs Row Interconnect LAB Local Interconnect
Control Signals LE1 LE2 LE3 LE4 LE5 LE6 LE7 LE8 Column Interconnect

FLEX 8000 Logic Element Carry-In Cascade-In To Row, Column, & LAB
Local Interconnects DATA1 Look-Up Table (LUT) Carry Chain Cascade Chain PRN CLRN DATA2 D Q DATA3 DATA4 LAB Clear/ Preset 1 Clear/ Preset Logic LAB Clear/ Preset 2 Clock Select LAB Clock 1 LAB Clock 2 Carry-Out Cascade-Out

Architecture Features
Controlling These Features Controls Design Implementation, Performance & Utilization Carry Chain Arithmetic Functions Cascade Chain Wide Fan-in Functions

Carry Chain Implements fast adders, counter and comparators Carry-In
(from previous LE) A1 B1 A2 B2 LUT Carry Chain DFF S1 S2 Next LE(s)

Cascade Chain Cascades LUT Outputs, Implementing High-Performance, Wide Fan-in Functions LE LUT in[3..0] LE2 LUT in[7..4] LEn LUT Result of Inputs in[0] to 4[n-1] in[4n (n-1)]

Without Cascade Chains: 3 LEs Using Cascade Chains: 2 LEs
Cascade Chain Example Without Cascade Chains: 3 LEs LE LUT in[2..0] in[5..3] in[7..6] result in0 in2 in1 in3 in4 in5 in6 in7 result 8-Input AND Gate Using Cascade Chains: 2 LEs LE in[3..0] LUT LE2 in[7..4] LUT result

Carry and Cascade Chain Construction
Begins in First LE (LE1) of Every LAB Function’s Carry Chain Can Begin in Any LE of an LAB Runs Downward through LEs of a LAB At End of LAB, carry chain continues to Top of Next LAB in Same Row Stops at End of Row FLEX 8000

Using Carry Chains in Your Design
Number of Chains No More Than 20% of FLEX Device Should Use Carry Chains Length of Each Chain Maximum Length Should Be 32 LEs for Performance For Ripple-Carry Longer than 32 LEs, Consider Carry Look-Ahead or Carry-Select Implementations to Improve Performance Carry Chains Longer Than 32 LEs May Still Provide Utilization Advantages Further Reading AN 36: Designing with FLEX 8000 Devices MAX+PLUS II Online Help: Search on “Carry”

Using Cascade Chain Cascade Chains Can Improve Density, Performance
LEs Locked Together, Challenging Fitting of Logic Recommendations No More Than 20% of the FLEX Device Should Use Cascade Chains Maximum Length Should Be 2 LEs for Performance Cascade Chains Longer Than 2 LEs May Still Provide Utilization Advantages Further Reading AN 36: Designing with FLEX 8000 Devices MAX+PLUS II Online Help: Search on “Cascade”

Synthesis Styles & FLEX Features
NORMAL Will Ignore Any Carry or Cascade Chains NORMAL FAST Will Use Carry & Cascade Primitives Manually Entered in Design & Automatically Synthesize More Where Appropriate FAST WYSIWYG WSIWYG Will Use Only Carry & Cascade Primitives Manually Entered in Design

FLEX 8000 IOE

FLEX 6000 Features... Register-rich, LUT-based, OptiFLEX architecture
800 ~ 1960 LEs, ~ gates Low-cost alternative to gate arrays for high-volume production Built-in low-skew clock distribution tree Built-in JTAG circuitry MultiVolt I/O PCI compliant Individual tri-state output enable control for each pin 3.3 V devices support hot-socketing

All Devices Have JTAG BST Circuitry
FLEX 6000 Devices EPF6010A EPF6016 EPF6016A EPF6024A Max. Usable Gates Logic Elements Registers Max. User I/O Packages 10,000 880 139 16,000 1,320 204 24,000 1,960 218 Refer to for latest packaging information All Devices Have JTAG BST Circuitry

FLEX 6000 Block Diagram 4 Dedicated Inputs Chip-Wide Reset
Output Enable Column Interconnect IOE Row Interconnect LAB LAB Local Interconnect

FLEX 6000 Global Nets 4 Global Control Nets Designed for High Fan-out Signals Any Register Control Signal (Clock, Clear) Data Combination of Data & Register Control Signals Global Control Nets Can Be Driven by Dedicated Inputs Internal Logic

FLEX 6000 LAB LEs 1-5 LEs 6-10 Row Interconnect Global Nets LAB Local
LAB Control Signals LEs 1-5 LEs 6-10

FLEX 6000 LAB Control Signals
4 Global Nets LAB Local Interconnect data1 LE1 LAB Clock 1 data2 LAB Clock 2 Synchronous Load data3 LAB Clear/Preset 1 data4 LAB Clear/Preset 2 Synchronous Clear Each LAB Supports For Registers 2 Clock Signals 2 Clear/Preset Signals For Counters Using Carry Chains* Synchronous Load Synchronous Clear

FLEX 6000 Logic Element Carry-In Cascade-In DATA1 Look-Up Table (LUT)
Chain Cascade Chain PRN CLRN DATA2 LE Out D Q DATA3 DATA4 LAB Clear/ Preset 1 Clear/ Preset Logic LAB Clear/ Preset 2 Chip-Wide Clear Clock Select LAB Clock 1 LAB Clock 2 Carry-Out Cascade-Out

User-Controlled Architectural Features Affects Performance & Utilization Carry Chain Arithmetic Functions Cascade Chain Wide Fan-in Functions These Features Are Controlled Using: Logic Options Synthesis Styles

LE-to-LE Connection: LAB Interconnect Only
LEs of Adjacent LABs Can Communicate through Their Shared LAB Local Interconnects: Provides a Very Fast Path (See Appendix Local Routing) LEs 1-5 Drive to the Right; LEs 6-10 Drive to the Left LEs Are Driven by Both Adjacent LAB Local Interconnects Data Inputs 2 & 4 Come from the Right Data Inputs 1 & 3 Come from the Left Any Channel of a LAB Local Interconnect Can Drive Any LEs of an Adjacent LAB 10 10 10 10 LEs 1-5 LEs 1-5 LAB Local Interconnect LAB Local Interconnect LAB Local Interconnect 5 5 5 5 LEs 6-10 LEs 6-10 10 10 10 10

Row Outputs Row Interconnect LAB Local Interconnect LAB
Any LE Can Drive through Row or Column Interconnect to Any IOE Row Interconnect 10 IOEs at End of Each Row LAB Local Interconnect LAB 10 Each IOE Is Driven by Any Channel in Adjacent LAB Local Interconnect All 10 LEs in Row-End LABs Can Drive Row IOEs through Adjacent LAB Local Interconnect for Fast Clock-to-Output

Chip-Wide Output Enable
FLEX 6000 IOE to Row or Column Interconnect Delay Chip-Wide Output Enable VCC from LAB Local Interconnect VCC I/O Pin from LAB Local Interconnect Slew-Rate Control (Selectable per Pin) Open-Drain Output (Selectable per Pin)

FLEX 10K Family Features... Industry’s first embedded array PLD(memory function) 10,000 ~ 250,000 typical gates 6,144 ~ 40,960 RAM bits (10K, 10KA) 24,576 ~ 98,304 RAM bits(10KE) ICR, built-in JTAG, PCI compliant MultiVolt I/O interface support ClockLock and ClockBoost option for reduced clock delay/skew and clock multiplication Pull-up clamping diode for 3.3 V PCI compliance Individual tri-state output enable control for each pin Open-drain option on each I/O pin Programmable ouptut slew-rate control Hot-socketing support (10KA, 10KE)

FLEX10K family Various supply voltage, family
-- 10K -- 5 V ( 10,000 ~ 100,000 typical gate) -- 10KA V ( 10,000 ~ 250,000 typical gate) -- 10KV V ( 50,000 , 130,000 typical gate) -- 10KE V ( 30,000 ~ 200,000 typical gate) MultVolt interface -- 10K V, 5V interface -- 10KA V, 3.3V, 5V interface -- 10KV V , 5V interface -- 10KE V, 3.3V, 5V interface

FLEX 10K/V/A/B Devices All Devices Have JTAG BST Circuitry
Typical Gates Features Registers Max. User I/O 10,000 EPF10K10 EPF10K10A 720 134 20,000 EFP10K20 1,344 189 30,000 EFP10K30 EPF10K30A 1,968 246 40,000 EFP10K40 2,576 50,000 EFP10K50 EPF10K50V EPF10K50A 3,184 310 70,000 EFP10K70 4,096 358 100,000 EFP10K100 EPF10K100A EPF10K100B 5,392 406 130,000 EPF10K130V EPF10K130A 7,120 470 250,000 EPF10K250A Logic Elements 576 1,152 1,728 2,304 2,880 3,744 4,992 6,656 12,160 RAM Bits 6.144 12,288 16,384 20,480 18,432 24,576 32,768 40,960 12,624 All Devices Have JTAG BST Circuitry (IEEE Std Compliant) Available at No Logic Cost Refer to for Latest Packaging Information

FLEX 10KE Devices All Devices Have JTAG BST Circuitry
Typical Gates Features Registers Max. User I/O 30,000 EPF10K30E 1,968 246 50,000 EPF10K50E 3,184 310 100,000 EPF10K100E 5,392 406 130,000 EPF10K130E 7,120 470 Logic Elements 1,728 2,880 4,992 6,656 RAM Bits 24,576 40,960 49,152 65,536 EPF10K200E 200,000 9,984 98,304 10,448 All Devices Have JTAG BST Circuitry (IEEE Std Compliant) Available at No Logic Cost Refer to for Latest Packaging Information

FLEX 10K Family Block Diagram
4 Dedicated Inputs, 2 Dedicated Clocks Chip-Wide Reset, Chip-Wide Output Enable Peripheral Control Bus Row FastTrack Interconnect Embedded Array Block (EAB) Logic Array Block I/O Element (IOE) Embedded Array Block (EAB) Local Interconnect Logic Element Column FastTrack Interconnect

Dedicated Inputs, Clocks
4 Dedicated Inputs Drive 4 Global Control Nets that Can Drive Any LE Control Signal (Clock, Clear, Enable) Four Nets of the “Peripheral Control Bus” (Clock, Clear, Output Enable) Data Any Combination of Above 4 Global Control Nets Can Also Be Driven by Internal Logic 2 Dedicated Clocks Drive 2 Global Clock Nets that Can Drive LE Clock Signals IOE Clock Signals Cannot Serve as Any Other Control Signal

FLEX 10K Family LAB Global Control Nets, Dedicated Clocks
Row Interconnect LAB Local Interconnect Column Interconnect LAB Control Signals LE1 LE2 LE3 LE4 LE5 LE6 LE7 LE8

FLEX 10K Family LAB Control Signals
Global Control Nets LAB Clock 1 LAB Clock 2 LAB Clear/Preset 1 LAB Clear/Preset 2 4 LAB Local Interconnect Dedicated Clocks 2 When going over what’s on this slide, point out that the significance of these controls being able to be driven by the LAB Local Interconnect means that they can be internally-generated and MAX+plus II will route then through the Interconnect so that they can control registers in this LAB. Each LAB Supports for its Registers 2 Clock Signals 2 Clear/Preset Signals

FLEX 10K Family Logic Element
Multiplexer for Register Packing Carry-In Cascade-In DATA1 Look-Up Table (LUT) Carry Chain Cascade Chain PRN CLRN To Row, Column Interconnects DATA2 D Q DATA3 DATA4 ENA LAB Clear/ Preset 1 Clear/ Preset Logic To LAB Local Interconnect LAB Clear/ Preset 2 Chip-Wide Reset Clock Select LAB Clock 1 LAB Clock 2 Carry-Out Cascade-Out

Controlling These Features Controls Design Performance & Utilization Register Packing Allows Using LUT & Register of Same LE Separately Carry Chain Arithmetic Functions Cascade Chain Wide Fan-in Functions Features are Controlled through MAX+plus II

Register Packing Allows LUT & Register of a LE to Be Used Separately
Multiplexer for Register Packing Carry-In Cascade-In DATA1 Look-Up Table (LUT) Carry Chain PRN CLRN To Row, Column Interconnects Cascade Chain DATA2 D Q DATA3 DATA4 ENA LAB Clear/ Preset 1 Clear/ Preset Logic To LAB Local Interconnect LAB Clear/ Preset 2 Chip-Wide Reset Clock Select Allows LUT & Register of a LE to Be Used Separately Can Improve Utilization LAB Clock 1 LAB Clock 2 Carry-Out Cascade-Out

Carry Chain Carry-In Carry Chain Carry-Out Cascade-In DATA1 Look-Up
Table (LUT) Carry Chain PRN CLRN To Row, Column Interconnects Cascade Chain DATA2 D Q DATA3 DATA4 ENA LAB Clear/ Preset 1 Clear/ Preset Logic To LAB Local Interconnect LAB Clear/ Preset 2 Chip-Wide Reset Clock Select LAB Clock 1 LAB Clock 2 Carry-Out Cascade-Out

Cascade Chain Cascades LUT Outputs, Implementing High-Performance, Wide Fan-in Functions LE LUT in[3..0] LE2 LUT in[7..4] LEn LUT Result of Inputs in[0] to 4[n-1] in[4n (n-1)]

I/O Element

EAB A Large Block of Embedded RAM
10K/V/A/B Bits, Single-Port RAM 10KE Bits, Dual-Port RAM EAB EAB

Available RAM in FLEX 10K Family Devices
One EAB per Row in all FLEX 10K Family Devices RAM Bits Device Rows 10K/V/A/B 10KE EPF10K10/A 3 6,144 EPF10K ,288 EPF10K30/A/E 6 12,288 24,576 EPF10K40A 8 16,384 EPF10K50/V/A/E 10 20,480 40,960 EPF10K ,432 EPF10K100/A/B/E 12 24,576 49,152 EPF10K130/V/E 16 32,768 65,536 EPF10K200E ,304 EPF10K250A/E 20 40,960 81,920

EAB EAB Can Be Configured Four Ways: FLEX 10K/V/A/B EAB 2,048 Bits RAM
FLEX 10E EAB 4,096 Bits RAM 256 x 8 512 x 4 1,024 x 2 2,048 x 1 256 x 16 512 x 8 1,024 x 4 2,048 x 2

Cascading EABs for Memory
EABs Cascaded to Create Wider RAM EABs Cascaded, Multiplexed to Create Deeper RAM No Speed Penalty up to 10K/V/A/B - 2,048 Bits Deep 10KE - 4,096 Bits Deep MAX+plus II Configures RAM in Fastest Way Possible 256 x 16 256 x 32 256 x 16

FLEX 10K/V/A/B EAB 1, 2, 4, 8 RAM/ROM 2,048 Bits 1, 2, 4, 8 Data In D D Data Out 11, 10, 9, 8 Address D EAB contains registers for incoming and outgoing signals 256 x 8 512 x 4 1,024 x 2 2,048 x 1 Write Enable D Write Pulse Circuit In Clock Out Clock

10KE EAB EAB contains registers for incoming and outgoing signals
Data Out D ENA Data In D ENA RAM/ROM 4,096 Bits Write Address D ENA 256x16 512x8 1024x4 2048x2 Write Enable D ENA Write Pulse Circuit EAB contains registers for incoming and outgoing signals Read Address D ENA Read Enable D ENA Clock 1 Clock 1 Enable Clock 2 Clock 2 Enable

MAX+plus II’s MegaWizard
Memory Elements are Created with MAX+plus II’s MegaWizard Manager Dual-Port RAM FIFO LPM_FF LPM_LATCH LPM_RAM_DQ LPM_RAM_IO LPM_ROM LPM_SHIFTREG

MegaWizard Manager Output
Selection of Output Files: AHDL File VHDL Component to Instantiate Verilog Component to Instantiate Automatically Generated Symbol for Schematic Include File

Memory Elements and Implementation
Elements Implemented in LEs: LPM_FF - An Array of D Flip-Flops (DFFEs in LEs) LPM_LATCH - An Array of Latches (LUTs in LEs) LPM_SHIFTREG - Shift Register Elements Implemented in LEs and/or EABs: Dual-Port RAM FIFO LPM_RAM_DQ (Separate Read & Write Data Ports) Recommended over LPM_RAM_IO LPM_RAM_IO (Single, Bi-directional Data Port) LPM_ROM

Use of EAB Logic Functions Memory Functions
Area-efficient and fast for complex functions DSP Arithmatic Logic Microprocessor / Microcontroller Memory Functions RAM ROM Dual-port RAM FIFO

APEX™ 20K & Quartus Overview

APEX 20K The Best of All Worlds FLEX 10K MAX 7000 FLEX 6000
Interconnect Embedded Memory High Density Phase-Locked Loop MAX 7000 Product Terms Wide Fan-in Fast State Machines APEX 20K FLEX 6000 Interleaved LABs LE Structure I/O Structure

APEX 20K Features 125-MHz System Performance
64-Bit, 66-MHz PCI Compliance 4-Level Continuous FastTrack® Interconnect New Level of Routing Hierarchy Enhanced Phase-Locked Loop (PLL) Advanced I/O Standard Support Includes SSTL-3, GTL+, LVDS, and More MultiVolt™ I/O Interface Advanced FineLine BGA Packaging

APEX 20K Devices Logic Elements RAM Bits Macrocells Gates User I/O
250 780 EP20K100 EP20K160 EP20K200 EP20K300 EP20K400 EP20K600 EP20K1000 4,160 6,400 8,320 11,520 16,640 24,320 42,240 Logic Elements 53K 82K 106K 147K 213K 311K 541K RAM Bits 416 640 832 1,152 1,664 2,432 4,224 Macrocells

APEX 20K Supply Voltage 2.5 V Core VCC 1.8 V Core VCC 0.25/0.22 µ
EP20K200 EP20K400 EP20K100 1.8 V Core VCC 0.18 µ EP20K1000E EP20K600E EP20K400E EP20K200E EP20K160E EP20K300E EP20K100E Comes up with first wave; click to get 20KEs.

MultiCore™ Architecture
LUT P-Term Memory FLEX 6000 Model MAX 7000 Model FLEX 10KE Model

FineLine BGA™ Efficiency
Traditional BGA 1.27 mm Ball Pitch 27 mm 256 Balls 35 mm 356 Balls 45 mm 600 Balls Requires Less than Half the Board Real Estate FineLine BGA 1.0 mm Ball Pitch 23 mm 484 Balls 17 mm 256 Balls 27 mm 672 Balls Area » 100-Pin TQFP

SameFrame™ Pin-Out Advantage
FineLine BGA 484-Pin FineLine BGA 256-Pin FineLine BGA Starts with PC board pattern. Click once to bring 256 on; click again to morph to 484; click again to morph back down to 256.

Embedded System Block Product Term ESB RAM ROM CAM

APEX 20K I/O Features Supports Multiple I/O Standards
LVTTL, LVCMOS GTL+, CTT, AGP HSTL, SSTL-2, SSTL-3 LVDS Hot Socketing Support MultiVolt™ Support for 1.8-, 2.5-, 3.3-V Devices Pin-by-Pin Selectable 3.3-V PCI Clamp

APEX 20KE I/O Blocks LVDS Input Block Output Programmable I/O Blocks
LVTTL LVCMOS GTL+ SSTL-3 Individual Power Bus, VREF

SignalTap™ Logic Analysis
APEX Communication Cable Quartus Comes up with board and chip; points are that BGAs are hard to get to, and that because of system integration, lots of previously accessible board nodes have disappeared into the chip. Click to bring up logic analysis; point is that few probe-able locations exist. Click to do “NO” logic analyzer, and bring in Signal Tap. Embedded Logic Analysis

SignalTap Plus Comes up with board. Point is that it’s sort of silly to use two logic analyzers, one for inside, one for outside, and can’t correlate them if you do. Click to bring up STP.

Embedded Product-Term Performance
tSU 2.9 ns P-TERM EPF10K100E-1 EPM7064S-5 tCO 4.7 ns tD 1.0 ns REG LUT tSU 0.7 ns tLAD 3.9 ns REG P-TERM APEX 20K-1 Speed Grade tCO 0.2 ns LUT Comes up with discrete implementation; click to get integrated implementation. Point here is that not only can you use the optimal logic implementation, but you also get the benefits of integration. 8.6 ns 4.8 ns

Quartus Development System
Altera’s Fourth-Generation Development Tool

Streamlined Design Flow
Workgroup Computing NativeLink™ Integration with EDA Tools Scripting Incremental Compilation Easy Floorplanning Linked to Design Intellectual Property

Additional Quartus Features
Verification Native HDL Simulator / Timing Analyzer SignalTap™: Hardware Verification at Speed Internet-Based Support Device Support Updates Patch Notification Quick Solutions Enhancement Requests Software Problem Reporting/Tracking

8-Port, 100-Mbit Ethernet Switch
32 Bit, 64 MHz 100 MBit MAC Interface In FIFO 16-to-32 Bit Interface Message Memory 96MB Out FIFO Write Memory Control SSTL-3 Port 1 PLL Read Memory Control SSTL-3 100 MBit MAC Interface In FIFO 16-to-32 Bit Interface Out FIFO Port 8 Memory Controller CAM System Memory GTL+ RISC µP FIFO Cache Memory LVTTL FIFO Usage Parameter Control S/M 32-Bit, 33-MHz PCI Diagnostic Interface 32 Bit, 33 MHz FLEX 10K MAX 7000 FLEX 6000

8-Port, 1-Gbit Ethernet Switch
64-Bit, 66-MHz PCI LVDS In FIFO 32-to-64 Bit Interface Out FIFO Port 1 1 GBit MAC Port 8 System Memory Cascade 64 Bit, 66 MHz 64 Bit, 100 MHz Write Control Message 96MB Read Usage Parameter Control S/M FIFO CAM RISC µP SSTL-3 GTL+ PLL Controller Cache Free Cell

APEX 20K & Quartus Summary
Revolutionary Architecture for Integration Quartus Speeds Complex Designs to Market 1-Gbit Ethernet Switch Illustrates Capabilities Basic Quartus desktop demo done before this; summary brings back the main points after the demo.

Altera MAX+PLUS II Development System
Notes:

MAX+PLUS II Design Flow
Design Entry Compilation Simulation Timing Analysis Notes: Device Programming

MAX+PLUS II Advantages
Fully Integrated, Single Interface Extremely Easy to Learn & Use Runs on Multiple Platforms Windows 3.1, Windows 95, Windows NT HP 9000 Series 700 IBM RISC System/6000 Workstations Sun SPARCstation Provides All Tools Needed for Complete PLD Project Cycle Extremely Fast Performance! Notes:

Altera Design Methodology
Hierarchical Design Management Top-down & Bottom-up Approaches Different Design Entry Can Be Used for Same Design Use Megafunctions/LPM Create Lower-Level Designs (Macrofunctions) for Different Functions Save & Check Macrofunctions Create Default Symbols or Include Files for Macrofunctions Call Out Macrofunctions in Top-Level Design Remember “20/20 Rule” for Future Changes or Additions Reserve 20% Logic Resources Reserve 20% I/O Pins Notes:

Altera Design Methodology
Schematic AHDL VHDL EDIF TOP-LEVEL DESIGN Schematic AHDL MACROFUNCTIONS EDIF AHDL VHDL Notes: MACROFUNCTIONS

Altera Design Methodology: Compilation
Select Target Device Set Applicable Logic Option Assignments Individual: Macrofunction-to-Macrofunction Basis Global: Top-level Design-wide Basis Compile Top-Level Design without Pin Assignments Functional: No Routing Timing: Place & Route Make Pin Assignments & Recompile, if Necessary Examine Report File (.rpt) Notes:

Altera Design Methodology: Verification
Simulation: Verifies Whether Design Functions Are Correct Functional: No Timing Information Timing: Check for Glitches, Static Hazards, etc. Timing Analysis: Verifies Whether Design Meets Performance Requirements Delay Matrix: Combinatorial Delays Setup/Hold Matrix: Setup/Hold Times Registered Performance: Maximum Frequency (fMAX) When Satisfied with How MAX+PLUS II Has Routed Design: Back-Annotate Project: Locks down Pin & Logic Option Assignments Notes:

Design Entry: MAX+PLUS II
Graphic (.GDF) AHDL (.TDF) VHDL (.VHD) EDIF (.EDF) .LMF Library Mapping File (.LMF) Notes: “Mix & Match” Different Methods of Design Entry

Graphic Design Entry Libraries prim mega_lpm mf User- Created Notes:

Graphic Design Entry Graphic Design Enter Symbol Connect Wire Label
Notes: Label Wires/Pins

Altera Hardware Description Language
High-Level, Hardware Behavior Description Language Uses Boolean Equations, Arithmetic Operators, Truth Tables, Conditional Statements, etc. Especially Well-Suited for Large or Complex State Machines All Described Behavior Is Implemented Concurrently Use Insert AHDL Template in the Text Editor Notes:

Hierarchical Design Management
A Top-Level Design Incorporates All Lower-Level Elements (Macrofunctions) of the Design into a Single File Use the Hierarchy Display to Examine & Navigate through the Design Hierarchy Hierarchy Display Also Shows Ancillary Files (e.g., Report, Simulation Input/Output, Message) Notes:

Hierarchical Design Management
Use Top-down or Bottom-up Design Methodology Build Your Design out of Lower-Level Building Blocks (Called Macrofunctions) Create Large, Complex Designs that Are Easy to Manage Use the Library of Parameterized Modules (LPM) to Create Architecture-Independent Designs Use Specialized Altera Macrofunctions to Meet Your Design Goals in Specific Target Markets (e.g., PCI, PCMCIA, ATM, DSP) Notes:

Design Compilation Flow
Functional SNF Extractor Timing SNF Extractor Functional Timing Simulation Simulation Different Implementation Correct? Correct? No Yes No Turn on Design Doctor Design Entry Yes Notes: Different Logic Options Timing Analysis Speed? Yes No Program

Design Compilation: Compiler
Detects & Locates Errors in Design Files Performs Logic Synthesis/Minimization Performs Design Rule Checking (Design Doctor) Fits Design Into Target Device Creates Simulation Files (.snf) Creates Device Utilization Report (.rpt) Creates Device Programming Files (e.g., .pof, .sof) Notes:

Design Compilation: Device Selection
Automatic Device Selection MAX+PLUS II Chooses the Smallest Possible Device from the Selected Device Family Select Auto as the Device in the Device Dialog Box (Assign Menu) MAX+PLUS II Can Partition Your Design Into Multiple Devices Select Auto Device in the Device Dialog Box (Assign Menu) Manual Device Selection Select Your Targeted Device in the Device Dialog Box (Assign Menu) Notes:

Design Compilation: Logic Synthesis
Logic Synthesis Options Influence How MAX+PLUS II Implements Your Design in the Device Architecture Logic Synthesis Options Set in Design Editors or Compiler Global Logic Assignments: Top-level Design-wide Basis. Let Max+Plus II make most of the decisions. Individual Logic Assignments: Macrofunction-to-Macrofunction Basis. User has more control in guiding Max+Plus II Set of Predetermined Choices for Synthesis Options Is Called a Logic Synthesis Style Use the Default Synthesis Styles or Create Your Own Consult On-Line Help for a Complete Description of Logic Synthesis Options & Styles Notes:

Design Compilation: Compiler Menus
Processing Menu Design Doctor: Checks Reliability of Design Functional SNF Extractor: Functional Compilation Timing SNF Extractor: Timing Compilation Linked SNF Extractor: Board Compilation Fitter Settings: Controls Fitting of Design Generate AHDL TDO File: Generates a Text Design Output File Notes:

Interfaces Menu EDIF Netlist Reader Settings: Sets Library Mapping File for an Imported EDIF File EDIF Netlist Writer: Generates an EDIF Output File Verilog Netlist Writer: Generates a Verilog Output File VHDL Netlist Reader Setting: Sets the User-Created VHDL Library VHDL Netlist Writer: Generates a VHDL Output File

Assign Menu Device: Selects Targeted Device Pin/Location/Chip: Makes Pin Assignments Timing Requirements: Makes Timing Assignments Clique: Keeps Block of Function Together Logic Options: Individual Logic Assignments Probe: Assigns a Unique Simulation Node Name for Buried Logic Global Project Device Options: Top-level Design-wide Programming or Configuration Options Global Project Timing Requirements: Top-level Design-wide Timing Assignments Global Project Logic Synthesis: Top-level Design-wide Logic Assignments Back-Annotate Project: Writes All Assignments to the assignment & configuration file (.acf) Notes:

Report File Lists Complete Details on Device Utilization
Project Summary Device Assignments Device-Specific Information Error Summary Resource Usage Interconnect Device Equations Notes:

Manipulating Assignments
Floorplan Editor Manipulating Assignments Graphical User Interface for Creating/Viewing Resource Assignments Pins Logic Cells Cliques Logic Options Drag-and-Drop Capability for Assigning Pins/Logic Cells Graphical View of Current Assignments as Well as Last Compilation External Chip View & In-Depth Logic Array Block View Notes:

Verification: Simulation
MAX+PLUS II Creates One of Two Types of Models of Design during Compilation Functional Model Logical Model Only, for Functional Simulation Generated Quickly, No Logic Synthesis or Fitting Timing Model Logical & Delay Model, for Timing Simulation Does Not Include Nodes that Are Synthesized Away during Logic Synthesis Simulation Channel Files (.scf) or Vector Files (.vec) Describe Simulation Stimulus Notes:

Which Nodes Can Be Simulated?
Timing Simulation Which Nodes Can Be Simulated? Nodes that Are Purely Combinatorial Logic Cannot Be Simulated Node May Be Transformed after Logic Synthesis Node May Be Removed after Logic Minimization “Hard” Nodes Can Be Simulated Inputs & Outputs of Devices Inputs & Outputs of Flipflops Inputs & Outputs of LCELL Buffers Inputs & Outputs of SOFT Buffers Not Removed by Logic Synthesis Notes:

Verification: Timing Analysis
Timing Analyzer Is a Static Timing Analyzer Adds Delays from Point to Point Three Forms of Timing Analysis (Analysis Menu) Delay Matrix: Calculates Combinatorial Delays Setup/Hold Matrix: Calculates Setup & Hold Times for Device Flipflops Registered Performance: Calculates Fastest Possible Clock Frequency Notes:

Using the Programmer & MPU
Programming a Device Using the Programmer & MPU Initiate Programming with the Programmer Module in MAX+PLUS II Programmer Defaults to Programming File for Specified Project Use Select Programming File (File Menu) to Select Another Programming File Perform Programming Operation with Buttons in Programmer Master Programming Unit (MPU) Stores Last Command (Use Start Button to Repeat) Notes:

Programming a Device BitBlaster ByteBlaster Serial Port: COM Port
PC or Workstation Program MAX 7000S & MAX 9000 Devices via the JTAG Interface Configure FLEX 8000 & FLEX 10K Devices via the Dedicated Configuration Pins Configure FLEX 10K Devices via the JTAG Interface ByteBlaster Parallel Port PC Only Faster/Cheaper Same Programming Capabilities as BitBlaster Notes:

MAX+PLUS II On-Line Help On-line help is a comprehensive set of information that is always available and accessible On-line help is available for all MAX+PLUS II menus, dialog boxes, and terminology Press Shift-F1 to get “Help Pointer” : Help on anything you see Check Procedures for “How to” information For any questions, try on-line help first

FLEX Design Guidelines
Never pre-assign pins Assign pins as late as possible and only after extensive simulation Reserve 20 % of pins and cells for changes Design synchronously and use dedicated global routing resources Pipeline for speed Limit use of carry and cascade cells Reduce high fan-out cells and pins

VHDL In this class, we will Learn basic VHDL constructs including:
VHDL basics and data types arithmetic operators and combinatorial circuits sequential circuits and state machines Examine VHDL synthesis for programmable logic Implement several VHDL designs in MAX+PLUS II VHDL Class

Agenda VHDL Basics and Lab Data Types and Lab
Arithmetic Operators and Lab Sequential Logic and Lab State Machines and Lab (MAX 7000 vs. FLEX 8000 synthesis) VHDL Class

What is VHDL? IEEE Industry Standard hardware description language
Description language for both simulation and synthesis Offshoot of Very High Speed Integrated Circuit (VHSIC) DOD program in early 1980s VHDL Class

VHDL Synthesis vs. other HDLs Synthesis
VHDL: Tell me how your circuit should behave and I will give you hardware that does the job ABEL, PALASM, AHDL: Tell me what hardware you want and I will give it to you VHDL Class

VHDL Synthesis vs. other HDLs Synthesis
Example of difference: VHDL: Give me a circuit whose output only changes when there is a low to high transition on a particular input. When that transition happens, make the output equal to the input until the next transition. Result: VHDL Synthesis gives you a positive edge triggered flip-flop Others: Give me a D-type flip-flop. Result: Synthesis gives you a D-type flip-flop. The sense of the clock depends on the synthesis tool. VHDL Class

VHDL Unit 1 VHDL Basics Entity Architecture Assignments VHDL Class

Entity Defines interface to outside world, i.e input and output pins
VHDL Entity Defines interface to outside world, i.e input and output pins Serves same function as a schematic symbol Inputs ENTITY example IS PORT ( a : in BIT; b : out BIT); END example; Outputs VHDL Class

VHDL Ports Defined in ENTITY Ports can be IN, OUT, INOUT VHDL Class

Architecture Defines implementation of design, i.e. logic equations
VHDL Architecture Defines implementation of design, i.e. logic equations Serves same function as a schematic ARCHITECTURE pld OF example IS BEGIN b <= a; END pld; Logic equations go between BEGIN and END VHDL Class

Example of Complete Design
VHDL Example of Complete Design ENTITY defines ports of design ENTITY example IS PORT ( a : in BIT; b : out BIT); END example; ARCHITECTURE pld OF example IS BEGIN b <= a; END pld; ENTITY and ARCHITECTURE make a pair linked by name ARCHITECTURE defines implementation VHDL Class

PROCESS Statement Groups sequential statements
VHDL PROCESS Statement Groups sequential statements WAIT Statement or Sensitivity list describes conditions for executing PROCESS Within the process, statements are executed sequentially VHDL Class

PROCESS Statement Using the Sensitivity List
VHDL PROCESS Statement Using the Sensitivity List PROCESS (sensitivity_list) BEGIN -- Sequential statement #1 -- Sequential statement #N END PROCESS; This process is executed after a change in any signal in the Sensitivity List VHDL Class

PROCESS Statement Using the WAIT statement: PROCESS BEGIN
VHDL Using the WAIT statement: PROCESS BEGIN WAIT condition -- Sequential statement #1 -- Sequential statement #N END PROCESS; This process is executed when the WAIT conditionis true! VHDL Class

PROCESS Statement Use LABELS for organization:
VHDL Use LABELS for organization: label: PROCESS (sensitivity_list) BEGIN -- Sequential statement #1 -- Sequential statement #2 END PROCESS label; The label identifies specific processes in a multi-process architecture VHDL Class

Signal Assignment Examples
VHDL Signal Assignment Examples Simple Conditional Selected q <= r or t; q <= ((r or t) and not(g xor h)); q <= ‘0’ WHEN clr = ‘0’ ELSE ‘1’ WHEN set = ‘1’ ELSE ‘X’; WITH sel SELECT q <= a WHEN ‘0’ b WHEN ‘1’ VHDL Class

? IF Statement Chooses action based on condition
VHDL IF Statement Chooses action based on condition Allows ELSIF, ELSE statements Must be inside PROCESS ? VHDL Class

IF Statement Example process is sensitive to all inputs used inside
VHDL IF Statement Example ENTITY if_ex IS PORT ( sel, a, b : in BIT; y : out BIT ); END if_ex; ARCHITECTURE if_ex OF if_ex IS BEGIN PROCESS (sel, a, b) IF sel = '1' THEN y <= a; ELSE y <= b; END IF; END PROCESS; process is sensitive to all inputs used inside process This circuit results in a multiplexer VHDL Class

LAB - Unit 1 Design 4:1 mux using and, or, not primitives
VHDL LAB - Unit 1 Design 4:1 mux using and, or, not primitives Design 4:1 mux using IF statements Once the design is entered, use the Save & Check feature (under the File-Projects menu) to check for syntax errors y a b c d sel_lsb sel_msb 1 2 3 Hint: Use the VHDL Templates VHDL Class

VHDL Unit 2 - Signals and Variables, Combinatorial Circuits, Multiple Processes A B 1 VHDL Class

VHDL Variables VHDL ENTITY var_ex IS PORT ( x, a, b :IN BIT;
z :OUT BIT); END var_ex; ARCHITECTURE example OF var_ex IS BEGIN PROCESS (x, a, b) VARIABLE tmp :BIT ; IF (x = '1') THEN tmp := a AND b; z <= tmp; ELSE z <= '1'; END IF; END PROCESS; END example; VARIABLE “tmp” holds intermediate value VHDL Class

VHDL Resulting Schematic VHDL Class

VHDL Signals ENTITY sig_ex IS PORT ( a, b, c :IN BIT; y :OUT BIT);
END sig_ex; ARCHITECTURE example OF sig_ex IS SIGNAL temp :BIT; BEGIN temp <= a XOR b; y <= temp AND c; END example; This SIGNAL is used to interconnect primitives VHDL Class

Resulting Schematic VHDL VHDL Class

VHDL Signals VHDL ENTITY mul IS PORT (a, b, c, selx, sely : IN BIT;
data_out : OUT BIT); END mul; ARCHITECTURE ex OF mul IS SIGNAL temp : BIT; BEGIN process_a: PROCESS (a, b, selx) IF (selx = ‘0’ THEN temp <= a; ELSE temp <= b; END IF; END PROCESS process_a; SIGNAL temp is used here to connect multiple processes process_b: PROCESS(temp, c, sely) BEGIN IF (sely = ‘0’ THEN data_out <= temp; ELSE data_out <= c; END IF; END PROCESS process_b; END ex; VHDL Class

Resulting Schematic VHDL Generated from process_a
Processes interconnected by SIGNAL temp Generated from process_b VHDL Class

Signals vs. Variables SIGNALS VARIABLES
VHDL Signals vs. Variables SIGNALS VARIABLES UTILITY: Represent Circuit Represent local storage Interconnect Global Scope (anywhere) Local Scope (inside process) Updated at end of PROCESS Updated Immediately (new value not available) (new value available) SCOPE: BEHAVIOR: VHDL Class

Examples of Differences
Signals vs. Variables VHDL Examples of Differences Correct Use (VARIABLE) ENTITY good IS PORT (i0, i1, i2, i3, a, b: IN BIT; q : OUT BIT); END good; ARCHITECTURE right OF good IS BEGIN PROCESS (i0, i1, i2, i3, a, b) VARIABLE val: INTEGER RANGE 0 TO 3; val := 0; IF (a = ‘1’ THEN val := val + 1; END IF; IF (b = ‘1’ THEN val := val + 2; END IF; CASE val IS WHEN 0 => q < = i0; WHEN 1 => q <= i1; WHEN 2 => q <= i2; WHEN 3 => q <= i3; END CASE END PROCESS; END right; New value is available VHDL Class

Examples of Differences
Signals vs. Variables VHDL Examples of Differences Incorrect Use (SIGNAL) ENTITY bad IS PORT (i0, i1, i2, i3, a, b : IN BIT; q : OUT BIT); END bad; ARCHITECTURE wrong OF bad IS SIGNAL val : INTEGER RANGE 0 TO 3; BEGIN PROCESS (i0, i1, i2, i3, a, b) val <= 0; IF (a = ‘1’ THEN val <= val + 1; END IF; IF (b = ‘1’ THEN val <= val + 2; END IF; CASE val IS WHEN 0 => q <= i0; WHEN 1 => q <= i1; WHEN 2 => q <= i2; WHEN 3 => q <= i3; END CASE; END PROCESS; END wrong; New value is not yet available VHDL Class

Non-Combinatorial Use of Variable
VHDL Non-Combinatorial Use of Variable ENTITY unsynth IS PORT ( sela, selb :IN BIT; dout :OUT BIT); END unsynth; ARCHITECTURE example OF unsynth IS BEGIN PROCESS (sela, selb) VARIABLE temp : BIT ; IF (sela = '1') THEN temp := '1'; ELSIF (selb = '1') THEN temp := '0'; END IF; dout <= temp; END PROCESS; END example; Internal variables should be assigned on every pass through a process! temp keeps old value if sela = ‘0’and selb = ‘0’ This defines a latch, not a combinatorial circuit. VHDL Class

VHDL LAB - Unit 2 Design an address decoder to select either the serial port at address 1010 or the parallel port at address Use an IF statement. Use the output of the address decoder to control the select line of the mux from LAB 1. Connect the address decoder and the mux using a SIGNAL. Once the design is entered, use Save & Check (under the File -> Projects menu) to check your syntax. process_a address decoder selector a b c d process_b sel serial_port data_out parallel_port 1 multiplexor VHDL Class

UNIT 3 Data Types Basic Data Types Enumerated Types Packages
VHDL UNIT 3 Data Types Basic Data Types Enumerated Types Packages Case Statement VHDL Class

VHDL Data Types VHDL is a strongly typed language, i.e disparate data types may not be assigned to each other All ports, signals, variables must be of some type Built-in types, or create your own VHDL Class

Data Types Simplest type is BIT BIT can have the values {‘0’,’1’}
VHDL Data Types Simplest type is BIT BIT can have the values {‘0’,’1’} What about tri-states? VHDL Class

STD_LOGIC Data Type Another common type
VHDL STD_LOGIC Data Type Another common type std_logic = {‘0’,’1’,’X’,’Z’} and 5 others not used for synthesis ‘X’ used for unknown ‘Z’ (not ‘z’) used for tristate VHDL Class

INTEGER Data Type Behaves like an integer in algebra
VHDL INTEGER Data Type Behaves like an integer in algebra Range is user-specified or compiler-default User can specify any subrange fred :INTEGER range 0 to 255; If range is not specified it will be the compiler-dependent default fred :INTEGER; VHDL Class

Bus Implementation VHDL offers vector types to implement buses
Common vector types are: bit_vector, std_logic_vector Examples: SIGNAL fred_bus :bit_vector (7 downto 0); SIGNAL barney_bus :std_logic_vector (3 downto 0); SIGNAL betty_bus :std_logic_vector (0 to 3); VHDL Class

Bus Assignment Reference entire bus fred_bus <= “11111111”;
VHDL Bus Assignment Reference entire bus fred_bus <= “ ”; Reference one bit of a bus bus (3) <= ‘1’; Reference a slice of the bus bus (3 downto 2) <= “11”; VHDL Class

VHDL Enumerated Types Enumerated types are the most common user-created types Enumerated types are used primarily for state machines Example: TYPE country IS (Germany, USA, Italy, Japan); TYPE state_type IS (state_a, state_b, state_c); VHDL Class

VHDL PACKAGEs What are packages?
Packages are a collection of elements including data type descriptions They can be shared by multiple designs/designers You can use standard packages which are included with VHDL or create your own VHDL Class

VHDL Packages Commonly Used Packages:
IEEE.std_logic_arith - arithmetic functions IEEE.std_logic_signed - signed arithmetic functions IEEE.std_logic_unsigned - unsigned arithmetic functions IEEE.std_logic_ std_logic and related functions ALTERA.maxplus2 - component declarations for all Altera macrofunctions VHDL Class

How to use a package LIBRARY <library name>;
VHDL How to use a package LIBRARY <library name>; USE <library name>.<package name>.all; In MAX+PLUS II, <library name> is a subdirectory of c:\maxplus2\max2vhdl Library name is IEEE, ALTERA Can specify a particular element instead of all individual items or .all Package Library VHDL Class

Packages in MAX+PLUS II
VHDL Packages in MAX+PLUS II Example: LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_unsigned.all; LIBRARY altera; USE altera.maxplus2.all; VHDL Class

VHDL User-defined Package User-defined packages must be in the same directory as the design To use your new packages: LIBRARY WORK; USE WORK.<package name>.all; VHDL Class

CASE Statements Used to generate combinatorial logic
VHDL Used to generate combinatorial logic Must specify all possibilities with a “WHEN OTHERS” statement CASE val IS WHEN “00” => q <= i0; WHEN “01” => q <= i1; WHEN OTHERS => q <= ‘X’; END CASE; val and i0, i1 will be input to combinatorial logic q will be output to combinatorial logic VHDL Class

VHDL LAB - Unit 3 Design an 8-bit wide 4:1 bus mux with tri-state output enable control Implement the mux in one process and the tri-state in a second process Use STD_LOGIC_VECTOR type Use a CASE statement process_a data(31 downto 24) data(23 downto 16) data(15 downto 8) data(7 downto 0) Multiplexer data_mux(7 downto 0) sel (1 downto 0) data_out(7 downto 0) Tri-State output_enable_control process_b VHDL Class

Unit 4 - Arithmetic Operators,Operator Overloading
VHDL Unit 4 - Arithmetic Operators,Operator Overloading - @#*! + multiply a = b + c * <= greater than > + subtract EQUALS std_logic <----> INTEGER VHDL Class

Arithmetic Operators + , - add/subtract
VHDL Arithmetic Operators + , - add/subtract * multiply (powers of 2 only in MAX) <, > greater than, less than <=, >= greater or equal, lesser or equal =, /= equal, not equal to VHDL Class

Operator Overloading: Why and What?!?
VHDL Operator Overloading: Why and What?!? VHDL defines arithmetic and boolean functions only for built-in data types: Arithmetic Operators such as +, -, <, >, <=, >= work for the INTEGER type Boolean Operators such as AND, OR, NOT work only with BIT type How do you use arithmetic and boolean functions with other data types? Operator Overloading VHDL Class

Operator Overloading: How is it implemented?
VHDL Operator Overloading: How is it implemented? LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; ENTITY overload IS PORT ( a : IN std_logic_vector (3 downto 0); b : IN std_logic_vector (3 downto 0); sum : OUT std_logic_vector (4 downto 0)); END overload; ARCHITECTURE example OF overload IS BEGIN adder_body:PROCESS (a, b) sum <= a + b; END PROCESS adder_body; END example; Include these statements at the beginning of each design file. This allows us to perform arithmetic on non-built-in data types. VHDL Class

LAB - Unit 4 Create a 24-bit adder using std_logic_vector
VHDL LAB - Unit 4 Create a 24-bit adder using std_logic_vector Ignore carry-in and carry-out Add an output enable control output_enable_control process_b Tri-State sum(23 downto 0) process_a Adder addend_a(23 downto 0) addend_b(23 downto 0) sum_out (23 downto 0) VHDL Class

VHDL Unit 5 Register Inference Latches Flip-Flops VHDL Class

Synthesis Rules Not all processes are synthesizable
VHDL Synthesis Rules Not all processes are synthesizable To be synthesizable, one of these must be true: Combinatorial circuit: Sensitive to all input signals Registered circuit: Sensitive to a single clock edge and optional asynchronous clear/preset/load signals VHDL Class

Latch Inference VHDL code describes behavior of transparent latch
PROCESS is sensitive to both Data and Gate Notice similarity to mux PROCESS (Data, Gate) BEGIN IF Gate = ??THEN Q <= Data; END IF; END PROCESS; VHDL Class

Flip-Flop Inference VHDL code describes behavior of D-Type Flip-Flop
This implementation uses PROCESS sensitivity list Clock is only signal in sensitivity list PROCESS (clk) BEGIN IF clk = 1 THEN q <= d; END IF; END PROCESS; VHDL Class

Flip-Flop Inference Implementation using PROCESS with WAIT statement
VHDL Flip-Flop Inference Implementation using PROCESS with WAIT statement PROCESS BEGIN WAIT UNTIL clk = ‘1’ q <= d; END PROCESS; VHDL Class

Flip-Flop Inference with Asynchronous Clear
VHDL Flip-Flop Inference with Asynchronous Clear Both Clock and Clear are in sensitivity list Why do we need the clk’EVENT? PROCESS (clock, clear) BEGIN IF clear = ‘0’ THEN q <= ‘0’; ELSIF clock’EVENT and clock = ‘1’ THEN q <= d; END IF; END PROCESS; VHDL Class

Gated Clocks Clock must be gated outside of PROCESS description
VHDL Gated Clocks Clock must be gated outside of PROCESS description Must define new clock as a signal ARCHITECTURE ex OF gatedclock IS SIGNAL gclock : std_logic; BEGIN gclock <= clka AND clkb; PROCESS (gclock) IF gclock = '1' THEN q <= d; END IF; END PROCESS; END ex; Clock is gated here Then used here VHDL Class

How Many Registers? VHDL ENTITY reg1 IS PORT ( d : in BIT;
clk : in BIT; q : out BIT); END reg1; ARCHITECTURE reg1 OF reg1 IS SIGNAL a, b : BIT; BEGIN PROCESS (clk) IF clk = ‘1’ THEN a <= d; b <= a; q <= b; END IF; END PROCESS; VHDL Class

VHDL How Many Registers? VHDL Class

How Many Registers? Signal assignment moved VHDL ENTITY reg1 IS
PORT ( d : in BIT; clk : in BIT; q : out BIT); END reg1; ARCHITECTURE reg1 OF reg1 IS SIGNAL a, b : BIT; BEGIN PROCESS (clk) IF clk = ‘1’ THEN a <= d; b <= a; END IF; END PROCESS; q <= b; Signal assignment moved VHDL Class

How Many Registers? b to q assignment is no longer edge sensitive VHDL
VHDL Class

How Many Registers? Order of signals changed VHDL ENTITY reg1 IS
PORT ( d : in BIT; clk : in BIT; q : out BIT); END reg1; ARCHITECTURE reg1 OF reg1 IS SIGNAL a, b : BIT; BEGIN PROCESS (clk) IF clk = ‘1’ THEN b <= a; a <= d; END IF; END PROCESS; q <= b; Order of signals changed VHDL Class

How Many Registers? Order of signal assignments makes no difference!
VHDL How Many Registers? Order of signal assignments makes no difference! VHDL Class

How Many Registers? Signals changed to variables VHDL ENTITY reg1 IS
PORT ( d : in BIT; clk : in BIT; q : out BIT); END reg1; ARCHITECTURE reg1 OF reg1 IS BEGIN PROCESS (clk) VARIABLE a, b : BIT; IF clk = ‘1’ THEN a := d; b := a; q <= b; END IF; END PROCESS; Signals changed to variables VHDL Class

How Many Registers? Remember:
VHDL How Many Registers? Remember: Variable assignments are updated immediately. Signal assignments are updated on clock edge. VHDL Class

Lab - Unit 5 Design a DFF with synchronous reset
VHDL Lab - Unit 5 Design a DFF with synchronous reset Modify it by adding an asynchronous reset Modify adder design from previous Lab so that it is an accumulator Compile for FLEX 8000 with Style = Fast Use the Timing Analyzer to determine the Registered Performance adder sum_out (23 downto 0) addend_a(23 downto 0) Register result (23 downto 0) addend_b(23 downto 0) sum(23 downto 0) VHDL Class

Unit 6 Module Generation for Arithmetic Operators
VHDL Unit 6 Module Generation for Arithmetic Operators MAX7000 vs FLEX8000 synthesis Counters Hierarchical Designs Component Instantiation Macrofunction and primitive libraries VHDL Class

VHDL Module Generation The VHDL synthesizer generates modules for each arithmetic function entered in a design These modules are then converted to structures that are optimized for the target device Example: Adder structure for FLEX is ripple-carry Adder structure for MAX is carry-look ahead Family-specific module generation is automatic VHDL Class

Module Generation a <= b + c; + FLEX VHDL design file Module MAX
Gate-level Structures VHDL Class

Counters Counters are just accumulators that always add a ‘1’ VHDL
ARCHITECTURE example OF counter IS BEGIN PROCESS (clk) VARIABLE count : std_logic_vector (7 downto 0); IF clk = '1' THEN count := count + 1; END IF; q <= count; END PROCESS; END example; VHDL Class

Counters Add enable, load and up/down features with IF statements VHDL
ARCHITECTURE example OF counter IS BEGIN PROCESS (clk) VARIABLE count : std_logic_vector (7 downto 0); IF clk = '1' THEN IF ldn = '0' THEN count := load; ELSE count := count + 1; END IF; q <= count; END PROCESS; END example; VHDL Class

VHDL Multiple Design Files VHDL allows hierarchical design through component instantiation top.vhd entity-architecture “top” component “mid_a” component “mid_b” mid_b.vhd entity-architecture “mid_b” component “bottom_a” component “bottom_b” mid_a.vhd entity-architecture “mid_a” component “bottom_a” bottom_b.vhd entity-architecture “bottom_b” bottom_a.vhd entity-architecture “bottom_a” VHDL Class

Component Instantiation
VHDL Component Instantiation The Upper-level design must have a COMPONENT declaration for a lower-level design before instantiating it COMPONENT declared here ARCHITECTURE upper OF top IS SIGNAL count : std_logic; COMPONENT simpcnt PORT ( clk : IN bit; q : OUT std_logic); END COMPONENT; BEGIN u1 : simpcnt PORT MAP (clk => sysclk, q => count); COMPONENT used here VHDL Class

Macrofunction and Primitive Libraries
VHDL Macrofunction and Primitive Libraries Silicon vendors often provide libraries of macrofunctions and primitives These can be used to control the physical implementation of the design within the programmable logic device Vendor specific libraries will improve the performance and efficiency of the design Altera provides a complete library of LPM compliant macrofunctions, plus other primitives VHDL Class

Macrofunction Instantiation
VHDL Macrofunction Instantiation All of the Altera macrofunctions and primitive components are declared in the VHDL package: ALTERA.maxplus2.all Within this package, all component ports are of type STD_LOGIC or STD_LOGIC_VECTOR VHDL Class

Macrofunction Instantiation
VHDL Macrofunction Instantiation Use the ALTERA library for macrofunction instantiation so that component declarations are not needed. LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; LIBRARY ALTERA; USE ALTERA.maxplus2.ALL; ENTITY macro IS PORT( clock, enable : IN std_logic; Qa, Qb, Qc, Qd : OUT std_logic); END macro; ARCHITECTURE example OF macro IS BEGIN u1 : gray4 PORT MAP (clk => clock, ena => enable, qa => Qa, qb => Qb, qc => Qc, qd => Qd); END example; VHDL Class

LAB - Unit 6 Create a simple 8-bit counter
VHDL LAB - Unit 6 Create a simple 8-bit counter Compile for 7k and 8k and Analyze Registered Performance Add load, enable, synch/asynch clear, up/down Create a top-level design and instantiate your counter Top_levl.vhd count8 q load enable up/down clear count8 q load enable up/down clear VHDL Class

Unit 7 - State Machines VHDL idle a = ‘0’ a = ‘0’ start check run
CASE current_state IS WHEN State_A => flag <= '0'; IF data = '0' THEN next_state <= State_A; ELSE next_state <= State_B; END IF; WHEN State_B => IF data = '0' THEN next_state <= State_B; ELSE next_state <= State_C; WHEN State_C => IF data = '0' THEN next_state <= State_C; ELSE next_state <= State_D; WHEN State_D => flag <= '1'; IF data = '0' THEN next_state <= State_D; ELSE next_state <= State_A; END CASE; idle a = ‘0’ a = ‘0’ start check run VHDL Class

State Machine Structure
VHDL Use enumerated types to create state values ARCHITECTURE example OF statemac IS TYPE state_type IS (state_a, state_b, state_c, state_d); SIGNAL state : state_type; BEGIN State names are defined as a type. Machine will start in first state listed. VHDL Class

State Machine Structure
VHDL Use two processes to describe machine operation: 1. to determine state 2. to determine output flags fsm: PROCESS BEGIN WAIT UNTIL clock = ‘1’; CASE state IS WHEN state_a => IF data = ‘0’ THEN state <= state_a; ELSE state <= state_b; END IF; WHEN state_b => state <= state_c; END CASE; END PROCESS fsm; output: PROCESS (state) BEGIN CASE state IS WHEN state_a => flag <= ‘1’; WHEN state_c => WHEN OTHERS => flag <= ‘0’; END CASE; END PROCESS output; VHDL Class

State Machine Encoding
VHDL State Machine Encoding Product-term based (MAX 7000 and MAX 9000) : Default Encoding is Binary Encoding Look-up table based (FLEX 8000 and FLEX 10K): Default Encoding is One-Hot Encoding Users may overwrite the MAX+PLUS II encoding defaults by using an ATTRIBUTE statement VHDL Class

Binary Encoding Example
VHDL Encoding specified in ATTRIBUTE statement (values match state names left to right) ENTITY statemac IS PORT (data, clk : IN BIT; flag : OUT BIT); END statemac; ARCHITECTURE ex OF statemac IS TYPE state_type IS (state_a, state_b, state_c, state_d); ATTRIBUTE encode : STRING; ATTRIBUTE encode OF state_type : TYPE IS “ ”; SIGNAL current_state, next_state : state_type; BEGIN VHDL Class

LAB - Unit 7 VHDL Design a state machine that will detect a pattern of “011011” from a serial data stream. When this pattern is detected set detect_flag output for one cycle. Check the completed design using Save & Check under the file -> project menu Serial_data Detect_Flag VHDL State Machine Clock VHDL Class

Summary Investigated MAX+PLUS II VHDL Design Entry
Learned VHDL concepts combinatorial and sequential circuits data types and packages arithmetic operators Hands on Labs, where we built : muxes state machines decoders adders counters VHDL Class

Altera’s Commitment to You
VHDL Complete Technical Support Any questions? If you can’t find it in Help, consult our Applications department Field Applications Engineers: Contact your local office Factory Applications Engineers: Call EPLD Factory Applications Engineers: For the most current literature: Call ALTERA Applications Bulletin Board System: Call (408) Applications FTP site: Contact ftp.altera.com World Wide Web Site: Contact Hands-on Training Classes Seminars VHDL Class

Altera Training Course

Similar presentations

Presentation on theme: "Altera Training Course"— Presentation transcript:

Similar presentations

About project

Feedback

Log in

Auth with social network:

Altera Training Course

Similar presentations

Presentation on theme: "Altera Training Course"— Presentation transcript:

Similar presentations

About project

Feedback