1. Arria 10 External Memory Interface Board Guidelines
Quartus Prime Software v17.0

2. Introduction This slide deck covers the following topics:
Layout recommendations
Simulation Guidance
For more details regarding board design, refer to the appropriate Board Design Guidelines section in the External Memory Interface Handbook
DDR2, DDR3, and DDR4 SDRAM Board Design Guidelines
LPDDR2 and LPDDR3 SDRAM Board Design Guidelines
RLDRAM II and RLDRAM3 Board Design Guidelines
QDR II and QDR-IV SRAM Board Design Guidelines
*EMIF = External Memory Interface

3. Software Requirements
Quartus Prime Software v17.0

4. Disclaimer Length matching guidelines are recommendations
Should not be considered as hard guidelines
Board-level simulation must be performed to ensure there are no signal integrity or ISI/Crosstalk related issues
To ensure there are no timing violations
Enter accurate information in the Board tab of the EMIF IP GUI
For more details on simulation guidance refer to this wiki page

5. General Board Guidelines
The following slides cover board guidelines for DDR3, DDR4, RLDRAM3, QDRIV and LPDDR3 protocols
Trace impedance plays an important role in signal integrity
Board-level simulation must be performed to determine best characteristic impedance for PCB
For example: It is possible that for a multi-rank system 40Ω would yield better results than the traditional 50Ω characteristic impedance
To minimize PCB layer propagation variance, it is recommended to route signals from the same net group on the same layer
Use 45° angles (not 90° corners)
Disallow critical signals across split planes
Route over appropriate VCC and GND planes
Keep signal routing layers close to GND and power planes
Avoid routing memory signals to memory clocks closer than inches (0.635mm)

6. Layout Recommendation Summary
DDR3
DDR4
RLDRAM3
QDRIV
LPDDR3
Max Length (Discrete Devices)
7 inches for Addr/Cmd 5 inches for DQS/DQ/DM
600ps
Max Length (DIMM)
4.5 inches
N/A
Data Group Skew
Match DQ and DM within 10ps of DQS
Match DQ within 10ps of DK/QK
Match DQA/DQB within 10ps of DK/QK
Match DQ and DM within 5ps of DQS
Address/Command VS Clock Skew
Match Addr/Cmd signals within 20ps of Mem CK
Match Addr/Cmd signals within 10ps of Mem CK
Package Skew Matching
Yes
Data Strobe to Mem CK Matching
Refer to slide 10
Match DK and CK within 50ps
Match DQS and Mem CK within 50ps
Clock Matching
2ps within a clock pair 5ps between clock pairs
Spacing Guideline (Data/Data Strobe/Addr/Cmd)
3H spacing between any Data, Data Strobe, and Addr/Cmd traces1
Spacing Guideline (Mem CK)
5H spacing between Mem CK and any other signal1
1 Where H is the distance to the nearest return path

7. Data to Data Strobe Delay Matching
Match the (package + board) trace delays up to 20ps of skew for signals within a data group
Data, Data strobe, Data mask
For more information on how to perform package de skew, refer to the Package Deskew section in the External Memory Interface Handbook
Package Trace Length
Board Trace Length
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7 DM
DQS
DQS_N
Inside FPGA
On PCB

8. Address/Command/Control Skew
The following slides go into detail explaining board guidelines in reference to Address/Command/Control signals
All Addr/Cmd/Control signals should match up to ±20ps compared to the Mem CK trace
For example: If Mem CK trace delay is 500ps
Allowed range for Addr/Cmd/Control signals is 480ps to 520ps
For discrete components:
Make sure ±20ps recommendation is met for each component in fly-by chain
For DIMMs:
Make sure the ±20ps recommendation is met at each DIMM connector
Applicable to single and multiple DIMM configurations

9. Address/Command/Control Skew
x(n) represents the clock trace length between FPGA and DRAM components, where n = 1, 2, 3…
y(n) represents Addr/Cmd trace length between FPGA and DRAM components, where n = 1, 2, 3…
Route all Addr/Cmd signals to match clock signals within ±20ps or approximately ±3.175mm to each discrete memory component
x = y ± 20ps
x + x1 = y + y1 ± 20ps
x + x1 + x2 = y + y1 + y2 ± 20ps
x + x1 + x2 + x3 = y + y1 + y2 + y3 ± 20ps
FPGA
DDR3 SDRAM Component
VTT x3 y3 y2 y1 y x2 x1 x
Clock
Addr/Cmd
Propagation Delay < 0.69 tCK

10. Data Strobe to Mem CK Matching
Timing between data strobe and clock signals on each device calibrate dynamically to meet tDQSS
To make sure skew is not too large for leveling circuit’s capability:
Propagation delay of clock signal must not be shorter than propagation delay of DQS signal at every device
CKi – DQSi > 0
0 < i < number of components – 1
Total skew of CLK and DQS signal between groups is less than one clock cycle
Max(CKi + DQSi) – min(CKi + DQSi) < 1 × tCK
For DIMM topology:
Delay and skew must take into consideration values of actual DIMM
DDR3 Component
VTT
FPGA …
DQ Group 0
DQ Group 1
DQ Group i CK
DQS
CK0
CK1
CKi
Cki = Clock signal propagation delay to device i
DQSi = DQ/DQS signals propagation delay to group i

11. Spacing Guidelines Avoid routing two signal layers next to each other
Always make sure signals related to memory interfaces are routed between appropriate GND or power layers
DQ/DQS/DM traces:
Maintain at least 3H spacing between edges (air-gap) of traces
Address/Command/Control traces:
Mem CK traces:
Maintain at least 5H spacing between two clock pairs or a clock pair and any other memory interface trace
GND or Power 3H H 5H
PCB cross-section
H is the vertical distance to the closest return path for a particular trace

12. Channel Simulation Guidance
For more details regarding simulation guidance, refer to this wiki page
Run Quartus Prime compilation with generated EMIF IP
Generate EMIF IP that accurately represents memory subsystem (Board tab of IP GUI)
Calculate setup and hold derating
Calculate board skews
Calculate channel signal integrity
Preliminary Layout
Tweak layout to improve:
Trace length mismatch
ISI
Crosstalk
Done
Are there any non-core timing violations in Report DDR? No
Yes