1. How objects are located in memory
Addressing Modes
How objects are located in memory
Copyright © Curt Hill

2. What is an addressing mode?
It is how a computer forms an address to fetch an item from memory
Sounds simple but usually is not
Usually involves some sort of computation
This presentation will not include any discussion of virtual memory which complicates things
Copyright © Curt Hill

3. Absolute Address The obvious way is to include the absolute address
AKA Direct addressing
The 8080 had an absolute address
Each instruction that accessed memory had one 16 bit address in it
In general absolute addresses are too large and too hard to relocate
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4. Size Issues The 8080 had a 64K address space and a 16 bit address
Modern computers have larger absolute addresses, typically bits
With 32 bit address a single address instruction would need 4 bytes for address and at least one for operation code and another for other operands
A two address machine with 24 bit addresses requires 48 bits for the two addresses and some more for the opcode etc.
There are few machines that have all instructions that are larger than 48 bits
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5. Relocation Abosolute addresses also have a relocation problem
A program with absolute addresses may only sit in one designated location in memory
It then takes a program to relocate it
The 8080 was small enough we did not have two programs running at once so it was not much of a problem
Such relocation is done with a loader, but we want to make it as easy as possible
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6. What other options are there?
Register addressing
Register indirect
Base and offset
Segment addressing
Stack addressing
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7. Register addressing We generate the address of a register
The contents of that register is the actual address
Registers are usually addressed with short address fields - typically 2-8 bits, whereas the address in the register may be 32 bit or longer
Very rapid access to the register
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8. Register indirect Specify the address of the register
Use the contents of the register as a memory address
Use the contents stored at the memory location as an address
Thus the register is used to find a pointer, which directs us to real operand
Usually in one step
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9. Base and offset addressing
AKA Displacement addressing
AKA Indexed addressing
In this scheme we have an Address register or General Purpose register pointing to a position in memory
Addresses are then coded as register plus offset
The number of bits in the instruction is less than that needed for an absolute address
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10. Eg IBM 360 16 register require a 4 bit address A 12 bit offset
16 bits for an address rather than 32 bits normally needed
An RX instruction needs 4 bytes
An SS instruction 6 bytes
The disadvantage is the maximum offset that can be used is 4096, past the register position
This makes for certain problems
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11. Limitations
Procedures or Functions need to have one base register for each 4K of code and data that they need
A subroutine that is 4K long is actually ideal, you do not want them larger than that
However, 4K is not much data, especially if dealing with arrays
However, an array will usually use an index register
So only the beginning of the array needs to within the 4K
Hence you put non-array data first and then the array
You may only access the end part of the array with a non-constant subscript
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12. Segment Addressing A variation of base and offset
Segment register is not needed in instruction
It is inferred
All that is given is an offset past the segment register
Generally there are fewer segment registers than base registers
The proper register must be inferred
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13. Intel 8086 and up
We have:
Code segment register
Data segment register
Stack segment register
This logically partitions memory into three chunks
Code is presumed to be a 16 bit offset past the code register
Data a 16 bit offset past the data register
The 8080 used absolute addressing in a 64K address space, when we move up it becomes an offset past the address register
Thus a segment is 64K long
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14. Relative Addressing Use the Program Counter as a base register
Typically only used for a jump, branch or call
This is often implied as well
The operation code usually determines the addressing mode
Copyright © Curt Hill

15. Indexing complicates this
AKA Based-indexed addressing
Arrays are the only data structuring that has direct hardware provision
We generate an address that is based on an array index
This array index cannot be known until run-time
We must first make a detour through arrays
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16. Arrays In C I can do the following: ATYPE x[10];
I want 10 copies of x which is of type ATYPE
Later I can say: = x[sub]
Sub is the subscript or index
What does the addressing of this thing look like?
The effective address must be computed in the following way: addr(x[0]) + sub * sizeof(ATYPE)
Copyright © Curt Hill

17. Example Suppose double d[100]; A reference to d[i] is found
Compute address using: addr(d[0]) + i * sizeof(double)
If d[0] is at location 250 and i contains 8 and double are 8 long: * 8 = 314
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18. Pascal
In Pascal the lower bound does not have to be either zero or one x: ARRAY[lower..upper] of item;
Now the effective address must be computed in the following way: addr(x[lower]) + (sub-lower) * length(item)
Can it get worse?
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19. Slack Bytes
Slack bytes are introduced when a items in an array should each have some type of boundary alignment in memory but the item is the wrong size
If the item is not a power of two size it may be time to introduce slack bytes to do the boundary alignment
For example:
Item is 5 bytes long and we must align it on a boundary divisible by 8
Add 3 slack bytes after each item
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20. Pascal with slack bytes
Slack = 8 – length(item) modulo 8
The effective address must be computed in the following way: addr(x[lower]) + (sub-lower) * length(item+slack)
The first expression addr(x[lower]) is handled by the normal addressing scheme:
Base + offset, Segment or whatever
That leaves the * length(item+slack) be handled in another way
Usually loaded into an index register
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21. System 360 Example
On 360 many addresses can be two registers and one offset
The first register and offset is the typical usage
The second register is an index register
The effective address is the sum of the two registers and offset
The index register typically is a subscript multiplied times length of the array item
On the 360 if the index register was zero, then a zero was produced
Regardless of the contents of register 0
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22. Relocation reconsidered
How is a base or segment register set?
It is usually set by user mode operations
On the 360, all 16 of the General Purpose register may be set by user command
However it is not pretty
On x86 they may also be set by user instructions
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23. System 360 The 360 has a Branch And Link instruction
It has two forms BAL and BALR
This is the subroutine call in 360
It loads the next address into a register and then branches to:
BAL a memory address derived by base + offset
BALR the contents of another register
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24. Subroutine Call Sequence L 15,SUBRADDR BALR 14,15 A 12,Stuff
The first L puts the address of the subroutine in register 15
The BALR loads the address of the third instruction into 14 and branches to address in 15
The A is executed when subroutine returns
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25. Finding current address
Normally load your subroutine address in one register and the BALR would save current address and branch to new
If the branch register was 0, the branch was suppressed and it became load the next address into the return register
This can then be used as a base register
It may also be the calling routine (OS or user routine) would load the segment register or base register
Copyright © Curt Hill

26. Microsoft OS
On Intel devices a program starts with the code segment register and stack segment register already loaded
The assembly language program must load its own data segment register
A far call is when the program loads a new code segment register as part of a call
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27. Indirect addressing
The address that you generate is used to access a word in memory that itself contains the real address
Eg I produce an address of 20
The word at address 20 is accessed and it then contains an address of 144, which is the effective address in question
Indirect addressing always requires an extra memory fetch
Useful programming tool
This can also be used in conjuction with other addressing modes
Eg. use base + offset to get at the word in memory
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28. PDP 11 Some machines use a more complicated indirect scheme
They reserve one bit for indirection
If that bit is one then the item is considered an address and not data
In such a scheme we can go through several pointers or addresses before arriving at the data we want
The PDP11 has one and two level indirection
Indexing may be applied before or after the indirection
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29. Stack addressing
Machines newer than the PDP 11 usually have a stack register
There are effectively several operations
Push a new item onto the stack
Pop an item off of the stack
Copy the top of the stack without moving the stack
Call and return often automatically use stack
The first two of those automatically imply and increment/decrement of the stack pointer
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30. High Level Languages Stack is a handy construct
A local variable of a procedure is an offset from the stack
Global variables are an indirection off of a stack variable
The return address and return value are also locations on the stack
In the call we push on values of value parameters, addresses of variable parameters, return addresses and space for a function result
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31. Stack Pointers
PDP 11 have pre and post incrementation or decrementation of variables to facilitate maintenance of a stack
Hence any register could be a stack pointer
Burroughs B5000 mainframes could use a stack register plus offset to address the items of the stack
They also had an item called a cactus stack, where an item in a stack was a stack pointer to another stack
Most modern machines have a stack pointer as a register
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32. Summary RISC machines tend to have just a few
CISC machines tend to have many
These addressing modes can be used in numerous combinations
Look at a few examples
Example notation
(Reg) = Contents of register as address
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33. System 360 Although a CISC, it is very early
RR instructions have both operands in registers
BALR and BR have a branch destination in a register
RX instructions have one register and one memory location
Memory is addressed by base and index register and displacement
SI have an immediate byte
RS has one memory and SS two references
Base and displacements
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34. Pentium addressing modes
Immediate: data is part of instruction
Register: operand in register
Displacement: (Segment register) + offset
Base: (Segment register) + (base register)
Base with displacement: (Segment) + (Base) + offset
Scaled index: (Segment) + (Index) * Scale + offset
Base with Index and Displacement: (Segment) + (Index) + (Base) + offset
Base with Scaled Index and Displacement: (Segment) + (Index)*Scale + (Base) + offset
Relative: (Program Counter) + offset
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35. PowerPC Addressing Modes
For loads and stores
Indirect = (Base register) + Offset
Indirect Indexed = (Base register) + (Index register)
For branches
Absolute = the address
Relative = (Program counter) + Offset
Indirect = (Link or Count register)
Integer arithmetic
Register = General Purpose Reg
Immediate = In instruction
Floating point arithmetic
Register = Floating Point Reg
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