1. Matteo VIGNETTI *a (WP2 ESR PhD Student)
*Supported by the European Union’s Seventh Framework Programme for research, technological development and demonstration under grant agreement n° 317446 (INFIERI)
Update on the development of Novel Pixel Sensors based on 3D CMOS technology
Matteo VIGNETTI *a
(WP2 ESR PhD Student)
F. Calmon a(Supervisor), R. Cellier b, P. Pittet b, L. Quiquerez b, A. Savoy-Navarro c
a Electronic Devices Department, INL, Lyon (France)
b Conception de Systèmes Hétérogènes, INL, Lyon (France)
c Laboratoire d’AstroParticule et Cosmologie, Université Paris-Diderot, Paris (France)

2. A novel 3D pixelated detector for vertex tracking
A 3D pixel: the core of the detector p p
Two coincident avalanche pulses are produced when a charged particle hits the pixel
Two vertically aligned avalanche diodes operated in Geiger-mode
The coincidence is verified thanks to dedicated electronics e h p p
TOP = 1
OUT = 1
BOTTOM = 1 e h p p p

3. Coincidence-based Avalanche Detector concept
In particles tracking systems, the ideal detector should provide a large signal while featuring a thin sensitive volume
Geiger-mode avalanche diodes:
A very thin sensitive region (~𝜇𝑚) is enough to produce a strong electrical signal thanks to a self-sustained multiplication process by impact ionization
suffer of false counts (dark count rate), due to dark thermal and field-assisted e/h pair generation and background photons
Coincidence detection:
Dramatically reduces the amount of false counts as the DCR of the two diodes are uncorrelated
false counts might occur during the time-window where the coincidence is checked
(Typical CMOS tech)
X 𝟏𝟎 𝟒 improvement
𝐹𝐶𝑅=2𝐷𝐶 𝑅′ 2 𝐴 2 ∆𝑡
FCR:Fake coincidence rate
𝐷𝐶𝑅′: dark count rate of the diode per unit surface
A: diode active area

4. Outline
Design of the avalanche diode
Design of the pixel electronics
3D integration
Tape-out
Preliminary tests
Design of a testing board

5. Outline
Design of the avalanche diode
Design of the pixel electronics
3D integration
Tape-out
Preliminary tests
Design of a testing board

6. Design of the avalanche diode
Premature edge breakdown (PEB) prevention
Sensitive surface
Cathode
Anode
PEB!
OK!
Dark Count Rate (DCR) minimization
DCR depends on the e – h pair generation rate in the diode space charge region (in the dark)
Carrier generation rate depends on:
CMOS technology (i.e. defects density)
avalanche diode architecture (e.g. junction enhancing tunneling-based carrier generation)

7. Design of the avalanche diode
TCAD simulations of several avalanche diode architectures found in literature:
AMS HV-CMOS 0,35µm technology
“low doped p-well guard-ring”
Substrate
Choice of the architecture based on:
Affordable CMOS technology in terms of tape-out costs
Best performing architecture among those compatible with the chosen CMOS technology
𝟓𝟎𝝁𝒎
Anode
Cathode

8. Outline
Design of the avalanche diode
Design of the pixel electronics
3D integration
Tape-out
Preliminary tests
Design of a testing board

9. Design of the pixel electronics – 2D level
Geiger-mode operation:
- - // - -
𝑽 𝑫
𝑰 𝑫 l
𝑽 𝒃𝒅
𝑽 𝒃𝒊𝒂𝒔 = 𝑽 𝒃𝒅 + 𝑽 𝒆𝒙
𝑰 𝑫 𝐢𝐬 𝐧𝐨𝐰 ~ 𝟎 𝑨, hence working point moves back to 𝑽 𝑫 = 𝑽 𝒃𝒅 + 𝑽 𝒆𝒙
Impinging photon at 𝑡= 𝑡 0
𝑽 𝑫
𝑰 𝑫
𝑽 𝒃𝒅 + 𝑽 𝒆𝒙 𝑹 𝑳
Working point at or below 𝑽 𝒃𝒅
Quenching
Avalanche
Initial bias
𝑽 𝒃𝒅 + 𝑽 𝒆𝒙 l
Recharge to the initial bias 𝒕
𝑽 𝒐
𝑽 𝒐 =𝟎𝑽
𝒕 𝒊 l
𝒕 𝟎
𝑽 𝒐 = 𝑽 𝒆𝒙

10. Design of the pixel electronics – 2D level
A time integration-base passive quench - active recharge circuit
Vignetti M. et al “A time-integration based quenching circuit for Geiger-mode avalanche diodes” 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015) June 7-10, 2015 Grenoble, France (2015)

11. Design of the pixel electronics – 3D level
The 3D pixel electronics has to be conceived in order to account for the possible parasitics introduced by the vertical interconnections.
SET_CoincidenceWindow
Coincidence_OUT
Coincidence circuit
Pulse shaping circuit
Bottom TIER
3D interconnection
Top TIER
Coincidence circuit
3D Pixel
SET_CoincidenceWindow

12. Outline
Design of the avalanche diode
Design of the pixel electronics
3D integration
Tape-out
Preliminary tests
Design of a testing board

13. 3D integration
Dedicated 3D technologies
Flip-chip assembly VS
Source: Tezzaron
Parasitics
Bump-bond based assembly
Large bump diameter
Chip-level assembly: Affordable!
negligible parasitics
very large scale integration compatible (𝑑~1𝜇𝑚)
Wafer level  very expensive!
3D integration strategy: TOP tier and BOTTOM tier on the same chip!
Only external PADs on BOTTOM die will be wire-bonded

14. Outline
Design of the avalanche diode
Design of the pixel electronics
3D integration
Tape-out
Preliminary tests
Design of a testing board

15. Tape-out
A test-chip submitted for TAPE-OUT on April 23rd in a MPW run.
Chips received on mid-September 2015
3D pixels cells
2x2 hybrid matrix cells
Test structures

16. Outline
Design of the avalanche diode
Design of the pixel electronics
3D integration
Tape-out
Preliminary tests
Design of a testing board

17. Preliminary tests Signal analysis Test setup Setup is good for
Daughter board
Setup is good for
Simple preliminary tests to check the different circuits and test structures
Some nice measurements can be obtained with a good oscilloscope
But
It is not practical for a full characterization
Parasitics
Dedicated testing board is required!

18. Preliminary tests Tunable hold-off time
154ns
44ns
Potentially short hold-off time
A dark count followed by an after-pulse
29ns

19. Preliminary tests Coincidence between two on-plane diodes
𝑉 𝑒𝑥 =1 𝑉 and 𝑡 ℎ = 75 𝑛𝑠 :
diode “bottom” (left)  38 kHz (15,2 𝐻𝑧/𝜇 𝑚 2 )
diode “top” (right)  16,8 kHz (6,7 𝐻𝑧/𝜇 𝑚 2 )
 Results are similar to what it is found in literature
After-pulsing is negligible for 𝑡 ℎ >200𝑛𝑠
Estimated FCR = 13 Hz
OBS:calculated FCR (not measured!).
Measurements show a negligible amount of fake pulses in a wide acquisition window in the oscilloscope.
Accurate measurements not yet available due to oscilloscope and test-bench limitations

20. Outline
Design of the avalanche diode
Design of the pixel electronics
3D integration
Tape-out
Preliminary tests
Design of a testing board

21. Design of a testing board
Signal analysis
Custom PCB board
FTDI (FPGA)
USB
Daughter board

22. Conclusions
A PEB safe avalanche diode has been designed accounting for the technological limitation imposed by the adopted CMOS process
Dedicated electronics for both Geiger-mode operation as well as coincidence detection have been devised
A 3D coincidence-based pixel as well as a small hybrid matrix has been successfully designed.
Test-chip submission for tape-out has been successfully accomplished
Preliminary results on functionality check are goods.
A dedicated test board design for an optimal characterization is in progress

23. Thanks!