1. Digital Logic Circuits Review
Dr. Voicu Groza
SITE Hall, Room 5017
ext. 2159
Voicu Groza 2011

2. Outline Logic Functions Boolean Algebra Logic Functions Minimization
Logic Gates
Combinational Circuits
Sequential Circuits
Specification
Analysis
Design

3. Logic function Logic Circuit Logic Inverter z = x
zi = Fi(x0,x1,x2, …) | zi {0,1}, i = 0,1,2, … m, xk {0,1}, k = 0,1,2, …n
where Fi = logic functions ; xk = input variables; zi = output variables
where Logic 0 = FALSE and Logic 1 = TRUE
Logic function F
can be represented by logic (Boolean) expressions, truth tables, K-maps, logic diagrams of the logic circuits that implement these functions.
Block diagram x0 x1 x2 x3
Logic
Circuit x
VHi ≈ +5V = TRUE = Logic 1
VLo ≈ 0V = FALSE = Logic 0 z 1 t
[ns]
(Ideal) time diagram z
Logic Inverter
x z x z 1
z = x

4. Approximations of Real Time-Diagrams
VHi ≈ +5V = TRUE = Logic 1
VLo ≈ 0V = FALSE = Logic 0 z 1 t
[ns]
td propagation delay
Approximations of Real Time-Diagrams
Propagation Delay
Logic Inverter x 1
0 z t
[ns]
x z
50%
z = x
Rise / Fall Time x z 1
90%
50%
10% td
delay tr
rise time tf
fall time

5. BOOLEAN ALGEBRA over {0, 1}
{B, =, +, , , 0, 1}, where:
B = set with at least 2 distinct elements;
0, 1 = 2 constants  B
+ OR
 AND
= equivalence relationship, with usual properties:
reflexivity: ( x  B)  (x = x)
symmetry: ( x, y  B)  (x = y  y = x)
transitivity: ( x, y, z  B)  (x = y and y = z  x = z)
Parentheses are allowed

6. BOOLEAN ALGEBRA over Boolean Vectors
Bn = {(a1, a2, … , an) | ai  {0,1}}
Let a=(a1, a2, … , an) and b = (b1, b2, … , bn)  Bn
define
a  b = (a1  b1, a2  b2, … , an  bn)
a  b = (a1  b1, a2  b2, … , an  bn)
a=(a1, a2, … , an)
then Bn, ,  , , 0,1 is a Boolean algebra, where, 0 = (0,0, …, 0) and 1 = (1,1, …, 1)
Basic Boolean Identities = axioms and theorems

7. BOOLEAN ALGEBRA AXIOMS
B={0,1} OR AND
Closeness:
 a, b  B a + b  B a  b  B
Identical element:
 a  B a + 0 = 0 + a = a [1] a  1 = 1  a = a [4]
Commutative:
 a, b  B a + b = b + a [9] a  b = b  a [10]
Distributive:
 a, b, c  B a+(bc) = (a+b)  (a+c) [14] a  (b + c) = ab + ac [13]
Complement:
 a  B,  a a + a = 1 [7] and a  a = [8]
Associative:
 a, b, c  B (a + b) + c = a + (b + c) [11] (a  b) c = a (b  c) [12]
NOTE: the equation numbers in square brackets, e.g. [1], coresspond to the Table 1-1 of Mano’s textbook

8. BOOLEAN ALGEBRA Fundamental Theorems
Idempotency
Null
Absorption
Uniting
Theorem 1a a + a = a [5]
Theorem 2a a + 1 = 1 [3]
Theorem 6a a + a · b = a
Theorem 7a a +a · b = a + b
Theorem 8a a · b + a ·b = a
Theorem 1b a  a = a [6]
Theorem 2b a · 0 = 0 [2]
Theorem 6b a · (a + b) = a
Theorem 7b a · (a + b) = a · b
Theorem 8b (a + b)(a +b) = a
Consensus: 13. (a • b) + (b • c) + (a' • c) = D. (a + b) • (b + c) • (a' + c) = a • b + a' • c = (a + b) • (a' + c)
Factoring: (a + b) • (a' + c) = D. a • b + a' • c = a • c + a' • b (a + c) • (a' + b)
Theorem 3 [17] a = a
De Morgan’s Theorems:
Theorem 5a [15]
Theorem 5b [16]
Theorem 5a’
Theorem 5b’
NOTE: equation numbers in square brackets, e.g. [5], coresspond to Table 1-1 of Mano’s textbook

9. Proving Theorems (Perfect Induction)
“ Proof ”: X. (Y+Z) = X.Y+X.Z
AND rules (identities)
0 . X = 0
1 . X = X
X . X = X
X . X = 0
X . Y = Y . X
X . (Y . Z) = (X . Y) . Z
X . (Y + Z) = X . Y + X . Z
X . Y = X + Y
X Y Z X. (Y+Z) X.Y+X.Z
____________________________________________________________
(2)
(4)
(6)
(8)
(10)
(12)
(13)
(16)
NOTE: equation numbers, e.g. (2), are from Table 1-1 of Mano’s textbook

10. Proving Theorems (Perfect Induction)… continued
“ Proof ”:
OR rules (identities)
0 + X = X
1 + X = 1
X + X = X
X + X = 1
(X) = X
X + Y = Y + X
X + (Y + Z) = (X + Y) + Z
X + Y . Z = (X + Y) . (X +Z)
X + Y = X . Y
X Y Z X + Y.Z (X+Y) . (X+Z)
_____________________________________________________________________
(1)
(3)
(5)
(7)
(17)
(9)
(11)
(14)
(15)
NOTE: equation numbers, e.g. (1), are from Table 1-1 of Mano’s textbook

11. These equations can be generalized
DeMorgan’s Theorems
X . Y = X + Y
X + Y = X . Y
X Y X . Y X + Y
X + Y X . Y
_______________________________
These equations can be generalized

12. All Logic Functions of Two Variables
16 possible functions of 2 input variables:
2**(2**n) = functions of n inputs x F y x y F0 F1 F2 F3 F4 F5 F6 F7 F8 F9
F10
F11
F12
F13
F14
F15 1
X Y possible functions (F0–F15) 1
not X
X and Y
X or Y
not Y X Y
X xor Y
X = Y
X nor Y not (X or Y)
X nand Y not (X and Y)

13. Digital Logic Gates

14. Minterms = one product term functions
ANDed product of literals – input combination for which output is true
Each variable appears exactly once, in true or inverted form (but not both!)
ABC
m0=
m1 =
m2 =
m3 =
m4 =
m5 =
m6 =
m7 =
000 1
001
010
011
100
101
110
111

15. Logic functions representation using Canonical form
Canonical Sum of Products (SoP): F = ABC + ABC + ABC + ABC
Sum of minterms: F = m m m m7
; F = Σ (2, 3, 5, 7) A B C
A . B . C F
min-
term A B C F
(m0)
(m1)
(m2)
(m3)
(m4)
(m5)
(m6)
(m7)

16. Simplifying logic functions using Boolean algebra rules
F = ABC + ABC + ABC + ABC
F = (ABC + ABC) + (ABC + ABC)
F = A(BC + BC) + A ( BC + BC)
F = AB( C + C) + AC ( B + B) 1 A B C
A . C F
A . B
F = AB + AC

17. Product-of-Sums Canonical Form
Maxterm = ORed sum of literals in which each variable appears exactly once in either true or complemented form, but not both!
P-o-S = Conjunctive Normal Form can be obtained by:
A. Finding the truth table rows where F is 0
0 in input column implies true literal
1 in input column implies complemented literal
F(A,B,C) = ΠM(0,2,4) =
= (A + B + C) (A + B’ + C) (A’ + B + C) A 1 B C
Maxterms + = M 2 3 4 5 6 7 F F’
or by
B. Negating the disjunctive form (SoP) of the negated function (F’):
Start from the Sum-of-Products of
F' = A'B'C' + A'BC' + AB'C'
Then apply de Morgan's:
F = (F')' = (A'B'C' + A'BC' + AB'C')‘ =
= (A+B+C) (A+B'+C) (A'+B+C)

18. Logic functions Representation Using Karnaugh MapsB C
000
111
101
100
001
010
011
110
Karnaugh map => graphical representation of a truth table of a logic function.
A B C F
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Each line in the truth table corresponds to a square in the Karnaugh map.
The Karnaugh map squares are labeled so that horizontally or vertically adjacent squares differ only in one variable. (Each square in the top row is considered to be adjacent to a corresponding square in the bottom row. Each square in the left most column is considered to be adjacent to a corresponding square in the right most column.)
Recommended for functions represented by sum of minterms logic expressions
1 3
A BC 1 B C
A BC 1
0 2
4 6

19. 4 variable logic functions representation on Karnaugh maps
AB CD 00 01 11 10 C B D A
A B C D F
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7) …
(8) …
(9) …
(10) …
(11) …
(12) …
(13) …
(14) …
(15)
Recommend for functions represented by
sum of minterms logic expressions
AB CD 00 01 11 10 C B D A

20. The Uniting Theorem Key tool for simplification: A (B' + B) = A
Essence of simplification:
Find two element subsets of the ON-set where only one variable changes its value – this single varying variable can be eliminated and a single product term used to represent both elements
F = A'B'+AB' = (A'+A)B' = B'
A B F
0 0 1
0 1 0
1 0 1
1 1 0
B has the same value in both on-set rows => B remains
A has a different value in the two rows => A is eliminated

21. Implicants Given a logic function z = F(x0, x1, x2, …)
Implicant = product term that,
if equal to 1, implies f = 1
whenever the implicant is 1=> f = 1
f can be 1 other times, as well: it may be implied by other implicants, rather than the 1 at hand
from the K-map point of view, an implicant is a rectangle of 1, 2, 4, 8, … (any power of 2) 1’s
Prime Implicant = cannot be totally covered by another implicant
(e.g., AC, BC, A’B)
Each “1” which is covered by a single implicant is marked with a star (*)
Essential Prime Implicant = a prime implicant that contains at least one “1*”
A minimum cover of a logic function has to contain all its prime implicants F
A B C
A B
A B C B
B C A
A B C C
A B C
A C B
A B
A C * A
0 1*
B C C

22. Simplifying logic functions using Karnaugh maps … looping
The logic function can be simplified by replacing canonical terms with a minimum cover of prime implicants, obtained by properly combining squares (looping) of the Karnaugh maps which contain 1s.
Looping a pair of adjacent 1s eliminates the variable that appears in
both direct and complemented form.
PI: AC, BC, A’B
EPI: AC, A’B
Redundant Implicant: BC
0 1
A B C 00 01 11 10
A B C F
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7) *2 AC
A BC * 1
B C
A B B
A B * A
0 1*
B C C
A C

23. Simplifying logic functions using Karnaugh maps … more looping
A B C D F
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
Looping a quad of adjacent 1s eliminates the two variables that appears in both direct and complemented form. CD
EPI*
Secondary PI AB
B D 00 1* BC 01 * 11 * BD CD 10 1* CD or BC
F = BD + BD +

24. SoP/NAND & PoS NOR implementation
Remember DeMorgan’s Theorem
Equivalent Gate Symbols A B
A+B A B
A . B =
A . B = A + B
A+B A B =
A . B A B
A + B = A . B
PoS/ NOR
SoP/NAND

25. TWO-LEVEL NAND gate implementation of the “Sum-of-Product” logic functions
F = AB + AC
NAND gates are faster than ANDs and
ORs in most technologies A B C F
X = ( X ) A B C F

26. Incompletely Specified Logic Functions
dc -> x = don’t care terms
Don't care terms can be treated as 1’s or 0’s, depending on which one is more advantageous.
So, if including a don't care in a group makes
the group bigger, or
makes it possible to reduce the number of groups,
the don't care should be included in the group, but not otherwise!
A B C D F
(0)
(1)
(2)
(3)
(4)
(5) x
(6)
(7)
(8)
(9)
(10) x
(11)
(12)
(13) x
(14) x
(15) x AB CD 00 01 11 10 *
1* x x
x 1*
Secondary EPI PI
EPI* AD AD
ABC AD
ABC AD
BC D
ABC or
BCD
Fmin = AD + AD +
BC D

27. Realizations of Incompletely Specified Logic FunctionsB C D F F0 F1 F2 F3 F4 F5 F6 F7 F8 F9
F10
F11
F12
F13
F14
F15
(0) 1
(1)
(2)
(3)
(4)
(5) x
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15) x AB CD 00 01 11 10 *
1* x x
x 1*
ABC or
BCD
F13min = AD + AD +
ABC or
BCD
F13 = A ⊕ D + A D D’ B’ C’ A D A’ B’ C’

28. Combinational Circuits
A combinational circuit is a setup of a number of connected logic gates implementing the logic function between n input variables and m output variables.
In a combinational circuit, the output is time-independent and does only depend on the circuit's input
In a combinational circuit, the output is “re-computed" as soon as a change in the input occurs, and it is presented to the output with a delay
z = F(x0, x1, x2, …) | z {0, 1}, xk {0, 1}, k = 0,1,2,…
F can be represented by
logic expression
truth table
K-map x0 x1 x2 x3
Logic
Circuit z

29. Combinational Circuit Design Procedure
1. Define the problem
2. Assign different letter symbols to the input and output variables
3. Derive the truth table defining the relationship between the inputs and the outputs
4. Obtain the simplified boolean expression for each output variable
5. Draw the circuit's logic diagram HA
Cout S
Half Adder A B
A B Cout S HA
Cout S
Cout = (A · B)
S = A ⊕ B A B

30. Full Adder
A B Cin Cout S
Equations are modified as follows.
Cout = ((A ⊕ B) · CIN) + (A · B)
S = A ⊕ B ⊕ CIN
HA1
HA2
C_OUT A B
SUM
C_IN

31. Sequential Circuits
The output of sequential circuits is logic function of the present state of external inputs, but also on the state of these inputs in past. Therefore, they are also referred to as circuits with memory.
The sequential circuits are formed by additional feedback signals, looped backward from the output to the input of the circuit (referred to as signals of internal state of the circuit). By this backward loop, the dependence on previous values of inputs is implemented as dependence on the current internal state of the machine.
The sequential switching circuits are
Asynchronous circuits = operate at time events defined by changes of inputs
Synchronous circuits = operate at time events defined by additional control signal called clock.
Memory

32. Classical automata Finite State Machines (FSMs) input I
A state diagram is a directed graph connecting all the possible states of the sequential circuits, where each transition has the following form:
Finite State Machines (FSMs)
input I
Internal state S
output O
(clock)
Example
- I = {e}
- O = {0,1,2,3}
- S = {S0,S1,S2,S3}
Initial state = S0
State Diagram:
Next state S+ computed by function  Output O computed by function 
Output Function
Transition Function
e=1 S0 S1
Moore-automata: O =  (S); S+ =  (I, S)
Mealy-automata O =  (I, S); S+ =  (I, S) 1
e=1
e=1 S3 S2 3 2
e=1

33. Sequential Circuits as FSM
Input set: X={Xi |i=0,m-1} X= {X0,X1,X2,…, Xm-1}
Output set: Z={zj | j=0,p-1} Z = {Z0,Z1,Z2,…, Zp-1}
States: S = {Sk | k=0,q-1} S={S0,S1,S2,…, Sq-1}
Transition function δ :XxS→S
Output function λ : X x S →Z
S(t+Δt) = δ(S(t),X(t))
Z(t) = λ (S(t),X(t))
If Δt=T and t = nT
(i.e., synchronous)
Sn+1 = δ(Sn,Xn)
Zn = λ(Sn,Xn)
Combinational
Circuits
Memory
S(t+Δt)
Z(t)
S(t)
X(t)
Z(t) = λ(S(t),X(t))
S(t+Δt)=δ(S(t),X(t))
Present State
Next State
Example S-R Latch (asynchronous)
A flip-flop or a latch holds (stores) 1 "bit". "Bit" ::= "binary digit." Q S R S R Q 34

34. S-R Latch ELEMENTARY MEMORY ELEMENTS: LATCHES AND FLIP-FLOPS 3 NAND 2
I1 I2 F
NAND
S-R Latch S Q R
= 0
= 1 3
(Set-Reset) Q S R
= 1 S
= 1
= 0 Q
= 0 t
SET 2 Q
Weird state!!
Set state
Reset state
Hold state
S R Qt+Δt Qt+Δt
Qt Qt
T S R
3 1 1
2 1 0
1 0 1
0 0 0 R S Q R
= 0
= 1
RESET 1 S Q R
= 1
= 0
HOLD R SR 00 01 11 10 X 1 Q ( t ) S

35. FUNCTIONAL or CHARACTERISTIC TABLE
SR Latch
FUNCTIONAL or CHARACTERISTIC TABLE
EXCITATION TABLE
S Q R St Rt Qt
Qt+Δt 1 0? St Rt
Qt+Δt
Function Qt
Hold x 1
Reset
Set 0?
Forbidden
(non-sense)
BLOCK DIAGRAM
STATE TABLE
Present
Next
State
Qt+Δt SR Qt 00 01 10 11 1 -
Characteristic Equation:
00v01 1
00v10 10 01 S Q 00
STATE DIAGRAM
00v10 01 10 QQ
00v01 11
SR=01 Q R 10 01 10
00v10
LOGIC DIAGRAM
00v01

36. JK Flip Flop - or how to eliminate the forbidden state?
FUNCTIONAL or CHARACTERISTIC TABLE
JK Flip Flop - or how to eliminate the forbidden state?
EXCITATION TABLE Jn Kn
Qn+1
Function Qn
Hold x 1
Reset
Set
Toggle
00v01 1
00v10
10v11
01v11
Positive-Edge -Triggered
JK Flip-Flop (rising edge)
J Q
CLK K
CHARACTERISTIC EQUATION:
Positive Pulse
( )
Negative Pulse
( )
CLK 1
CLK 1
Negative-Edge -Triggered
JK Flip-Flop (falling edge) t t
Positive
Edge
J Q
CLK K
Negative
Edge
Negative
Edge
Positive
Edge
Leading edge
Trailing
edge
Leading edge
Trailing
edge

37. Clock Pulse Definition
IEEE Std 181™ “IEEE Standard for Transitions, Pulses, and Related Waveforms,” IEEE Instrumentation and Measurement Society
negative-going transition: terminating state is more negative than its originating state.
positive-going transition: terminating state is more positive than its originating state.
transition duration: the difference between the two reference level instants of the same transition. Unless otherwise specified, they are the 10% and 90% of the reference levels.
NOTE: The following terms are depreciated: risetime (rise time), falltime (fall time), leading edge, rising edge, trailing edge, falling edge, and transition.
90%
10%

38. Gated D Latch δ S Enable D S R Q Q Q Q 0 1 1 0 0 0 1 1 0 1 1 1 1 0 1 0
0 1
1 0 D Q Q R
Enable
Enable 1 D S Q R
Hold
“Hold”state
“Transparent” state

39. D Flip-Flop Synchronous Master-Slave D CLK Q D1 EN1 EN2 Slave Master D
Enab.
Master
Latch 1
Latch 2
Synchronous
Master-Slave
D Flip-Flop 1 D
CLK
EN1
EN2 D1 Q
Latch 2 is Transparent
Latch 2 is Holding
Latch 1 is Transparent
Latch 1 is Holding
Latch 1 is
Transparent
D1 = Din*
Din*
Q = D1 = Din*
Input data D may change
Changed input data D enter Latch 1
The state of the flip-flop’s output Q copies input
D when the positive edge of the clock CLK occurs
Positive-Edge-Triggered
D Flip-Flop

40. FUNCTIONAL or CHARACTERISTIC TABLE
Synchronous
D Flip-Flop
(Edge-triggered)
FUNCTIONAL or CHARACTERISTIC TABLE
EXCITATION TABLE Q D
CLK Dn Qn
Qn+1 1 1
BLOCK DIAGRAM
STATE DIAGRAM
Qn+1 = Dn
Dn = Qn+1
TIME DIAGRAM
Setup time
There is a timing "window" around the clocking moment during which the input must remain stable and unchanged in order to be recognized.
Hold time D
Din*
Input data D may change 1
CLK
Propagation time 1 Q
Q = Din*
The state of the flip-flop’s output Q copies input
D when the positive edge of the clock CLK occurs
Positive-Edge-Triggered
D Flip-Flop

41. T Flip-Flop FUNCTIONAL or EXCITATION TABLE CHARACTERISTIC TABLE Tn Qn
Positive-Edge -Triggered
T Flip-Flop (rising edge)
TABLE Tn Qn
Qn+1 1 Q T
CLK 1

42. SEQUENTIAL CIRCUITS Sn Next State Logic State Register Sn+1 = δ(Sn,Xn)
... 2m+n rows of binary combinations ranging from 0 to 2m+n − 1.
SEQUENTIAL CIRCUITS
After the n-th clock, the outputs (Zn) and the flip-flops next-states (Sn+1), i.e., the outputs of the Combinational Circuit, depend on the circuit’s inputs (Xn) and the flip-flops current states (Sn). The state table is a truth table showing the circuit’s outputs
Zn = λ(Sn,Xn) and the flip-flops next states Sn+1 = δ(Sn,Xn) for each circuit’s input/flip-flops present states combination (Xn/Sn). For a sequential circuit with m flip-flops, p input
variables, and q output variables, the state table consists of:
m columns representing the flip-flops present states
p columns representing the circuit’s inputs
m columns representing the flip-flops next states
q columns representing the circuit’s outputs m Sn
Next State Logic
Sn+1 = δ(Sn,Xn)
Transition function
Combinational Circuits
Output Logic
Zn = λ(Sn,Xn)
Output function
State Register
Flip Flops
Sn+1 m m Sn p Xn Zn q
Clk

43. Synchronous Sequential Circuits as FSM
Next State Logic
Sn+1 = δ(Sn,Xn)
Transition function
Combinational Circuits
Output Logic
Zn = λ(Sn,Xn)
Output function
State Register
Flip Flops
Sn+1 Zn Sn Xn
Clk
Sn = Present (current) State
Next State
Inputs
Outputs
Inputs
Next State Logic
Sn+1 = δ(Sn,Xn)
Transition function
Combinational Circuits
Output Logic
Zn = λ(Sn,Xn)
Output function
Sn+1 Xn Sn
State Register
Flip Flops
Sn = Present (current) State Zn
Outputs
Next State

44. Moore FSM Output based on present state only: Zn = λ(Sn)
The behavior of sequential circuits can be described using the Finite State Machine (FSM) model
Mealy FSM Output based on present state and present input: Zn = λ(Sn,Xn) m δ
s(n) λ
Next state
Register
State
z(n)
x(n) p
s(n+1) m
present
state q
Present input
clk
Moore FSM Output based on present state only:
Zn = λ(Sn) m δ
s(n) λ
z(n)
Next state
Register
State
x(n) p
s(n+1) m
present
state q
Present input 45
clk

45. 2. USE SR Characteristic (functional) table
SEQUENTIAL CIRCUITS ANALYSIS
Find the Transition Function of a ... D (Transparent) Latch
0. Being given the logic diagram of sequential circuit:
3. Derive the State Table (i.e., the truth table of the transition function) of the analyzed sequential circuit, which is … discovering the D-FF Characteristic (or Functional) Table! Q S R D
Enable
ANALYSIS =
from circuit to transition table
= find Q(t+Δt) = δ(D(t),Q(t))
Enable D Qt+Δt Qt+Δt
Qt Qt
0 1
1 0
0 x
1 1
S=D.Enable
R=D.Enable 1
2. USE SR Characteristic (functional) table 3
Qt Qt
0 1
1 0
Enable D S R Qt+Δt Qt+Δt
Conclusion: the analyzed circuit is a D Latch implemented with an SR Latch.
When the Enable =1 the information present at the D input is stored in the latch and will “appear as it is” at the Q output ( => it is like that there is a “transparent” path from the D input to the Q output)
S R Qt+Δt Qt+Δt
Qt Qt 2

46. SEQUENTIAL CIRCUITS ANALYSIS
from circuit to state diagram = find
A(n+1) = δA(x(n),A(n),B(n))
B(n+1) = δB(x(n),A(n),B(n))
y(n) = λ(x(n),A(n),B(n))
DA = x A +x B = A+
DB = x A’ = B+
y = x’ A +x’ B
Transition function δ
Output function λ
State Table
Present
State In
Next
Out A B x A+ B+ y 1
Logic Diagram
State Register δ
State Diagram
nodes = states
arcs = transitions λ

47. Sequential Circuit Design Procedure
Sequential Circuit Design = from Finite State Machine FSM => Logic Circuit
Sequential Circuit Design Procedure
Step 0: From the problem specification, create the state diagram which shows all of the states that the FSM can be in, and how to switch from one state to another Step 1: State Table - transition (δ) and output (λ) functions Make a state table based on the problem specification or state diagram. It may show the next states Sn+1 and outputs Zn as functions of present states Sn and inputs Xn (transition function: Sn+1 = δ(Sn,Xn), output function Zn = λ(Sn,Xn). State minimization = reduce the number of states in the table (not in CEG2136) Step 2: State Assignment (Encoding). Assign binary codes to the states in the state table, if they were not assigned already. If you have N states, your binary codes will have at least log2 N digits, and your circuit will have at least log2 N flip-flops  Transition table (i.e., binary-coded state table) = a state table with encoded states. Step 3: Excitation Table and Equations. Choose the type of flip-flops to be used. For each flip-flop and each row of your transition table, find the flip-flop input values that are needed to generate the next state from the present state. You may use flip-flop excitation tables. Step 4: Find simplified equations for the flip-flops inputs & the circuit outputs Z. Step 5: Build the circuit! 48

48. Design D-Latch using SR Latch1
D.En=01
En=0 Q S R D
Enable δ
START HERE Qt
Qt+Δt St Rt x 1
En D Qt+Δt Qt 1
0 x
1 0
1 1
Given: D-Latch State Diagram or Characteristic Table
SR Excitation Table
respects SR=0
Step 1: Initial State table 1
Step 4: SR input equations D S Q I S
0 0 x 1 x
En DQt x 1 II
State table of Sequential Circuit to be Designed
Step 5 4
Enable R En D Qt
Qt+Δt S R x 1
S = En.D
R = En.D 5 4
S = En.D
R = En.D 4 5’ R
En.D
En DQt x 1
En.D D Q S
x x2 En Q R
Excitation table for
Sequential Circuit to be Designed
Step 3

49. Design a D-Latch using SR Latch ++
START
Given: D-Latch Characteristic (functional) table
Design a D-Latch using SR Latch ++ Qt
Qt+Δt St Rt x 1
Comb.
Circuits
En D Qt+Δt Qt 1
0 x D S Q
SR Excitation Table
Enable
Step 1 R
Step 3 En D Qt
Qt+Δt S R x 1
State table of the Sequential Circuit to be Designed (D-Latch)

50. Design a JK-FF using SR Latch
J KQt
0 0 x *2 J
Comb.
Circuits Qt
Qt+Δt St Rt x 1
S= JQ’ S Q 1
1 4 x*
SR Excitation Table
J KQt K
R= KQ R
x x*2
Step 1
Step 3 1
0 4 0* J K Qt
Qt+Δt S R x 1
State table of the Sequential Circuit to be Designed (JK)

51. SEQUENTIAL CIRCUITS DESIGN
FSM (Finite State Machine) Representation Design = from State Diagram => Logic Circuit Diagram
Problem: Apply the Sequential Circuit Design Procedure to derive the logic diagram of a logic circuit which implements the following FSM
Step 1
Present State Sn In
Next State Sn+1
Sn+1 = δ(Sn,Xn) A B x A+ B+ 1
x=0
State
Diagram
=> => => => 00 00
x=0
x=1
x=1
x=0 01 11
x=1
x=1 10
x=0

52. FSM => => => Transition Table
SEQUENTIAL CIRCUITS DESIGN
FSM => => => Transition Table
Step 1
Sn+1 = δ(Sn,Xn)
Present State Sn In
Next State Sn+1
x=0 00 10 11 01
x=1 A B x A+ B+ 1
=> => => =>

53. FSM => => => Transition Table
SEQUENTIAL CIRCUITS DESIGN
FSM => => => Transition Table
Step 1
Sn+1 = δ(Sn,Xn)
Present State Sn In
Next State Sn+1
x=0 00 10 11 01
x=1 A B x A+ B+ 1
=> => => =>

54. FSM => => => Transition Table
SEQUENTIAL CIRCUITS DESIGN
FSM => => => Transition Table
Step 1
Sn+1 = δ(Sn,Xn)
Present State Sn In
Next State Sn+1
x=0 00 10 11 01
x=1 A B x A+ B+ 1
=> => => =>

55. FSM => => => Transition Table
SEQUENTIAL CIRCUITS DESIGN
FSM => => => Transition Table
Step 1
Sn+1 = δ(Sn,Xn)
Present State Sn In
Next State Sn+1
x=0 00 10 11 01
x=1 A B x A+ B+ 1
=> => => =>

56. SEQUENTIAL CIRCUITS DESIGN
FSM Excitation Table
Step 3
Present State Sn In
Next State Sn+1
Flip-flops’
Inputs A B x A+ B+ JA KA JB KB 1
Next State Excitation
Equations
Combinational Circuits
State Register
JA QA
clk KA Sn
JB QB
Clk KB x
Clk

57. SEQUENTIAL CIRCUITS DESIGN
FSM Excitation Table
Step 3 A B x A+ B+ JA KA JB KB 1 Qn
Qn+1 Jn Kn x 1
JK FF Excitation Table

58. SEQUENTIAL CIRCUITS DESIGN
FSM Excitation Table
Step 3 A B x A+ B+ JA KA JB KB 1 Qn
Qn+1 Jn Kn x 1
JK FF Excitation Table

59. SEQUENTIAL CIRCUITS DESIGN
FSM Excitation Table
Step 3 A B x A+ B+ JA KA JB KB 1 Qn
Qn+1 Jn Kn x 1
JK FF Excitation Table

60. Efficient Derivation of JK Excitation Equations
Step 3
SEQUENTIAL CIRCUITS DESIGN
Efficient Derivation of JK Excitation Equations Qn
Qn+1 Jn Kn x 1
Qn+1 if Qn= 0 (copy next state where present state is 0)
J <=
x if Qn= 1 (put don’t care where present state is 1)
Qn+1 if Qn= 1 (copy complement of the next state
K <= where present state is 1)
x if Qn= 0 (put don’t care where present state is 0) Qn
Qn+1 Jn Kn x 1
NOTE: Use this “recipe” just to expedite generation of the JK input excitation functions of a given FSM.
Boolean expressions of J and K has to be expressed in terms of available signals, like present states (Qn) and inputs (X), not next states (Qn+1), which of course are not available in the present!!!

61. FSM Excitation Table (JA)
SEQUENTIAL CIRCUITS DESIGN
FSM Excitation Table (JA)
Step 3 A B x A+ B+ JA KA JB KB 1 Qn
Qn+1 Jn Kn x 1
copy Qn+1 if Qn= 0
J =>
fill with x if Qn= 1

62. FSM Excitation Table (JB)
SEQUENTIAL CIRCUITS DESIGN
FSM Excitation Table (JB)
Step 3 A B x A+ B+ JA KA JB KB 1 Qn
Qn+1 Jn Kn x 1
Qn+1 if Qn= 0
J =
x if Qn= 1

63. FSM Excitation Table (KA)
SEQUENTIAL CIRCUITS DESIGN
FSM Excitation Table (KA)
Step 3 A B x A+ B+ JA KA JB KB 1 Qn
Qn+1 Jn Kn x 1
Qn+1 if Qn= 1
K =
x if Qn= 0

64. FSM Excitation Table (KB)
SEQUENTIAL CIRCUITS DESIGN
FSM Excitation Table (KB)
Step 3 A B x A+ B+ JA KA JB KB 1 Qn
Qn+1 Jn Kn x 1
Qn+1 if Qn= 1
K =
x if Qn= 0

65. Excitation Equations & Implementation
Present State Sn
Step 4 KA B
Flip-flops’
Inputs Bx A In JA B A B x JA KA JB KB 1 Bx A
x x x x
x x x x 1 x 1
KA = Bx x
JA = Bx
Step 5 KB B Bx A x
JB =KB A JB B
x x 1 1
x x 1 0 Bx A 1
x x
x x JB x B 1
KB = x+A’B KB
JB = Ax x

66. Synchronous 4-bit Counter
Present state Sn
Next state Sn +1 Q3 Q2 Q1 Q0 1 x
Sequential Circuit Block Diagram
JK-FF
Excitation Table
Next State Excitation
Equations
Combinational Circuits
State
Register Sn
J Q
clk K
Clk Qn
Qn+1 Jn Kn x 1
Transition Table
State Diagram
1111
0001
0000
1000
1100
1101
0011
0010
0110
1110
Reset

67. Counter Des ign Excitation Table Present state Sn Next state Sn +1
Q3 input
Q2 input
Q1 input
Q0 input Q3 Q2 Q1 Q0 J3 K3 J2 K2 J1 K1 J0 K0 1 x
Counter Des ign

68. Synchronous 4-bit Counter Excitation Equations
Q1Q0 00 01 11 10
Q3Q2 1 x
Q1Q0 00 01 11 10
Q3Q2 x 1
Q1Q0 00 01 11 10
Q3Q2 x 1
Q1Q0 00 01 11 10
Q3Q2 x 1

69. Synchronous 4-bit Counter Implementation with JK flip-flops