1. Embedded Systems Programming
AVR Architecture 1

2. AVR Architecture - Recap
Main components:
CPU (containing ALU)
Ports for input and output
Internal-only data and address busses
Internal clock and dividers (Up to 8MHz - thus can achieve up to 8 MIPS)
On-chip memory systems Usage
EEPROM 4K bytes (read only) Fixed ‘Data’ / Configuration
FLASH 128K bytes (read only) Program code
SRAM 8K bytes (read / write) Volatile data
There exist a wide variety of AVR implementations
See for useful information on the different AVR implementations and the instruction set variations. 2
Embedded Systems Programming A Richard Anthony, Computer Science, The University of Greenwich

3. AVR Architecture – ATmega1281 interfacing (1)
The 64 pin package has 54 I/O pins, comprising 6 * 8-bit parallel I/O Ports (A-F)
and 1 * 6-bit parallel I/O Port (G)
In addition, the Microcontroller has a number of other I/O interfaces:
Direct input signals Reset (not strictly I/O, but provides external control I/P)
Hardware interrupts (INT0-7)
Pin-Change interrupts (PCINT0-7)
Serial communication Serial Peripheral Interface Bus (SPI)
Two Wire Serial Bus Interface (TWI)
Universal Async Receiver/Transmitter (USART) * 2
Analogue Input Analogue to Digital converter (ADC) – 8 channels
Analogue comparator
Timing / Counting Timer / Counter units (6)
Timer pulse output (including PWM)
Timer external clock input
However, there are no additional pins available, so these functions are multiplexed onto the 54 Parallel I/O pins, and are termed the ‘alternate functions’ of these pins.
Embedded Systems Programming A Richard Anthony, Computer Science, The University of Greenwich

4. AVR Architecture – ATmega1281 interfacing (2)
Alternate parallel port functions
Bit
Port A
Port B
Port C
Port D
SPI SS / PCINT0
TWI SCL / INT0 1
SPI SCK / PCINT1
TWI SDA / INT1 2
SPI MOSI / PCINT2
USART1 RXD1 / INT2 3
SPI MISO / PCINT3
USART1 TXD1 / INT3 4
OC2A / PCINT4
ICP1 T1 Input capture trigger 5
OC1A / PCINT5
XCK1 (USART1 Ext Clock In/Out) 6
OC1B / PCINT6
T1 (clock I/P - count external events) 7
OC0A / OC1C / PCINT7
T0 (clock I/P - count external events)
Embedded Systems Programming A Richard Anthony, Computer Science, The University of Greenwich

5. AVR Architecture – ATmega1281 interfacing (3)
Alternate parallel port functions
Bit
Port E
Port F
Port G
USART0 RXD0 / PCINT8 /
PDI (Programming Data Input)
ADC0 1
USART0 TXD0 /
PDO (Programming Data Output)
ADC1 2
XCK0 (USART0 Ext Clk In/Out) /
AIN0 (Analogue Comparator +ve Input)
ADC2 3
OC3A /
AIN1 (Analog Comparator -ve Input)
ADC3
TOSC2 (Ext crystal for T/C2) 4
OC3B / INT4
ADC4 / TCK (JTAG)
TOSC1 (Ext crystal for T/C2) 5
OC3C / INT5
ADC5 / TMS (JTAG)
OC0B 6
T3 (clock I/P - count external events) / INT6
ADC6 / TDO (JTAG) 7
ICP3 T3 Input capture trigger /
CLK0 (Divided System Clock) / INT7
ADC7 / TDI (JTAG)
Embedded Systems Programming A Richard Anthony, Computer Science, The University of Greenwich

6. AVR Architecture - Recap
The heart of the microcontroller is a
CPU. This executes instructions and
controls the other functional blocks.
The address, data and control busses
enable the various functional blocks to
communicate.
Clocks /
Timing
CPU
Various clock sources and timer options
are provided
On-chip memory simplifies deployment
And enables fast access
Memory
There is a wide variety of I/O logic and
ports to enable very flexible interfacing
To the monitored / controlled system
Address / data / control
I/O 6
Embedded Systems Programming A Richard Anthony, Computer Science, The University of Greenwich

7. AVR Architecture - CPU Some key points:
The CPU unit manages the overall behaviour of the microcontroller and
executes instructions
The CPU is closely coupled to the on-chip Static RAM and Program Flash to enable low access times. The on-chip EEPROM is reached via the busses.
The Arithmetic Logic Unit (ALU) executes arithmetic operations on the general purpose registers. The flags in the Status Register are directly updated based on the outcome of ALU actions.
The Stack Pointer always points to an address in SRAM.
The Program Counter points to the next instruction to be fetched. The Instruction Register holds the next instruction to be executed. Both these registers are directly mapped onto Program Flash memory addresses.
Address / data busses
Embedded Systems Programming A Richard Anthony, Computer Science, The University of Greenwich

8. The Stack pointer (advanced) 1
Initialisation
In addition to its role in facilitating return-from-subroutine operation, the stack pointer can be used to temporarily store register contents for two main reasons:
1. Preserving values
Register contents are placed on the stack before a subroutine call is made (push), and are restored by reading them from the stack after the subroutine returns (pop). This enables the subroutine to reuse the same registers for storage, without data loss.
SP →
RAMEND
SRAM
Empty
No subroutine in use Register data saved on the Stack Subroutine called
Register1 data
Preserve register
1 and 2 contents
Restore register
Call Subroutine
Return from
subroutine
Register2 data
Sub return addr 8
Embedded Systems Programming A Richard Anthony, Computer Science, The University of Greenwich

9. The Stack pointer (advanced) 2
2. Passing arguments into a subroutine
The Stack can be used as a means of passing arguments to a subroutine in a similar way to which arguments are passed in a higher level language. In, Out, and In/Out arguments can be supported in this way (but requires very careful Stack manipulation).
The example below illustrates passing ‘In’ arguments to a subroutine
SP →
RAMEND
No subroutine in use Argument on Stack Subroutine called
Register value
to be passed
as argument
Call
Subroutine
Return from
subroutine
SRAM
Empty
Sub ret addr
Argument
Control handed back to callee Subroutine active Stack manipulation
General-
purpose
registers
Retrieve
argument
Restore
ret addr 9
Embedded Systems Programming A Richard Anthony, Computer Science, The University of Greenwich

10. The Stack pointer (advanced) 3
Instructions for direct storage and retrieval to/from the stack
Push Places the contents of a register onto the stack.
Example:
Push R17 STACK ← R17
SP ← SP - 1
Pop Takes a value from the stack and places it into a register.
Pop R17 SP ← SP + 1
R17 ← STACK
Typical calling code sequence
Push registers
Call subroutine
Pop registers 10
Embedded Systems Programming A Richard Anthony, Computer Science, The University of Greenwich

11. 57 Interrupt vectors (inc Reset) Program code starts here
Memory maps and address ranges - Flash
57 Interrupt vectors (inc Reset)
57 separate interrupts
addresses 0x00 – 0x72
Program code starts here
128K bytes of Flash memory are provided on-chip.
This is non-volatile memory and thus is used to store program code and some fixed data such as look-up tables (e.g. a character code table for an LCD display).
Contents are loaded via special programmer hardware and software.
The ‘application flash section’ can be reprogrammed during run-time (e.g. to provide persistent storage of data).
Max program size is assembly instructions (minus the space for the interrupt vectors).
$FFFF 11
Embedded Systems Programming A Richard Anthony, Computer Science, The University of Greenwich

12. Memory maps and address ranges - EEPROM
Electrically Erasable Programmable Read-Only Memory (EEPROM) is non-volatile memory.
The ATmega1281 has 4K bytes of EEPROM on-chip, which can be written to a byte at a time during run time.
Since embedded systems typically have no hard disk, the EEPROM memory is the best option of the on-chip memory options for persistent storage of data. This keeps data separate from the program memory (Flash) which is accessed in pages of 32 words or more.
The EEPROM memory has a dedicated address space, and a special programming technique is required to write to it.
Addresses range: 0x0000 to 0x1000
Use this memory to store configuration data that must remain in the system even when power is off (e.g. Fixed messages, security codes ...) 12
Embedded Systems Programming A Richard Anthony, Computer Science, The University of Greenwich

13. Memory maps and address ranges – SRAM (Data memory 1)
Static RAM (SRAM) is the fastest access memory on the ATmega1281.
SRAM is volatile – use it to hold run-time data, lost when power turned off.
The AVR architecture prevents SRAM from holding program code, as only the FLASH memory is linked to the Program Counter and the Instruction Register.
Similarly, the SRAM is the only memory accessible by the Stack Pointer and other parts of the data-manipulation logic and register mechanisms and thus this is the only place where directly addressable data can be placed.
Data stored in Flash or in EEPROM must first be copied into SRAM before it can be used in program execution. 13
Embedded Systems Programming A Richard Anthony, Computer Science, The University of Greenwich

14. Memory maps and address ranges – SRAM (Data memory 2)
General purpose registers occupy the first 32 addresses in the data
address space
64 I/O registers and 416 External I/O registers occupy the next 480
addresses
Stack
8K bytes of on-chip, direct and indirect addressable SRAM.
This can be used to store data for any purpose, at any time.
Care must be taken when writing to SRAM however, because the Stack occupies the upper addresses and grows downwards (in terms of address).
Expandable by adding external memory in another chip (addressing for this is via ports A and C)
Embedded Systems Programming A Richard Anthony, Computer Science, The University of Greenwich