1. System on Chip Design and Test ECE 715
SV & UVM based Constrained Random Verification Technique
Pranay Samanta

2. Outline Verification and the need of verification
Why System-Verilog for verification
UVM - Methodology made for verification
Example Coding
Understanding why this verification technique is really helpful

3. What is verification
A process used to demonstrate the functional correctness of a design.
To making sure your are verifying that you are indeed implementing what you want.

4. Testing vs Verification
Verification is done on the RTL level or SOC level where testing done in silicon.

5. Respin is expensive
Courtesy: IP verification -Tian-Sheuan Chang

6. Why System Verilog for Verification? Still Evolving
Courtesy:

7. Universal Verification Methodology I

8. Universal Verification Methodology II
Test benches for verilog/VHDL/System C designs.
UVM has system verilog base class library.
Supports constrained random verification.

9. UVM Env (Left Hand Side of Previous Pic)
Pic courtesy: UVM cookbook

10. UVM Base Class Library
Pic courtesy: UVM cookbook

11. Basic Example – 2-bit adder
module two_bit_adder(input clk, input reset, input a, input b, output s, output c, output finish);
always
begin
wait(reset==0);
@(posedge clk);
s = a’b + ab’;
c = ab;
finish = 1;
end
endmodule

12. adder_top.sv module adder_top; `include “adder_env.sv”
run_test(); //test-name passed by command
adder_if vif(clk,reset);
two_bit_adder(clk, reset, vif.a, vif.b, vif.s, vif.c, vif.finish);
//clock and reset generation
endmodule

13. adder_test.sv
class adder_test extends uvm_test; task run_phase(uvm_phase phase); uvm_config_db(#int)(this,”env.agent.sequencer.run_phase”,”def ault_sequence”,adder_seq); endtask endclass

14. adder_seq.sv class adder_seq.sv extends uvm_sequence#(adder_packet);
task run_phase(uvm_phase phase);
for(i==0;i<4;i++)
`uvm_do(req);
`uvm_do_with(req.a=0;req.b=0;) * Will tell later
endtask
endclass

15. adder_packet.sv
class adder_packet extends uvm_sequence_item; rand bit a; rand bit b; bit finish; bit c; bit s; endclass

16. adder_driver.sv
Class adder_driver extends uvm_driver#(adder_packet); task run_phase(uvm_phase phase); reset_signals(); get_and_drive(); endtask task get_and_driver(); seq_item_port.get_next_item(req); send_to_dut(req); item_done(); task send_to_dut(adder_packet vif.clk); vif.a = pkt.a; vif.b = pkt.b; endclass

17. adder_interface.sv virtual interface adder_if(input clk, input reset);
logic a;
logic b;
logic finish;
endinterface

18. adder_top.sv module adder_top; `include “adder_env.sv”
run_test(); //test-name passed by command
adder_if vif(clk,reset);
two_bit_adder(clk, reset, vif.a, vif.b, vif.s, vif.c, vif.finish);
//clock and reset generation
endmodule

19. Basic Example – 2-bit adder
module two_bit_adder(input clk, input reset, input a, input b, output s, output c, output finish);
always
begin
wait(reset==0);
@(posedge clk);
s = a’b + ab’;
c = ab;
finish = 1;
end
endmodule

20. adder_monitor.sv
class adder_monitor extends uvm_monitor#(adder_packet); uvm_analysis_port(#adder_packet) scoreboard_port; uvm_analysis_port(#adder_packet) coverage_port; adder_packet vif.clk iff vif.finish==1); pkt1.a = vif.a; pkt1.b = vif.b; pkt1.s = vif.s; pkt1.c = vif.c; scoreboard_port.write(pkt1); coverage_port.write(pkt1); endclass

21. adder_scoreboard.sv
class adder_Scoreboard extends uvm_scoreboard; function write(adder_packet pkt_score); if(pkt_score.a!=pkt_score.b) begin if(pkt_score.s==1) $display(“Sum is right”); else $display(“Sum is wrong”); if(pkt_score.c==0) $display(“Carry is right”); else $display(“Carry is wrong”); end else …………………………………………………….. ………………………………………………………..

22. adder_coverage.sv class adder_coverage extends uvm_component;
adder_packet pkt2;
covergroup cg; cover_point_1 : coverpoint pkt2.a ; cover_point_2 : coverpoint pkt2.b ; cross_12 : cross cover_point_1,cover_point_2 ; endgroup
function write(adder_packet pkt3);
pkt3.sample();
endfunction
endclass
If not 100%, constrained stimulus needed by test.
`uvm_do_with in sequence.

23. What I have not shown

24. Advantages we have understood
Automatic test generation -> Time is saved for verification. Huge huge benefit.
Constrained Random Verification -> Used to check corner cases. Unexpected bug being found.
Reusable Environment -> Use of the same environment in different project.

25. Why should you be interested in verification?
70% of design time is taken by verification.
Design Engineer : Verification Engineer should be 1:1. But the real scenario is not like that.
So lots of job in verification in VLSI industry.

26. Interested? www.verificationacademy.com www.doulos.com UVM user guide
SV used guide
Enough to understand SV and UVM and be expert in this field. (Considering if you have platform to use your knowledge)