Digital Design Jeff Kautzer Univ Wis Milw.

Digital Design Jeff Kautzer Univ Wis Milw

Review: Digital Information
Information is represented numerically using a binary number system An n bit number has digit weightings 2(n-1) 2(n-2) 2(n-3) …… Example: b = = 26 4 bit binary “nibbles” are abbreviated using hexidecimal 1001b = 9h, 1010b = Ah, 1011b = Bh, … b = Fh Logic 1: Represented by a high voltage level and/or forward current Logic 0: Represented by a low voltage level and/or reverse current Binary numbers are conveyed individually in time between two or more digital devices. Devices have electrical limitations in drive, speed, distance, & fanout Devices may share the same wires/nodes using time based multiplexing

Review: Basic 2 Input Logic Operators
Gates and their Demorgan Equivalents Note: A Bubble implies logic inversion

Review: Basic 2 Input X-OR Operators & Gates

Review: Truth Tables, Karnaugh Maps
Grey Code

Example: Binary-7Segment Display Decoder
2 Types of Display Configurations Vcc Common Cathode LEDS Active High Common Anode LEDS Active Low Gnd

7- segment used to form digits 0-9
7 Segment Display 7- segment used to form digits 0-9

Commercial TTL BCD-to-7-segment decoder/driver driving a common-anode 7-segment LED display; 7447 segment patterns for all possible input codes.

Truth Table for Active High (Common Cathode Display Drive)
Hex Digits A-F not defined by this decoder. All Segments OFF

Truth Table Reduction Two lines can be combined if the same output is obtained but the input variable values differ in only 1 bit position. The variable for which the value differs with no effect on output is eliminated from the resulting expression. D C B D C B C B A D C B

Combining Adjacent Cells (Min Terms) Reduces Logic Implementation
a = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD Karnaugh Map Combinations AC BD 8 Min Terms …. 8 Input OR Gate Min Term = 4 Input AND Gate (plus ~4 Inversions) ~ 10 Gates ACD CD

Additional Segment Maps

Liquid-Crystal Displays
Liquid-crystal display: (a) basic arrangement; (b) applying a switching voltage between the segment and the backplane turns ON the segment. Zero voltage turns the segment OFF.

Commerical Logic devices for driving an LCD segments and full 7-segment displays

Common XOR Reduction Patterns
(Alternating Columns, Quads, and Pairs, Checkerboards)

Digital IC Technologies/Families
Bipolar: Utilizes BJT’s exclusively as switching elements. Originated by Fairchild/TI, families have included STD, L, H, LS, S, ALS, AS and F pp74xxx###P Standard Part Numbering Scheme Package Suffix (Plastic, Ceramic, DIP, SOJ, etc) Generic Device Function Number (Ex. 244 Octal Driver) Family Designation (Ex. ALS, AS, F, etc) 7 =Commercial (0-70C), 5 =Military (-55 to 125C or more) Mfg Prefix (Ex. SN = Texas Inst, DM = Fairchild, etc) Example Function/Family Package Options For Family Examples see:

Active Bipolar Logic Families
ALS Advanced Low-Power Schottky Logic AS Advanced Schottky Logic F Fast Logic LS Low-Power Schottky Logic S Schottky Logic TTL Transistor-Transistor Logic (STD)

Review: Schottky Diode
PN Junction Si Diode Similar to std diode Low Forward Voltage Drop (~0.3V) C B E Schottky Transistor Schottky Diode from Collector to Base of NPN switching transistor Vbc < Vf of Schottky Diode (~0.3V) Vce-sat (schottky) > Vce-sat (std BJT) Base-Collector Clamp prevents hard saturation Switches Faster as a result

Digital IC Technologies/Families
CMOS: Utilizes C-MOSFETs exclusively as switching elements. Originated with 4000 series family (still produced) followed with C, HC, HCT, AC, ACT, FCT, LV, LVC and many others (see list) Devices follow Bipolar part numbering scheme (except for 4000 series) Characterized by Very low input current (leakage current) Symmetric Output drive currents Device size/process scales. Industry has moved from 5um channels to less than 75nm channels in < 30 yrs Example: HC, HCT Families Function/Family Package Options

ACTIVE CMOS Logic Families
Advanced CMOS Logic (1.5 to 5.5V typ) ACT Advanced CMOS Logic AHC Advanced High-Speed CMOS (2.0 to 5.5V typ) AHCT Advanced High-Speed CMOS ALVC Advanced Low-Voltage CMOS Technology (2.3 to 3.6V typ) AUC Advanced Ultra-Low-Voltage CMOS Logic (0.8 to 2.7V typ) AUP Advanced Ultra-Low-Power CMOS Logic (0.8 to 2.7V typ) AVC Advanced Very-Low-Voltage CMOS Logic (0.8 to 2.7V typ) CB3Q Low-Voltage, High-Bandwidth Bus Switch Technology CB3T Low-Voltage, Translator Bus Switch Technology CBT Crossbar Technology CBT-C CBT with Undershoot Protection CBTLV Low-Voltage Crossbar Technology CD4000 CMOS Logic (4000 Series, 3 to 18V typ) FCT Fast CMOS Technology GTLP Gunning Transceiver Logic Plus HC High-Speed CMOS Logic (2.0 to 6.0V typ) HCT High-Speed CMOS Logic LV-A Low-Voltage CMOS Technology (2.0 to 5.5V typ) LV-AT Low-Voltage CMOS Technology LVC Low-Voltage CMOS Technology (1.6 to 3.6V typ) PCA Inter Integrated Circuit PCF SSTV Stub Series Terminated Low-Voltage Logic TVC Translation Voltage Clamp VME VME Bus Products

Other Digital IC Semiconductor Technologies
BiCMOS: Combination CMOS/BJT. Can be implemented using Si but SiGe becoming popular for mixed signal applications. Families include: HSTL, BCT, FB, ABT, ALB, LVT and others (see list) ECL/LVDS: Emitter Coupled Logic / Low Voltage Differential Signaling. Si BJT or CMOS devices that utilize differential signaling with extremely low voltage swings. Typically seen on the output from A/D conversion circuits. Switching speeds > 60Mhz. GaAs: FET based devices with extremely fast switching and delay characteristics. Ft > 10Ghz easily achievable. Costs > 20X that of fast CMOS

Active BiCMOS Logic Families
ABT Advanced BiCMOS Technology ABTE Advanced BiCMOS Technology / Enhanced Transceiver Logic ALB Advanced Low-Voltage BiCMOS (3.0 to 3.6V typ) ALVT Advanced Low-Voltage CMOS Technology (2.3 to 3.6V typ) BCT BiCMOS Technology FB Backplane Transceiver Logic GTL Gunning Transceiver Logic HSTL High-Speed Transceiver Logic JTAG JTAG Boundary Scan Support LVT Low-Voltage BiCMOS Technology (2.7V to 3.6V typ) SSTL Stub Series Terminated Logic

Other Aspects of Technology: Component Life Cycle Phases
= Mean (Max) Sales of Unit Components per Unit Time s = One Standard Deviation in Sales/Time

Life Cycle of a Component
Special Histogram of Production as Measure by Component Sales/Time (# shipped/time) Concept Assumes Component Sales follow monotonically increasing to peak, then monotonically decreasing to obsolesence Life Cycle is Measured Relative to Peak of Sales +/- 1s from Peak = Mature Product -1s to –2s from Peak = Growth Product -2s to –3s from Peak = Introductory Product +1s to +2s from Peak = Declining Product +2s to +3s from Peak = Phase Out Product +3s and higher from Peak = Obsolete Product Limitations of Product by Demographics, Geographics Cautions and Warnings Compatibilities or Incompatibilities Specific Label Applications or Misapplications Safety Rules

Logic Signal Electrical Characteristics
Finite Transition Time Zone Driver must switch voltage thru this zone within specified time or risk causing linear operation of receiver ! Typically < 1uS but varies with logic family technology

Logic Device Drive Parameters
Note: Sourced currents are always listed as a negative number by convention on data sheets

Interpreting the Data Sheet
Vih, Vil Ioh, Iol Ioh (note max Ioh) Iol (note max Iol) Iih, Iil

Device Output Structure Type 1: Totem Pole
Current Limiting Resistor (reduced in modern devices) Top Voh/Ioh Source Driver (Switch to Vcc) Bottom Vol/Iol Sink Driver (Switch to Gnd) Cross-over of Q4:Q5 – ON/OFF may result in high current spike from Vcc to Gnd Octal and larger devices rated for “Gnd Bounce” Volp. Measure of Static output disturbance when all other outputs switch simultaneously.

Device Output Structure Type 2: Open Collector/Drain
Current Limiting Resistor Removed Top Voh/Ioh Source Driver Removed Bottom Vol/Iol Sink Driver Sink Trans Q5 acts as a switch to Gnd No inherent Logic 1 voltage drive Interface in 2 ways; Pullup resistor to Vcc to establish logic 1 voltage level Switch current through load device (Ex. Relay Coil, LED, Lamp, Solenoid, etc) Note OC/OD Datasheets: May list Vce-sat for Vol, Ic max for Iol max, Vce max (off). Will NOT list Voh, Ioh values ! OC/OD Outputs will have very slow Logic 0 to 1 transition times !

OC/OD outputs may be tied together, Wire-OR
Determining Pullup Resistor Limits Maximum R - Limited by Logic 1 condition: R must supply Iih to receiver plus supply any leakage current to the driver OFF transistors. Finite Current of Io flows thru R dropping voltage. Usually use R < 100KW Minimum R - Limited by Logic 0 condition: Driver ON may cause Vol as low as 0V, Driver must sync Io from Vcc thru pullup resistor plus Iil source current from receiver. Total load current cannot exceed Driver Iol current capacity. Usually use R> 1KW

Device Output Structure Type 3: Tristate-able
Current Limiting Resistor (reduced in modern devices) Top Voh/Ioh Source Driver (Switch to Vcc) Bottom Vol/Iol Sink Driver (Switch to Gnd) Q7/Q8 used to stop base current to Q3/Q4 darlington Turn off Source Driver Q2 used for same purpose but controls Sink Driver E turns OFF Q4 and Q5 simultaneously

Interpreting the Data Sheet
Vcc Supply Voltage Range Normal Input Specs apply to Enable Input (G) Off State Output Leakage Currents Logic Level Dependent Icc Max Supply Current Note: Occurs when outputs in Hi Z

Multiplexing Drivers for Bus Operation
Active Driver must provide Iih/Iil currents to ALL receivers plus all the OFF state leakage currents of the other inactive Drivers Must NOT have 2 or more Drivers Active simultaneously. Time Division multiplexing (timing) analysis critical to long term reliabililty of devices

Standard vs Schmitt Trigger Input Functions
Single Input Threshold Vth, Eliminates Undefined Transition Zone Input should also have minimum “hysteresis” to provide noise immunity As Vin increases thru Vth, Vth decreases by DV (Vhyst) As Vin decreases thru Vth, Vth increases by DV (Vhyst) Vth is typically 1.0 – 2.0 V, Vhyst should be > 200mV Schmitt Trigger should always follow OC/OD outputs or other slow rise or fall time signals (Ex. Optocoupler Outputs, RC Reset Circuits, etc )

Basic Combinatorial Timing Parameters
TpHL(TpLH): Propagation Delay from High to Low (Low to High) Logic Level Usually measured between the 10% and 90% total voltage transition points. Tpd or Tp: Propagation Delay usually stated as worst case of TpHL and TpLH. Tott or Tout: Output Transition Time. For many families (HC, HCT, etc), gate delays are stated with separate specifications for logical output value generation (Tpd) plus physical output voltage transition (Tott). Need to sum these for total prop delay !! TpzH(TpzL): Propagation Delay from High Impedance to High (Low) Logic Level TpHz(TpLz): Propagation Delay from High (Low) Logic Level to High Impedance

Review of Medium Scale Integration (MSI) Logic Circuits
Common digital system tasks are commercially available as MSI logic devices in many different TTL and CMOS families Functions such as decoding/encoding, multiplexing, demultiplexing, comparison, arithmetic, code converting, and data busing

General decoder diagram
Decoders A decoder accepts a set of inputs that represents a binary number and activates only the output that corresponds to that input number. General decoder diagram

3-line-to-8-line (1-of-8) decoder, Active High

Typically decoders have ENABLE inputs used to control operation
All ENABLE inputs must be satisfied for an output to be active

Enables can be used to cascade into larger decoders Example: Four 74ALS138s forming a 1-of-32 decoder

The 7442 style BCD-to-decimal decoder
One output is active based on the Binary Coded Decimal input value

Counter/decoder combination can be used to provide timing and sequencing operations

Encoders A encoder is a decoder in reverse, that is, it accepts a single active input from an input set, and delivers an N-Bit code corresponding to which input was active. General encoder diagram.

Logic circuit for an octal-to-binary (8-to-3) active low encoder.
For proper operation, only one input should be active at one time.

A priority encoder has special logic to ensure that when two or more inputs are activated, the output code will correspond to the highest-numbered input. 74147 style decimal-to-BCD priority encoder.

Priority encoder application as a switch encoder.
NOTE: Switches must be debounced (not shown)!

Priority Encoder Application: Keyboard entry of 3-digit number into storage registers with proper debounce and clear function

Functional diagram of a digital multiplexer (MUX)
Multiplexers A multiplexer (MUX) is a circuit that selects 1 input from a set based on the selection code input. Functional diagram of a digital multiplexer (MUX)

Simple Two-input multiplexer gate level design

Four-input multiplexer

74151 Style 8-input multiplexer with complementary output

Two 74HC151s combined to form a 16-input multiplexer.

74157 Style Quad Two-Input MUX

Data Routing MUX Application
System for displaying two multidigit BCD counters one at a time.

Parallel-to-Serial MUX Application
Parallel-to-serial converter; waveforms for X7X6X5X4X3X2X1X0 = JK’s used as Toggle Flip-flop Ripple Counter

MUX/Decoder Application
Operation Sequencing MUX/Decoder Application Seven-step control sequence Starts by filling tank1, when full it toggles to fill tank 2, etc.

Logic Function Generation MUX Application
MUX used to implement a canonical SOP logic function

Review of Medium Scale Integration (MSI) Logic Circuits
Common digital system tasks are commercially available as MSI logic devices in many different TTL and CMOS families Functions such as decoding/encoding, multiplexing, demultiplexing, comparison, arithmetic, code converting, and data busing

De-Multiplexers A Demultiplexer (DEMUX) takes a single input & distributes it over several outputs.

1-line-to-8-line demux

74138 style decoder can function as a demultiplexer with E1 used as the data input. Typical waveforms shown for a select code of A2 A 1 A 0 = 000 show that O0 is identical to the data input I on E1.

Security monitoring system MUX/DEMUX Application

Synchronous data transmission system

One 16 bit transmission cycle

74HC85 4-bit magnitude comparator
Comparators A Comparator takes two inputs numbers and yields a result to indicate <, =, > 74HC85 4-bit magnitude comparator

74HC85 wired as a single 4-bit comparator
Two 74HC85s cascaded to perform an 8-bit comparison

Magnitude comparator used in a simple controller application
Set Point Magnitude comparator used in a simple controller application

Basic idea of a two-digit BCD(hex)-to-binary converter.
Code Converters A code converter changes data presented in one type of binary code to another type of binary code Basic idea of a two-digit BCD(hex)-to-binary converter.

BCD-to-binary Conversion
Compute the binary sum of the binary equivalents of all bits in the BCD representation that are 1s. Example (BCD) = (2) (10) (40) = (52)

BCD-to-binary converter with 74HC83 4-bit parallel adders.

Data Bus Interface These circuits include tristate-able buffers and latches Time Division Multiplexing 3 different devices can transmit 8-bit data over an 8-line data bus to a µ-processor; only one device at a time is enabled so that bus contention is avoided.

Truth table and logic diagram for the 74ALS173 tristate register

Tristate registers connected to a data bus.

Signal activity during the transfer of the data 1011 from register A to register C

Simplified way to show signal activity on data bus lines.

Simplified representation of bus arrangement.

Bundle method for simplified representation of data bus connections
Bundle method for simplified representation of data bus connections. The “/8” denotes an 8 bit data bus.

Basic Combinatorial Timing Parameters
TpHL(TpLH): Propagation Delay from High to Low (Low to High) Logic Level Usually measured between the 10% and 90% total voltage transition points. Tpd or Tp: Propagation Delay usually stated as worst case of TpHL and TpLH. Tott or Tout: Output Transition Time. For many families (HC, HCT, etc), gate delays are stated with separate specifications for logical output value generation (Tpd) plus physical output voltage transition (Tott). Need to sum these for total prop delay !! TpzH(TpzL): Propagation Delay from High Impedance to High (Low) Logic Level TpHz(TpLz): Propagation Delay from High (Low) Logic Level to High Impedance

Review: Sequential Logic Building Blocks

Basic Sequential Timing Parameters
Tsu: Setup Time, Data must be stable this min time prior to CLK edge Th: Hold Time, Data must remain stable this min time after CLK edge Td: CLK to Q or Output Delay, Time for Data Propagation to Q Tset/Treset: Control Input to Output Change delay Tw: Min Control Input Width (active low) Tclk: Min Logic 1 (high) + Min Logic 0 (low) time for CLK signal. May be stated separately or as Max Frequency (Fmax). Note: Tclk – (Tsu + Th) = Worst Case usable time to change data.

Missing Tsu or Th ….. Possible Results
FF latches the data normally as if Tsu and Th were satisfied FF misses the intended data but clocks data at next opportunity FF misses the intended data completely, lost FF latches the correct data but with extended Td FF latches the correct data but exhibits many output transitions FF misses the intended data and exhibits many output transitions FF misses the data and causes other spurious affects Metastable Behaviour

Characterizing Metastable Likelyhood
Fd can be estimated using a worst case assumption based on clock frequency To and t: Technology (family) specific, usually published in a separate metastability characterization report from the Mfg. Tw: Walkout time allowable within a given application (1/Fc – Tsu – Th) in many cases

Examples: To & t, Metastability Constants
Worst Case Metastability Analysis Clearly this device is not well suited for the intended application ! Metastability MTBFs Need to Be >> 100 years

Improvement Using Better (faster) Device
Using Metastable hardened Device Enormous difference in Metastability Performance of Device Technologies

Same Example Using Multistage Synchronization
Synchronization also used to improve “System” Immunity to Metastability Same Example Using Multistage Synchronization Synchronization Causes System Response Time Penalty

Simple Data Transfer Example: 10Mhz CPU Memory Read Cycle
Using Timing Parameters, Timing Analysis Simple Data Transfer Example: 10Mhz CPU Memory Read Cycle Timing Diagram notation uses binary signals (CLK, Controls) and bussed signals (Address and Data) CPU Generates System Timing relative to a master CLK. Sends out Address and Control Signals, Expects Data in T3 Basic Memory Read Cycle is 3 CLKs long but can be extended using the DTACK (Wait State) signal CPU Samples DTACK in T2, if non-active, T2 is repeated (Wait State); if active, T2 ends followed by T3 CPU Expects Data at midpoint of T3, Note Data Setup Time and Data Hold Time Requirements Timing Analysis Determines if Target Memory Device is Fast Enough or if it requires Wait States

Using the “Target” device as viewpoint
Timing Analysis Using the “Target” device as viewpoint Read-Only-Memory is Target Device Target Device Timing Parameters Target has 3 basic input signals Address: Specifies 1 storage location in device to be read CE (active low): Disables entire device including selector system and output driver OE (active low): Disable output driver only

Timing Analysis… To Get the Data

Timing Analysis… To Get the Data
Possible Improvements: Use Faster FPGA with lower Tpd Exercise 1 wait state using DTACK

Timing Analysis… To Finish the Cycle
Can Memory disable output drive in time?

General State Machine Architecture
Inputs Next State Comb Logic State Variables (FF) Array Output Decoder Logic Possible Outputs Outputs Present State Info CLK Mealy Architecture Requires Output Decoder Logic Block

Review: State Machine Design
Typical “Bubble Diagram” Important to “Account” for ALL possible states

2 Classes of State Machines:
Moore Architecture Mealy Architecture Mealy type may utilize fewer FFs, more compact Moore type offers possibility for state variables to be outputs (no glitch) Both types can be implemented with either D or JK type FFs. D used in PLDs

General State Machine Architecture
Inputs Next State Comb Logic State Variables (FF) Array Output Decoder Logic Possible Outputs Outputs Present State Info CLK Mealy Architecture Requires Output Decoder Logic Block

Example 1 Design a state machine which is capable of detecting an input signal and adding a 2 clock delay on the trailing (falling) edge of the input. All paths (arrows) which terminate in a logic 1 for Qa, Qb or OUT generate a MIN term in their respective K-Map

Schematic Implementation
IN Qa OUT Qb CLK Set & Reset inputs unused, terminated with pullup resistors to logic 1

Example 2 Design a state machine which arbitrates between 2 CPUs sharing a common memory system. Each CPU has a separate request and grant signal. In the event of simultaneous request, give preference to CPU A. Grant 2 Grant 1 Q2Q1 R2R1 R1 Q1 R2 Q2 Preference is given to CPU A with don’t care condition for R2 when R1 is active Moore Implementation Allow state variables to be used directly as outputs

2 Maps for Q2Q1 D-Input Logic
R2R1 Q2Q1 Q1= R1* Q2 Grant 2 Grant 1 Map for Q1 R2R1 Q2Q1 Q2Q1 Q2= (R2* Q2* Q1) + (R2* R1* Q1) R2R1 R1 Q1 Map for Q2 R2 Q2 CLK

Machine Partitions

Equivalence Partition

State Reduction

Symmetric Logic Functions

Properties of Symmetric Logic Functions

Programmable Logic PLD: Programmable Logic Device
Typically has defined routing and deterministic function delays. Smaller and less complex than other forms FPGA: Field Programmable Gate Array Routing and ultimate function delay is part of the design process Complex array of central logic block functions and peripheral I/O functions amidst block-block routing resource Embedded functions available such as CPU’s (Ex. Altera NIOS)

Basic Sum-of-Products PLD architecture

PLD Connection Nomenclature

Comparison of PROM Architecture (Fixed AND, Programmable OR)
Blank PROM Architecture Programmed PROM Architecture Comparison of PROM Architecture (Fixed AND, Programmable OR)

Simple PLD Architecture (Programmable AND, Fixed OR)

Routing Resource Simple FPGA Architecture (Central Logic Block Array, Peripheral I/O Blocks)

Example: Xilinx Virtex II

Inside the Conf Logic Block
Virtex II Series Facts: 1: Each FPGA capable of having CLB 2: Each CLB has 4 Slices 3: Each Slice - 2 Functional Generators - Arithmetic Login Block - Large Multiplexers - Fast carry look ahead chain - Horizontal chain of OR gates 4: Functioning at 420MHz 5: 3Mb RAM 6: 12 Digital Clock Managers

Different HDL Options VHDL Verilog
ADA like syntex and lots of redundancy (can provide more flexibility) Design is composed of entities and are different for different architectures. Harder to learn and complex. Much stronger test bench design. Verilog C like syntex. Built-in types and logic representations. Design is composed of modules (functions). Much easier to learn. More cumbersome test bench design.

VHDL Basics Very High Speed Integrated Circuit (VHSIC) Hardware Description Language IEEE Std (VHDL87 & VHDL93) Required by DOD for all ASIC designs Designs are generally captured in modules which have 2 parts; Entity Description - Blackbox description including all inputs and outputs Architecture Description - Describes the internal signals and overall relationship of entity inputs to outputs Best learned by studying examples and not formal language rules

Example - 8 bit comparator VHDL keywords and library options are in bold Comments follow “--”
z 8 y library ieee; Use IEEE standard library use ieee.std_logic_1164.all; Use IEEE standard data type entity jeff is entity description, black box name is “jeff” port (x, y: in std_logic_vector (7 downto 0); -- 4 input pin description, 2 eight bit variables, x & y z: out std_logic); output pin z, single bit end jeff; end of entity description architecture john of jeff is separate name for architecture is “john” begin keyword z <= ‘1’ when x = y else ‘0’; z is “assigned” the value 1 if x = y, else z = 0 end john; end of architecture

Example - 4:1 Multiplexer VHDL keywords and library options are in bold Comments follow “--”
mux0 mux3 zout mux1 mux2 ssel 2

library ieee; Use IEEE standard library use ieee.std_logic_1164.all; Use IEEE standard data type entity jeffs_mux is port entity description, black box name is “jeffs_mux” (mux0, mux1, mux2, mux3: in std_logic; -- 4 input pin description, Four input signals, mux0-3 ssel: in std_logic_vector (1 downto 0); -- 5 input pin description, 2 bit selection signal “ssel” zout: out std_logic); output pin zout, single bit end jeffs_mux; end of entity description architecture jeffs_mux of jeffs_mux is -- 8 can have same name for entity and architectures begin keyword with ssel select zout <= VHDL construct called “with, select, when” mux0 when “00”, select mux0 with ssel = 00 mux0 when “01”, select mux1 with ssel = 01 mux0 when “10”, select mux2 with ssel = 10 mux0 when others; select mux3 with ssel = 11 or all other possible end jeffs_mux; end of architecture description

mux0 mux3 zout mux1 mux2 ssel 2 library ieee; Use IEEE standard library use ieee.std_logic_1164.all; Use IEEE standard data type entity jeffs_mux is port entity description, black box name is “jeffs_mux” (mux0, mux1, mux2, mux3: in std_logic; -- 4 input pin description, Four input signals, mux0-3 ssel: in std_logic_vector (1 downto 0); -- 5 input pin description, 2 bit selection signal “ssel” zout: out std_logic); output pin zout, single bit end jeffs_mux; end of entity description architecture jeffs_mux of jeffs_mux is -- 8 can have same name for entity and architectures begin keyword with ssel select zout <= VHDL construct called “with, select, when” mux0 when “00”, select mux0 with ssel = 00 mux0 when “01”, select mux1 with ssel = 01 mux0 when “10”, select mux2 with ssel = 10 mux0 when others; select mux3 with ssel = 11 or all other possible end jeffs_mux; end of architecture description Single quotes used when describing the value assignment to a std_logic type variable Double quotes used when describing the value assignment to a std_logic_vector type variable The IEEE std_logic type specifies 9 (nine) possible values including ‘0’, ‘1’, ‘Z’ (high impedance), ‘-’ (don’t care) among others (not discussed in this basic intro) Each bit therefore has 9 possible values, A 2 “bit” variable actually has 29 = 81 possible states “with-select-when” construct useful only if one signal is assigned based on values of input. Another construct called “case-when” inside of a process statement can be used if more than one signal needs assignment.

Example - 4 bit D type latch VHDL keywords and library options are in bold Comments follow “--”
q 4 data aclk reset D Latch

library ieee; Use IEEE standard library use ieee.std_logic_1164.all; Use IEEE standard data type entity jeffs_flop is port entity description, black box name is “jeffs_flop” (aclk, reset: in std_logic; input pin description, clock and reset pins data: in std_logic_vector (3 downto 0); -- 5 input pin description, 4 D type inputs q: out std_logic_vector (3 downto 0)); -- 6 output pin description, 4 latch outputs, q3 - q0 end jeffs_flop; end of entity description architecture jeffs_flop of jeffs_flop is -- 8 can have same name for entity and architectures begin keyword p1: process (aclk, reset) begin VHDL process construct called “if-then” if reset = ‘0’ then q <= (others => ‘0’); q is assigned ‘0’ when reset = 0 if rising_edge (aclk) then q <= data; q is assigned ‘data” when, reset = 1 and clocked end if; end of “if” cases end process; end of VHDL case-when end jeffs_flop; end of architecture description

q 4 data aclk reset D Latch library ieee; Use IEEE standard library use ieee.std_logic_1164.all; Use IEEE standard data type entity jeffs_flop is port entity description, black box name is “jeffs_flop” (aclk, reset: in std_logic; input pin description, clock and reset pins data: in std_logic_vector (3 downto 0); -- 5 input pin description, 4 D type inputs q: out std_logic_vector (3 downto 0)); -- 6 output pin description, 4 latch outputs, q3 - q0 end jeffs_flop; end of entity description architecture jeffs_flop of jeffs_flop is -- 8 can have same name for entity and architectures begin keyword p1: process (aclk, reset) begin VHDL process construct called “if-then” if reset = ‘0’ then q <= (others => ‘0’); q is assigned ‘0’ when reset = 0 if rising_edge (aclk) then q <= data; q is assigned ‘data” when, reset = 1 and clocked end if; end of “if” cases end process; end of VHDL case-when end jeffs_flop; end of architecture description VHDL Process construct used to embody an algorithm, starts with a label, “p1” Process contains “sensitivity” list which contains all signals that can possible cause the value of output q to change The process can be thought of an algorithm although the implication is that all cases are evaluated concurrently because the implementation is in hardware and not software! The signal “data” is not in the sensitivity list because it can change at any time and does directly effect the output, q

Example - State Machine Bus Arbitor
req0 * /req1 ack0 gnt0=0 gnt1=1 ack1 gnt0=1 gnt1=0 /req0 * req1 /req0 /req0 * req1 req0 * req1 req0 * /req1 req0 * req1 /req1 idle0 gnt0=1 gnt1=1 idle1 gnt0=1 gnt1=1

Example - State Construct VHDL keywords and library options are in bold Comments follow “--”
library ieee; Use IEEE standard library use ieee.std_logic_1164.all; Use IEEE standard data type entity state_example is port entity description, name is “state_example” (clk, rst, req0, req1: in std_logic; input pin description, clock, reset & request pins gnt0, gnt1: out std_logic); outputs (not necessarily the state variables) end state_example; end of entity description -- 7 architecture jeff of state_example is architecture name is “jeff” type state_type is (ack0, ack1, idle0, idle1); -- 9 type declaration (list of state names) signal state, next_state: state_type; two types of signals, current state & next state begin keyword transitions: process (state, req0, req1) begin VHDL process construct called “case-when” case state is when ack0 => gnt0 <= ‘0’; gnt1 <= ‘1’; When in state ack0, gnt0 = 0 & gnt = 1 if req0 = ‘1’ and req1 = ‘0’ then next_state <= ack1; active low req1 acknowledged elsif (req0 and req1) = ‘1’ then next_state <= idle0; no request, go back to idle0 else next_state <= ack0; if no change in inputs, loop here end if;

Example cont’d - State Construct VHDL keywords and library options are in bold Comments follow “--”
when ack1 => gnt0 <= ‘1’; gnt1 <= ‘0’; When in state ack1, gnt0 = 1 & gnt = 0 if req0 = ‘0’ and req1 = ‘1’ then next_state <= ack0; active low req0 acknowledged elsif (req0 and req1) = ‘1’ then next_state <= idle1; no request, go back to idle1 else next_state <= ack1; if no change in inputs, loop here end if; when idle0 => gnt0 <= ‘1’; gnt1 <= ‘1’; When in state idle1, gnt0 = 1 & gnt = 1 if req1 = ‘0’ then next_state <= ack1; active low req1 acknowledged** elsif (req0 = ‘0’ and req1 = ‘1’) then next_state <= ack0; active low req0 acknowledged else next_state <= idle0; if no change in inputs, loop here end if; when idle1 => gnt0 <= ‘1’; gnt1 <= ‘1’; When in state idle1, gnt0 = 1 & gnt = 1 if req0 = ‘0’ then next_state <= ack0; active low req0 acknowledged** elsif (req0 = ‘1’ and req1 = ‘0’) then next_state <= ack1; active low req1 acknowledged else next_state <= idle1; if no change in inputs, loop here end if; end case; End Case construct end process; Process ending statement

Example cont’d - State Construct VHDL keywords and library options are in bold Comments follow “--”
operation: process (rst, clk) begin define 2nd process “operation” if rst = ‘1’ then state <= idle0; when, rst = 1 then state = idle0 (asynchrounous) elseif rising_edge (clk) then state <= next_state define basic state >> next_state operation end if; end of “if” cases end process; end of process “operation” end state_example; end of architecture description New data type (called state_type) is used in this example (enumeration type) to give names to the states. Process contains “sensitivity” list which contains all signals that can possible cause the value of output state to change The process “operation” describes the basic flip-flop operation in a state machine with a clock. The process “transitions” describes the basic state transition logic depicted in the bubble chart.

Clocks and Timing Analysis
Most large scale ASICs and systems built with these ASICs have several synchronous clock domains connected by asynchronous communication channels - Flexibility due to different rate clocks on same chip. - Different polarities also available. - Timing analysis plays a big role in analysis and design verification

Memory Technology Memory Terminology General Memory Operation
CPU-Memory Connection ROM ROM Architecture Types of ROM Flash Memory ROM Applications Semiconductor RAM RAM Architectures SRAM DRAM DRAM Structure and Operation DRAM R/W Cycles DRAM Refreshing DRAM Technology Expanding Word Size and Capacity Special Memory Functions Troubleshooting RAM Systems Testing ROM

Memory Terminology Capacity: Density of Device - 4096 20-bit words
= 81,920 bits = 4096*20 = 4K*20 - 1 M or 1 meg = 220 - 1 G or 1 giga = 230 Address: Binary numerical selection input Control: Various enable inputs for entire memory device or for output buffer control Read Operation: fetch data from memory Write Operation: store data in memory

Access Time: Time from first input in to data out
Volatile Memory: Any type of memory that looses data when power is compromised RAM: Random Access Memory is memory that can be read or written in normal operation. Access time is the same for any address in memory ROM: Read Only Memory is memory that can be programmed but is generally not written to in normal operation. Static RAM (SRAM): RAM which uses internal flipflops to store data and no dynamic refresh operation is required to store the data. Dynamic RAM (DRAM): Stored data on internal capacitors will only remain for a short period, typically ~2-5mSec, before it must be read and re-written in a “refresh” operation.

Typical Memory Read/Write Operation
Apply the address that is being accessed for the operation Assert read or write control as well as enables If the cycle is a write cycle, assert the input data to be stored in memory during the write operation If the cycle is a read cycle, latch the output data coming from memory during the read operation Enable (or Disable) the memory so that it will (or will not) respond to the address and r/w command.

FIG 12-3 (a) Diagram of a 32  4 memory; (b) virtual arrangement of memory cells into 32 four-bit words.

Fig (a) Logic symbol for 27C64 Erasable PROM; (b) typical EPROM package showing ultraviolet window; (c) 27C64 operating modes.

MROMs are programmed during manufacturing process.
Summary MROMs are programmed during manufacturing process. PROMs are programmed one time by the user. EPROMs can be erased using UV light. EEPROMs and flash memory are electrically erasable and can have their contents altered after programming. Data are retained in a RAM device only as long as power is applied. SRAM uses storage elements that are basically latch circuits. DRAM uses capacitors to store data by charging or discharging them.

General Memory Organization
Contents General Memory Organization

Fig 12-4 (a) writing the data word 0100 into memory location 00011; (b) reading the data word 1101 from memory location

12-3 CPU-Memory Connections
Write Operation 1. CPU supplies the binary address of the location 2. CPU places the data on the data bus line 3. CPU activates the appropriate control signals 4. Memory decodes the binary address 5. Data are transferred to the selected location Read Operation 2. CPU activates the appropriate control signals 3. Memory decodes the binary address 4. Memory places data onto the data bus

Fig 12-5 Three groups of lines connect the main memory ICs to CPU.

12-4 ROM

12-5 ROM Architecture

12-6 ROM Timing

Fig 12-9 MOS MROM (Mask-programmed ROM)
12-7 Types of ROMs Fig 12-9 MOS MROM (Mask-programmed ROM)

A14 Fig Logic symbol for TMS47256 ROM made using NMOS/CMOS technology. (MROM)

Fig Programmable ROMs (PROMs) use fusible links that can be selectively blown open by the user to program a logic 0 into a cell. PROMs = one-time programmable ROMs

Fig (a) Symbol for the 2864 Electrically EPROM; (b) operating modes; (c) timing for the write operation.

The disks are manufactured with a highly reflective surface
CD ROM The disks are manufactured with a highly reflective surface Digital data are stored on the disk one bit at a time by burning or not burning a pit into the reflective coating

12-8 Flash Memory

Fig 12-15 (a) Logic symbol for the 28F256A flash memory chip; (b) control inputs

Fig 12-16 Functional diagram of the 28F256A flash memory chip
Fig Functional diagram of the 28F256A flash memory chip. (Courtesy of Intel Corporation.)

Firmware: OS programs and language interpreters
12-9 ROM Applications Firmware: OS programs and language interpreters Bootstrap Memory: when the computer is powered on, it will execute the instructions that are in bootstrap program Data Tables Data Converter Function Generator Auxiliary Storage

Fig 12-17 Function generator using a ROM and a DAC

Fig 12-18 The ML2035 programmable sine-wave generator (Courtesy of MicroLinear)

Example Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and generates an output binary number equal to the square of the input number.

Major disadvantage: volatile
12-10 Semiconductor RAM When the term RAM is used with semiconductor memories, it is usually taken to mean read/write memory (RWM) as opposed to ROM. Major disadvantage: volatile Main advantage: can be written into and read from rapidly with equal ease

Fig 12-19 Internal organization of a 64  4 RAM
12-11 RAM Architecture Fig Internal organization of a 64  4 RAM

Fig 12-20 Logic symbols for (a) the 2147H RAM chip; (b) the MCM6206C RAM.

SRAM can store data as long as power is applied to the chip
12-12 Static RAM SRAM can store data as long as power is applied to the chip Fig Typical timing for static RAM: (a) read cycle; (b) write cycle

Fig 12-23 Symbol and mode table for the CMOS MCM6264C

Fig 12-24 JEDEC standard memory packaging

Store 1s and 0s as charges on a small MOS capacitor
12-13 Dynamic RAM (DRAM) Store 1s and 0s as charges on a small MOS capacitor Because of the tendency for these charges to leak off after period of time, DRAMs require periodic recharging of the memory cells (refreshing) Larger capacities and lower power consumption

Fig 12-25 Cell arrangement in a 16K  1 DRAM
12-14 DRAM Structure & Operation Fig Cell arrangement in a 16K  1 DRAM

Fig 12-26 Symbolic representation of a dynamic memory cell
Fig Symbolic representation of a dynamic memory cell. During a WRITE operation, semiconductor switches SW1 and SW2 are closed. During a read operation, all switches are closed except SW1.

Fig (a) Simplified architecture of the TMS M  1 DRAM; (b) RAS/CAS timing. (Courtesy of Texas Instruments.)

Fig (a) CPU address bus driving ROM or SRAM memory; (b) CPU addresses driving a multiplexer that is used to multiplex the CPU address lines into the DRAM

Fig 12-29 Timing required for address multiplexing

12-15 DRAM R/W Cycles Fig Signal activity for a read operation on a dynamic RAM. The R/W input (not shown) is assumed to be HIGH.

Fig 12-31 Signal activity for a write operation on a dynamic RAM.

12-16 DRAM Refreshing Fig The RAS-only refresh method uses only the RAS signal to load the row address into the DRAM to refresh all cells in that row. The RAS-only refresh can be used to perform a burst refresh as shown. A refresh counter supplies the sequential row addresses from row 0 to row 1023 (for a 4M  1 DRAM).

Fig TMS44100 refresh modes

FPM (Fast Page Mode) DRAM EDO (Extended Data Output) DRAM
12-17 DRAM Technology Memory modules FPM (Fast Page Mode) DRAM EDO (Extended Data Output) DRAM SDRAM (Synchronous DRAM) DDRSDRAM (Double Data Rate SDRAM) SLDRAM (Synchronous Link DRAM) DRDRAM (Direct Rambus DRAM)

Fig 12-34 Combining two 16  4 RAMs for a 16  8 module.
12-18 Expanding Word Size and Capacity Fig Combining two 16  4 RAMs for a 16  8 module.

Fig 12-35 Eight 2125A 1 K  1 chips arranged as a 1K  8 memory

Fig 12-36 Combining two 16  4 chips for a 32  4 memory

Fig 12-37 Four 2K  8 PROMs arranged to form 8K  8

Fig 12-38 A system with incomplete address decoding

Fig 12-39 A memory map of a digital dashboard system

Fig 12-40 Eight 4M  1 DRAM chips combined to form a 4M  8 memory module

12-19 Special Memory Functions
Power-Down Storage Cache Memory FIFO Circular Buffers

Fig In FIFO, data values are read out of memory (b) in the same order that they were written into memory (a)

Fig 12-42 4K  8 RAM memory connected to a CPU
12-20 Troubleshooting RAM Systems Fig K  8 RAM memory connected to a CPU

Reference ROM chip approach Checksum
12-21 Testing ROM Socket approach Reference ROM chip approach Checksum

Fig Checksum method for an 8  8 ROM: (a) ROM with correct data; (b) ROM with error in its data

Digital Design Jeff Kautzer Univ Wis Milw.

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