1. Operational Amplifiers1

2. A useful integrated circuit implementation of an almost idealized amplifier
Figure 2.1 Circuit symbol for the op amp.
Microelectronic Circuits - Fifth Edition Sedra/Smith

3. Often Vcc = Vee for balance with respect to ground (important as it maintains symmetry when overdriven)
Figure 2.2 The op amp shown connected to dc power supplies.
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4. Infinite input impedance (no source loading)
Idealized OpAmp:
Infinite input impedance (no source loading)
Extremely high gain (A – watch out for oscillation)
Zero output impedance (can deliver power to a load)
Differential input (high degree of “common mode” rejection)
Sometimes differential output
Figure 2.3 Equivalent circuit of the ideal op amp.
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5. - input + input Vid = v2 - v1 ; vicm = (v2 + v1 )/2
Figure 2.4 Representation of the signal sources v1 and v2 in terms of their differential and common-mode components.
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6. v3 = GmR(v2-v1) ; Gm = 10 mA/V, R = 10k,  = 100 ; A = 104 V/V or 80 dB ; Input Impedance? Output Impedance?
Figure E2.3
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7. Vout = -Vin*(R2/R1) ; hint: v1 = 0 since any voltage differential means vo is large and i1 = 0 so a simple voltage divider yields the result (next slides)
Figure 2.5 The inverting closed-loop configuration.
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8. Why is the negative input voltage equal to the positive input voltage (0, “virtual ground”)?
Figure 2.6 Analysis of the inverting configuration. The circled numbers indicate the order of the analysis steps.
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9. Finite gain: G = -( R2/R1 )/(1 + (1 + R2/R1 )/A ); hint: v1 = -vo / A
Figure 2.7 Analysis of the inverting configuration taking into account the finite open-loop gain of the op amp.
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10. v1=0, i2=i1, node eq. at x, A = -(R2/R1)*( 1 + R4/R2 + R4/R3 )
Figure 2.8 Circuit for Example 2.2. The circled numbers indicate the sequence of the steps in the analysis.
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11. Figure 2. 9 A current amplifier based on the circuit of Fig. 2. 8
Figure 2.9 A current amplifier based on the circuit of Fig The amplifier delivers its output current to R4. It has a current gain of (1 + R2/R3), a zero input resistance, and an infinite output resistance. The load (R4), however, must be floating (i.e., neither of its two terminals can be connected to ground).
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12. TransResistance Amplifier Ex2
TransResistance Amplifier Ex2.5; Ri=0 (vo=v1=0), Rm=-10k, Ro=0, vo=-5V; see table 1.1 for the definition of TransResistance
Figure E2.5
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13. Ex 2.6: Vo doesn’t change with load – low output impedance
Figure E2.6
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14. We have an adder! (use superposition – assumes linearity!)
Figure A weighted summer.
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15. sedr42021_0211.jpg
Figure A weighted summer capable of implementing summing coefficients of both signs.
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16. Now v1=vi ; A = 1 + R2/R1 ; see next slide
Figure The noninverting configuration.
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17. Note the “1+”
Figure Analysis of the noninverting circuit. The sequence of the steps in the analysis is indicated by the circled numbers.
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18. A simple and useful Op Amp circuit: can be used as a power amplifier
can be used to isolate stages in a filter – allows an easy design methodology
Figure (a) The unity-gain buffer or follower amplifier. (b) Its equivalent circuit model.
Microelectronic Circuits - Fifth Edition Sedra/Smith

19. Voltage divider on the positive input; A = 1+9 = 10; v+=0. 6v1+0
Voltage divider on the positive input; A = 1+9 = 10; v+=0.6v1+0.4v2 so vo=6v1+4v2
Figure E2.9
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20. See Ex 2.13
Figure E2.13
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21. As in Figure 2.4
Figure Representing the input signals to a differential amplifier in terms of their differential and common-mode components.
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22. See next two slides Figure 2.16 A difference amplifier.
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23. Again assuming linearity.
Figure Application of superposition to the analysis of the circuit of Fig
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24. If R3=R1 and R4=R2; Ad=R2/R1 then Acm=0
Figure Analysis of the difference amplifier to determine its common-mode gain Acm ; vO / vIcm.
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25. But the input impedance is low! 2*R1 – not good
Figure Finding the input resistance of the difference amplifier for the case R3 = R1 and R4 = R2.
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26. Requires good resistor matching available in IC’s with careful design
Common mode rejection in 2nd stage. First stage provides high input impedance.
Requires good resistor matching
available in IC’s with careful design
Resistor value set by resistivity*length/(width*depth)
Resistivity is variable chip to chip and with temperature, but consistent in each chip if temperature differences are minimized
Length and width are accurately set by the “mask”
Depth is variable chip to chip (diffusion) but again consistent on a particular chip
Figure A popular circuit for an instrumentation amplifier: (a) Initial approach to the circuit; (b) The circuit in (a) with the connection between node X and ground removed and the two resistors R1 and R1 lumped together. This simple wiring change dramatically improves performance; (c) Analysis of the circuit in‘ (b) assuming ideal op amps.
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27. Watch out for “pot” noise, modern circuits use a voltage controlled resistor (FET).
Figure To make the gain of the circuit in Fig. 2.20(b) variable, 2R1 is implemented as the series combination of a fixed resistor R1f and a variable resistor R1v. Resistor R1f ensures that the maximum available gain is limited.
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28. As long as the open loop gain is high compared to the feedback-determined gain, not a problem. See next slide
Amplifier roll-off needs to be controlled to maintain stability (ch.8 – not in the first course).
Figure Open-loop gain of a typical general-purpose internally compensated op amp.
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29. Flat response till the open-loop gain drops to near the ideal closed loop gain.
Figure Frequency response of an amplifier with a nominal gain of +10 V/V.
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30. Same here
Figure Frequency response of an amplifier with a nominal gain of –10 V/V.
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31. The output current limit restricts you to higher load impedances
You want symmetrical clipping (only generate odd harmonics) so music sounds better
The output current limit restricts you to higher load impedances
Figure (a) A noninverting amplifier with a nominal gain of 10 V/V designed using an op amp that saturates at ±13-V output voltage and has ±20-mA output current limits. (b) When the input sine wave has a peak of 1.5 V, the output is clipped off at ±13 V.
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32. This can also cause signal distortion
The slew rate is the fastest rate of change that the output can deliver.
This can also cause signal distortion
Figure (a) Unity-gain follower. (b) Input step waveform. (c) Linearly rising output waveform obtained when the amplifier is slew-rate limited. (d) Exponentially rising output waveform obtained when V is sufficiently small so that the initial slope (vtV) is smaller than or equal to SR.
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33. sedr42021_0227.jpg
Figure Effect of slew-rate limiting on output sinusoidal waveforms.
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34. We need to compensate for this offset in real circuits.
Real OpAmps: the devil is in the details. Here the text discussed the “offset voltage” (referred to the input)
We need to compensate for this offset in real circuits.
Figure Circuit model for an op amp with input offset voltage VOS.
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35. Ex 2.23
Figure E2.23 Transfer characteristic of an op amp with VOS = 5 mV.
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36. The offset gets amplified!
Figure Evaluating the output dc offset voltage due to VOS in a closed-loop amplifier.
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37. This is a manual operation, not great, but I’ve used it.
Figure The output dc offset voltage of an op amp can be trimmed to zero by connecting a potentiometer to the two offset-nulling terminals. The wiper of the potentiometer is connected to the negative supply of the op amp.
Microelectronic Circuits - Fifth Edition Sedra/Smith

38. The DC offset gain is 2, the signal (AC) gain is –R2/R1
The offset causes a DC offset in the output and asymmetrical clipping.
Figure (a) A capacitively coupled inverting amplifier, and (b) the equivalent circuit for determining its dc output offset voltage VO.
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39. Input bias current offset – another imperfection
Figure The op-amp input bias currents represented by two current sources IB1 and IB2.
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40. The input resistor translates the offset current into an offset voltage.
Figure Analysis of the closed-loop amplifier, taking into account the input bias currents.
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41. Balancing the input resistors helps.
Figure Reducing the effect of the input bias currents by introducing a resistor R3.
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42. Balance in the input circuit is maintained in an AC coupled OpAmp by matching R2
Figure In an ac-coupled amplifier the dc resistance seen by the inverting terminal is R2; hence R3 is chosen equal to R2.
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43. sedr42021_0236.jpg
Figure Illustrating the need for a continuous dc path for each of the op-amp input terminals. Specifically, note that the amplifier will not work without resistor R3.
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44. Same as with resistances, but now we have “s” (the Laplace transform complex frequency)
ZL=sL; ZC=1/sC; ZR=R
Figure The inverting configuration with general impedances in the feedback and the feed-in paths.
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45. Set s=j to get the complex frequency response
A=R2||(1/sC)/R1; DC gain = -R2/R1 High frequency gain =0; 3dB point determined by R2C2
Set s=j to get the complex frequency response
Figure Circuit for Example 2.6.
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46. Used to build “Analog Computers” (along with adders and multipliers)
They were popular (and very useful) when I was an undergraduate – 1960’s
Interestingly, Simulink (Matlab, a very useful tool) simulates an analog computer on a digital computer
Figure (a) The Miller or inverting integrator. (b) Frequency response of the integrator.
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47. Details again. Put a large resistor across C to fix (see slide after next)
Figure Determining the effect of the op-amp input offset voltage VOS on the Miller integrator circuit. Note that since the output rises with time, the op amp eventually saturates.
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48. sedr42021_0241.jpg
Figure Effect of the op-amp input bias and offset currents on the performance of the Miller integrator circuit.
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49. sedr42021_0242.jpg
Figure The Miller integrator with a large resistance RF connected in parallel with C in order to provide negative feedback and hence finite gain at dc.
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50. Yes, it does the integral
Figure Waveforms for Example 2.7: (a) Input pulse. (b) Output linear ramp of ideal integrator with time constant of 0.1 ms. (c) Output exponential ramp with resistor RF connected across integrator capacitor.
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51. High frequency noise is a problem here
Put a resistor across the input capacitor to limit HF gain
And a small capacitor across the output resistor to provide a second HF “pole”
Figure (a) A differentiator. (b) Frequency response of a differentiator with a time-constant CR.
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52. Spice models (used in Multisym, OrCad or LTspiceIV)
You can also use a manufacturer supplied spice model
Figure A linear macromodel used to model the finite gain and bandwidth of an internally compensated op amp.
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53. sedr42021_0246.jpg
Figure A comprehensive linear macromodel of an internally compensated op amp.
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54. sedr42021_0247.jpg
Figure Frequency response of the closed-loop amplifier in Example 2.8.
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55. sedr42021_0248.jpg
Figure Step response of the closed-loop amplifier in Example 2.8.
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56. Low noise (small signal amplification)
The 741 was an early, practical, OpAmp and is still in use (available at low cost)
Many better ones, specialized for particular characteristics are available:
Low noise (small signal amplification)
High power out/slew rate (Output stages)
Low power drain (battery operation)
High voltage operation (large voltage swings)
Figure Simulating the frequency response of the µA741 op-amp in Example 2.9.
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57. Stability is almost guaranteed by the low phase shift (just over 90) at unity gain (0 dB)
Figure Frequency response of the µA741 op amp in Example 2.9.
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58. sedr42021_0251.jpg
Figure Circuit for determining the slew rate of the µA741 op amp in Example 2.9.
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59. sedr42021_0252.jpg
Figure Square-wave response of the µA741 op amp connected in the unity-gain configuration shown in Fig
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60. The remaining 31 figures are from end-of-chapter problems.
Figure P2.2
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61. sedr42021_p02008.jpg
Figure P2.8
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62. sedr42021_p02016.jpg
Figure P2.16
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63. sedr42021_p02022.jpg
Figure P2.22
Microelectronic Circuits - Fifth Edition Sedra/Smith

64. sedr42021_p02025.jpg
Figure P2.25
Microelectronic Circuits - Fifth Edition Sedra/Smith

65. sedr42021_p02030.jpg
Figure P2.30
Microelectronic Circuits - Fifth Edition Sedra/Smith

66. sedr42021_p02031.jpg
Figure P2.31
Microelectronic Circuits - Fifth Edition Sedra/Smith

67. sedr42021_p02032.jpg
Figure P2.32
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68. sedr42021_p02033.jpg
Figure P2.33
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69. sedr42021_p02034.jpg
Figure P2.34
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70. sedr42021_p02035.jpg
Figure P2.35
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71. D to A Converter Figure P2.43
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72. Analog Voltmeter (I used to use a VTVM)
Figure P2.46
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73. sedr42021_p02047.jpg
Figure P2.47
Microelectronic Circuits - Fifth Edition Sedra/Smith

74. sedr42021_p02049.jpg
Figure P2.49
Microelectronic Circuits - Fifth Edition Sedra/Smith

75. sedr42021_p02050.jpg
Figure P2.50
Microelectronic Circuits - Fifth Edition Sedra/Smith

76. sedr42021_p02051.jpg
Figure P2.51
Microelectronic Circuits - Fifth Edition Sedra/Smith

77. sedr42021_p02059.jpg
Figure P2.59
Microelectronic Circuits - Fifth Edition Sedra/Smith

78. sedr42021_p02062.jpg
Figure P2.62
Microelectronic Circuits - Fifth Edition Sedra/Smith

79. sedr42021_p02068.jpg
Figure P2.68
Microelectronic Circuits - Fifth Edition Sedra/Smith

80. sedr42021_p02069.jpg
Figure P2.69
Microelectronic Circuits - Fifth Edition Sedra/Smith

81. sedr42021_p02070.jpg
Figure P2.70
Microelectronic Circuits - Fifth Edition Sedra/Smith

82. sedr42021_p02071.jpg
Figure P2.71
Microelectronic Circuits - Fifth Edition Sedra/Smith

83. sedr42021_p02077.jpg
Figure P2.77
Microelectronic Circuits - Fifth Edition Sedra/Smith

84. sedr42021_p02078.jpg
Figure P2.78
Microelectronic Circuits - Fifth Edition Sedra/Smith

85. sedr42021_p02108.jpg
Figure P2.108
Microelectronic Circuits - Fifth Edition Sedra/Smith

86. sedr42021_p02117.jpg
Figure P2.117
Microelectronic Circuits - Fifth Edition Sedra/Smith

87. sedr42021_p02118.jpg
Figure P2.118
Microelectronic Circuits - Fifth Edition Sedra/Smith

88. sedr42021_p02119.jpg
Figure P2.119
Microelectronic Circuits - Fifth Edition Sedra/Smith

89. sedr42021_p02122.jpg
Figure P2.122
Microelectronic Circuits - Fifth Edition Sedra/Smith

90. sedr42021_p02125.jpg
Figure P2.125
Microelectronic Circuits - Fifth Edition Sedra/Smith

91. sedr42021_p02126.jpg
Figure P2.126
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