1. CMOS LNA Design Optimization Approaches.
Viswakiran Popuri
EE201C (Spring 2009)

2. Overview Motivation: Need for Analog/RF CAD Major Contributions
Comparison of Various approaches
Future scope

3. Need for Analog/RF Design Automation
SoCs are becoming more and more digital.
CAD has made Digital design (RTL to Layout) almost a push button job thus reducing its design time.
SoCs are designed using Digital top flow leveraging on the CAD developed for Digital design.
Analog/RF Design (circuit & layout) time on the other hand increased in spite of fast SPICE-like simulators as more issues like
Simulator related
DC convergence problems due to very complex models of the components.
Process related
Statistical (Worst case corner extraction / Monte Carlo runs) simulations are a must due to increased process variations.
Integration related
Reliability/ESD/SoC integration checks are a must.

4. CAD: Digital vs Analog/RF
Feature
Digital
Analog/RF
Functionality
Single mode
Multi-modes
Set of gate sizes
Limited
Unlimited (practically)
Trade-offs
Area  Power Delay
Many more..
Process Variations
Modeled in terms of Power/delay tables
Difficult to translate them into perf specs.
Hierarchy
Defined flow of design info across hierarchy.
No abstraction of design info.

5. Problems Specific to RF Design
Circuits are typically tuned /narrowband.
The center frequency is very sensitive to parasitics of the elements.
Series resistance of a on-chip spiral inductor
Bottom/top-plate capacitance & ESR of on-chip MIM/N-well Capacitor.
In LNAs & Mixers, Linearity (IIP3) is an important spec and it requires a long time-domain simulation.
In Oscillators, Phase noise is an important spec and requires a long PSS simulation.
Typically, these two are the bottleneck for RF circuit simulation time.
Noise due to parasitic resistances accumulate.
Eg. Induced Gate Effect, Distributed Gate Resistance give rise to Gate noise.

6. Major Contributions Design perspective
[1] Shaeffer, “A 1.5-V, 1.5-GHz CMOS LNA”, JSSC May 1997
[2] Nguyen, “CMOS LNA Design Optimization Techniques”, IEEE Trans on Microwave Theory & Techniques, May 2004
Automation perspective
[3] Tulunay, “A Compact Optimization Methodology For Single-ended LNA”, ISCAS 2004
[4] Vancorenland, “Optimal RF design using smart Evolutionary Algorithms”, DAC 2000
[5] Nieuwoudt, “SOC-NLNA: Synthesis and Optimization for fully Integrated Narrow-Band CMOS LNA”, DAC 2006
[6] Wai-kit So, “Design and Optimization of Highly Linear CMOS LNA via Geometric Programming”, ASICON 2007

7. Design Perspective LNA Design has multiple competing specifications
Moderate Power gain
Reduced Noise Figure
Acceptable Linearity
Good Input/Output Impedance Matching
Isolation between Input and Output
Low Power Dissipation
SOC level constraints
Number of Pads available for LNA
Type of inductor:
On-chip spiral inductor (low Q)
Bondwire inductor (low Inductance value & needs a pad)
Off-chip inductor (needs a pad & PCB footprint)

8. Design Optimization Approaches in LNA
Four Popular Approaches.
Classical Noise Matching (CNM)
Simultaneous Noise and Input Matching (SNIM)
Power Constrained Noise Optimization (PCNO)
Power Constrained SNIM (PCSNIM)
Adding more components to give more degrees of freedom.
Typically, input transistor’s size, (Vgs-Vt) are the design parameters.
Added in SNIM
Added in PC-SNIM

9. Design Optimization Using SPICE
Typically optimized by SPICE simulations.
Trade-off curves are derived and optimal design points are decided.
Pd increase =>
NF Decrease
*Figure from [1]
*Figure from [2]

10. Optimization Automation Perspective
Modeling approaches
SPICE based (Slow and accurate)
Equation based (Fast and manually derived)
Curve-fitting models based (Fast and automatically derived)
Optimization approaches
Stochastic
Find global optimum through many simulations
E.g
Simulated Annealing [3]
Evolutionary Algorithm [4]
Deterministic
Quicker result for smoother objective function.
Sequential Quadratic Programming [5]
Geometric Programming [6]

11. [3] Tulunay, “A Compact Optimization Methodology For Single-ended LNA”, ISCAS 2004
Equation-based modeling of gain, noise figure, input impedance.
Simulated annealing based optimization.
Uses parasitics during optimization.

12. Optimization Formulation
Width of the input transistor (W), Load inductance (Ld), gate inductance (Lg), Source inductance (Ls) and the bias current (Ibias) are the five design variables.
Goals: NF, S21, S11.
Equality constraints: Real(Zin) = 50 Ohms, Imag(Zin) = 0
Inequality Constraints: Power = Vdd*Id, Area = A(Ls) + A(Ld) + 2*W*L
Equality constraints
Inequality constraints
E & I are sets of equality and Inequality constraints.
[ci(x)] = max{0,-x} and μ is the penalty parameter determining the weight that we assign to constraint satisfaction relative to minimization of the objective function.
Weights are determined iteratively to get the best solution.

13. Results 0.35 um CMOS technology
Not at 900 Mhz. Needs further fine tuning

14. [4] Vancorenland, “Optimal RF design using smart Evolutionary Algorithms”, DAC 2000
Uses approximate Model most of the times. The approximation is corrected by evaluating the real circuits once in a while.
Behavioral model instead of curve-fitted model to capture the design knowledge.
Genetic Algorithm called “Differential Evolution” (DE) is used as the optimization routine.
The crucial idea behind DE is a scheme for generating trial parameter vectors.
DE adds the weighted difference between two population vectors to a third vector. This way no separate prob distribution has to be used which makes the scheme completely self-organizing.

15. Advantages of DE DE is a very fast and efficient genetic algorithm.
It is faster than ‘spice in the loop’ approach since a major part of the function evaluations is done on a faster fitted model.
Behavioral model will generally generated a better fitting over a wider range compared to a polynomial approximation.
Possibly cascade the algorithm with a non-stochastic greedy algorithm, leading to a faster convergence.
The algorithm is inherently parallel making it very suitable for parallel optimizations.

16. Behavioral models used
LNA Models:
Inductor Model:
Specifications:

17. Optimization Formulation
Cost function is a composite function of many objectives.
Proper weights & exponents to be assigned to each cost part for achieving the best solution.
Cost function is fitted using a non-stochastic algorithm.
Find the parameter set [P1opt…..PNopt] satisfying the minimization constraint.

18. Results First, LNA was optimized for given specs (Ibias = 5mA)
Then, use the fitted behavioral model of the first experiment to derive the global trade-off of LNA gain for Power between optimal designs.

19. Sequential Quadratic Programming for single objective case
[5] Nieuwoudt, “SOC-NLNA: Synthesis and Optimization for fully Integrated Narrow-Band CMOS LNA”, DAC 2006
Accurate Analytical Model for LNA (next slide). It is claimed to be 40% more accurate than other reported models.
Sequential Quadratic Programming for single objective case
Normal Boundary Intersection method for pareto curve generation

20. Analytical Models capturing the parasitics accurately
Noise figure has
gate induced noise
Distributed gate resistance

21. Optimization Formulation
Multi-objective function is converted to single-objective function and solved using SQP.
SQP exploits gradients in the objective and constraint functions at each iteration. This means both the functions should be convex in order for SQP to reach global optimum.

22. Normal Boundary Intersection
Find the individual minima for each of the perf.
The idea is that the pareto optimal points are underneath the convex hull of the individual minima.
A search on a line normal to the hull towards origin yields pareto optimal points if the respective portions are convex.

23. Results (0.35 um CMOS) Lower Values of Inductor MonteCarlo Designs
CPCNO (Classical Power Constrained Noise Optimization)
MPCNO (Matched Power Constrained Noise Optimization)
MonteCarlo
Designs
Better than
stochastic
Optimization

24. [6] Wai-kit So, “Design and Optimization of Highly Linear CMOS LNA via Geometric Programming”, ASICON 2007
Fitted posynomial model for the LNA
Geometric programming used for optimization.
Geometric Programming is used in analog sizing based on the premise that the objective and constraint functions are convex.
Linearity (IIP3), typically measured through long transient simulations is modeled using a curve-fitted monomial equation.

25. Convex Problem
Optimization problem with nonconvex objective f(x) (a) and convex objective (b).
In the nonconvex problem, a gradient-based method finds a local optimum in a (initial guesses 1 and 2), in b (initial guesses 3 and 4), or in c (initial guess 5).
In the convex problem, the optimum d is found using interior-point algorithms regardless of the initial guess.

26. Optimization Formulation
Minimization of a convex obj function over a convex set.
GP is a special kind of convex programming consisting of posynomials.
f(x1,…..,xn) is a posynomial if it has the form shown below left.
Ck are non negative.
f’s are posynomials and g’s are monomial functions.

27. Monomial Fitting technique
Used for approximating GP-incompatible constraint, f(x), and turning it into a GP-compatible format f’(x)
Applicable when f(x) is convex in a log-log plot against its variables x.
The objective of the fitting process is to minimize the difference between the original function f(x) and the fitted monomial approx function f’(x), by least-square method.
Weights a & c are chosen to minimize the sum of squared errors. This is solved as a linear regression problem.

28. Monomial Fitted Models
IIP3’s monomial fitted through data from SPICE simulations.

29. Results (0.18 um CMOS)
IIP3 estimates deviate more as it requires transient simulation and is difficult to model using simple equation.
NF and IIP3 are highly sensitive for low bias currents (Id =1mA).

30. Comparison of the Various Approaches
Tulunay
Vancorenland
Nieuwoudt
Wai-kit So
Modeling
LNA Perf
Simple model
Behavioral Model + SPICE model
Accurate Analytical models
Monomial models
Accuracy of Parasitics
Moderate
Accurate
Linearity No
Yes
Optimization
Algorithm
Simulated Annealing
Evolutionary
SQP GP
Computation
Not Reported
< 1 Min for Pareto Graph
575 eval (22.5
Sec) -> LNA
2573 eval (152.7
Sec) -> Pareto
< 1 Sec!

31. Recap of the Approaches
[3] Deals it with simplistic equations & simulated annealing optimization.
The results are not accurate.
[4] Uses mixed modeling & Genetic algorithm.
Faster than SPICE but more accurate than [3]
The weights of the cost function are generated through a greedy algorithm.
[5] Uses Accurate analytical model and optimizes using SQP
Accurate model has the essential parasitics.
Gives lower inductance values than manual designs & performs better than Stochastic methods.
[6] Uses Curve-fitted monomial models and GP for solving it.
Models linearity using a monomial. SPICE results show maximum deviation from model results for linearity.
All parasitics are not included. Noise estimation more optimistic than SPICE.
Quickest and global optimum is assured for convex functions.

32. Future Scope
Find a way to estimate Linearity (IIP3) through computationally less intensive simulation (for eg. DC)
Statistical variation into the parameters.
Include choices like type of inductor (On-chip, bondwire, Off-chip) into the system level optimization.
Allow more Package/Interface/RF front-end co-design as they are tightly coupled.

33. Thank You! Q & A