1. System Level JTAG Life Cycle solution Worldwide FAE Meeting
Delivered by: Ken Filliter

2. Agenda – System Level JTAG
System level JTAG – (why and what for)
Customer examples
Mini-JTAG tutorial (common buzzwords)
Dealing with multiple SCAN chains (STA112)
Embedded JTAG (STA101 & SCANEASE)
Differential Signals (IEEE1149.6)
Analog Test (STA476)
Bringing it all together
More applications examples
This presentation will cover why our major infrastructure customers are using system level embedded JTAG for test and programming.
We won’t go into too much detail on the standard itself – the 1s and 0s are generated using software after all.
NSC offers a comprehensive JTAG system solution that includes the ability to mux multiple scan chains and provide the hardware/software components of a JTAG Master
We also offer devices that meet the differential JTAG standard and the only one of it’s kind, an Analog JTAG master.
There are a lot of capabilities for this type of set-up, so the intent is to showcase all of the various things customers are doing – and why.
Worldwide FAE Meeting
Delivered by: Ken Filliter

3. System Level JTAG – Why ? Infrastructure Philosophy ~ 2000
DfT Design for Test
importance of testability well established
JTAG used extensively for proto and Mfg test.
JTAG as a general purpose Maintenance Bus
IEEE 1532 describes how to configure FPGAs using JTAG. Adopted by Xilinx, Altera and Lattice.
Pervasive JTAG also becomes de facto choice for emulation for uP and DSPs.
The IEEE JTAG standard was ratified in 1990 – at the time this was driven by the emergence of surface mount packages and the fact that In-Circuit-Testers (ICT) needed physical access to test – and that access was going away.
Ten years later ~2000, JTAG has become pervasive in high pin count digital ICs such as ASICs, FPGAs, DSPs and uPs. JTAG use is extensive for complex digital boards, such as used in infrastructure – there is no other way to provide testability.
As JTAG use became extensive, IC manufacturers took advantage of an existing bus for other tasks – such as programming and emulation. The IEEE1532 standard described FPGA programming via JTAG and emulators using the JTAG bus became very common.
By 2008, JTAG has become a widely used test and maintenance bus – particularly in complex primarily digital cards – as used in Infrastructure.
2008 – JTAG the dominant bus for Test, Programming and Emulation
Worldwide FAE Meeting
Delivered by: Ken Filliter

4. Infrastructure Life Cycle Challenges
IBM commits that new Server blades will always be backwards compatible to existing platforms.
Telecom vendors routinely assume ~20 year support life for Infrastructure – and of course 5 9s reliability.
Costs for Technician Service calls prohibitive
Hardware/Software upgrades accelerating
Proliferation of standards/new features.
Let’s look at the Life cycle challenges facing the Datacom/Telecom Infrastructure community.
Backwards compatibility is a serious end customer concern. No service provider wants to buy very expensive hardware that is obsolete in 2 years. A major selling point for IBM is guaranteed backwards compatibility for servers.
Telecom hardware is often expected to last as long as 20 years, and there are lucrative service contracts involved to make this happen. The famous % up-time is still the benchmark for reliability
Technician service calls are very expensive – and thus avoided as much as possible.
The introduction of new standards and revenue generating features and services is accelerating – how to support these with fielded hardware ?
All of the above make a strong case for why the ability to perform remote system level firmware upgrades is a compelling feature.
Worldwide FAE Meeting
Delivered by: Ken Filliter

5. Life Cycle Advantages 1.) Upgrades 2.) Test and Diagnostics
Ability to remotely perform system wide firmware upgrades
2.) Test and Diagnostics
Ability to do remote testing and diagnostics
Ability to perform software debug
Reduce “No-Fault-Found” problem
There are two capabilities that are very desirable in fielded infrastructure hardware.
First is the ability to perform remote firmware upgrades – perhaps FPGA configuration code or boot code.
The 2nd is the ability to perform remote comprehensive testing. Being able to identify failures in hardware and then diagnose the failure. This capability may enable work-arounds, shorten any required service call and reduce no-fault-found incidence of returned cards.
A subset of the remote test is software testing, that is use the same access and registers used for emulation during development, remotely.
Worldwide FAE Meeting
Delivered by: Ken Filliter

6. System Level Challenges
This card appears to have a hardware fault, can I run BIST ?
This card has intermittent crashes – like to access diagnostic registers
Here’s a fielded system and some of the administrative tasks that would come in handy. The card on the left has intermittent crashes and then boots OK. It would be useful to access the diagnostic registers to analyze the fault. The card in the middle can’t support a new feature – a firmware update would fix that but a technician call is too expensive.
The card on the right appears to have a hardware failure. Before I send a technician with a new card I’d like to run all of the Built-In-Selt-Test (BIST) routines and better understand the actual failure.
This card needs a firmware update – how can I do it remotely ?
Worldwide FAE Meeting
Delivered by: Ken Filliter

7. No Fault Found Dilemma
What to do when expensive returned cards pass all tests in the factory….?
Might be a software problem ?
Likely due to connector or backplane ?
Technician may have replaced cards until problem went away – most cards good ?
Very desirable to have field test capability and fault logs.
“No-Fault-Found” is a nagging problem when servicing hardware.
Here’s a typical scenario – a technician arrives at a frantic customer who’s system is in trouble. The technician pulls a card that seems like the likely problem but the problem remains, a 2nd card is replaced and now the system works fine. The technician suggest that the 2nd card is at fault but the customer thinks either or both cards may be bad – send them both back. At the factory both cards test fine. Now what ? Do we send potentially bad cards to a customer ?
If BIST and other test techniques can be run remotely, then the service rep has a better chance of immediately fixing the problem, and returned hardware has a known fault.
Worldwide FAE Meeting
Delivered by: Ken Filliter

8. System Level JTAG Examples
Unisys uses STA101 for remote debug of high-end servers.
Nokia & Motorola use STA476 in 3G basestations to verify power supply voltages during factory and field test.
Nortel uses STA101/111/112/SCANEASE for remote test, firmware upgrades and debug in EDGE Routers and High-end Servers
This slides lists some of the typical uses our infrastructure customers have for system or embedded JTAG.
Note the variety of uses – some test, FPGA and FLASH programming, emulation and Analog testing.
It’s valuable to understand the customers “hot buttons” because JTAG is a very versatile bus standard.
Worldwide FAE Meeting
Delivered by: Ken Filliter

9. System Level JTAG Examples
Cisco uses STA101/111/112/SCANEASE for firmware upgrades in mid and high-end Routers.
Huawei uses STA101/111/112 for firmware upgrades in 3G basestations, Routers and Switches.
Ericsson uses STA111/112 for field BIST testing of Routers.
Customers who use a lot of FPGAs are often interested in an embedded JTAG bus for FPGA programming and possible upgrades over the life cycle.
Designs that are more ASIC based tend to be more concerned with testing – generally running the Built0-in-Self-Test (BIST) algorithms.
Worldwide FAE Meeting
Delivered by: Ken Filliter

10. Hundred’s of high-speed differential connections
Ericsson Switch Card
Confidential
GOAL !
Field Test
STA111
ASIC
Complex Digital ASICs
Field Test
Hundred’s of high-speed differential connections
This is a simplified view of an Ericsson Switch card. Ericsson makes extensive use of complex proprietary ASICs with large numbers of high-speed differential channels.
The goal is to have a very quick and thorough test of the potential failure points – the complex ASICs, and the connections between them.
Backplane
Worldwide FAE Meeting
Delivered by: Ken Filliter

11. Ericsson Field Testing
Confidential
Run simultaneous Built-in-Self-Test (BIST) on complex ASICs
Download pass/fail signatures
STA111
ASIC
A very quick and thorough way to test this card is to first do a parallel interconnect test on all of the differential I/O. Then initiate BIST simultaneously in all of the ASICs and verify the signatures. In a short amount of time Ericsson achieves very high fault coverage.
Run parallel dot 6 tests on interconnect – ensure no failures
Backplane
Worldwide FAE Meeting
Delivered by: Ken Filliter

12. e.g. - Cisco Router Goals: uP ASIC ASIC STA112 SPA1 SPA2 SPA3 SPA4
1.) Allow external test via JTAG header of MB & SPAs
2.) Program SPA FPGAs using MB Flash
FLASH uP
ASIC
ASIC
STA101
STA112
JTAG
Header
LSP0
LSP6
LSP5
LSP4
LSP3
LSP2
This block diagram is a portion of a Cisco router. This particular model is scalable and has 4 optional cards that can be added at any time.
Cisco uses JTAG in a couple of ways – in the factory they connect via the JTAG header and test the mother board using the STA112 to access the mother board.
For the fielded system they use the embedded JTAG Master, our SCANSTA101 and SCANEASE software to program the FPGAs on the SPA cards. Note that if the 4 cards are identical they only need one Flash memory to update all the FPGAs.
Also if at some point they wanted to change the FPGA code, they could use JTAG to update the FLASH on the mother board either remotely or by technician
SPA1
SPA2
SPA3
SPA4
Confidential
Optional Jacket Cards
Worldwide FAE Meeting
Delivered by: Ken Filliter

13. e.g. – Nokia 3G Base Station
Nokia uses STA476 to monitor 16 different power supply Voltages on complex 3G cards
STA 476
STA 476
Nokia’s 3G basestations have numerous power supplies and during factory test it’s a challenge to get quick and accurate verification of all supplies. They use our SCANSTA476 to check as many as 8 supplies. Some complex cards even require 2 STA476s to monitor 16 voltages.
Confidential
Worldwide FAE Meeting
Delivered by: Ken Filliter

14. JTAG IEEE1149.1 (A few basic concepts)
It’s most important to understand how customers are using the JTAG standard, however a basic understanding of the spec is useful in understanding the bottlenecks and some of the features of our devices.
One point we emphasize to customers is that 3rd party software tools are available to generate all of the necessary vectors – it’s not necessary to have an intimate knowledge of the standard to derive the benefit.
Worldwide FAE Meeting
Delivered by: Ken Filliter

15. Testing before JTAG Test Headaches Big Tester “Bed of Nails” Fixture
The old method of testing complex boards involved an in-circuit tester that was expensive, proprietary, and required a long development time. Today’s very high density boards, many-layer printed circuit boards (PCBs) with buried nodes, and ball grid array (BGA) packages with hidden balls make such testing very difficult.
Complex Bed-of-Nails fixtures can run in the several $10Ks of $ and often require 3-4 weeks development time. In-Circuit-Testers require relatively large pads that complicate layout – also they must have direct physical access to nodes.
Test Headaches
an in-circuit “bed of nails” tester (ICT) was used
but buried nodes and hidden balls makes this impractical
also high cost, long development time, and proprietary hardware
Worldwide FAE Meeting
Delivered by: Ken Filliter

16. Testing with JTAG Test System in a PC
Just 5
wires!
JTAG technology means test points for each device pin are built into the ICs and these test point are connected to a 5-wire serial bus. Test development and execution can then be done on a simple personal computer (PC).
Using ATPG (Auto-Test-Pattern-Generation) software vectors can be generated in a short time. 3rd party tools combining hardware and software run from 10K$ to 50K$ per seat depending on complexity and features.
JTAG to the Rescue
test points are “built into” chips to allow “virtual” access
low cost, short development time, and universal hardware
Worldwide FAE Meeting
Delivered by: Ken Filliter

17. JTAG Is Added “Around” IC Allows Access to Pins & Internal Nodes
The 5-wire serial JTAG bus (actually, the /TRST pin is optional) consists of a serial bus around each IC and a state machine known as a “Test-Access-Port”.
TDI is fed into the device – then routed to a flipflop pair for every I/O and then leaves the device at the TDO pin. The boundary scan cells (BSC) are transparent when the device is in mission mode but when in test mode can be used to force (outputs) or sample (inputs) test vectors.
TCK (test clock) and TMS (test mode select) are used to control the state machine that determines if the device is in mission mode or test mode. TRST (Test Reset) is an optional pin that is an asynchronous return to mission mode.
5-Wire JTAG
Serial Test Bus
Worldwide FAE Meeting
Delivered by: Ken Filliter

18. IEEE-1149.1 State Machine (aka TAP Test-Access-Port)
This is a block diagram of the 16 state Test Access Port. The TAP determines if the device is in mission mode (TLR Test-Logic-Reset) or in one of the 15 states that control the test circuitry. When in test mode, the state machine controls whether the device is shifting in vectors, or updating (force/sense). There are 3 registers of interest, the data register that has the test vectors, the instruction register that contains the test instruction and a 1 bit bypass register to allow the device to be bypassed.
For the purpose of today’s discussion the important points are that the TAP, controlled by TCK and TMS determines the mission or test condition of the device, and serial data, either instructions or data can be loaded into all of the devices in the chain.
Worldwide FAE Meeting
Delivered by: Ken Filliter

19. The “SCAN Chain” How JTAG is Connected on the PC Board
Serial data in/out makes one big loop through all chips
Clock, mode, and reset signals shared by all chips
TAP control pins TCLK, TMS, and TRST pins are connected in parallel:
All chips are driven by one TMS signal from the PC
All chips are driven by one TCLK signal from the PC
All chips are driven by one TRST signal from the PC
The serial chain pins TDI and TDO signals are daisy-chained together:
PC  Chip 1 TDI
Chip 1 TDO  Chip 2 TDI
Chip 2 TDO  Chip 3 TDI
Chip 3 TDO  Chip 4 TDI
Chip n-1 TDO  Chip n TDI
Chip n TDO  PC
Worldwide FAE Meeting
Delivered by: Ken Filliter

20. Using JTAG to Test Board Interconnect Integrity
Now let’s show how JTAG can be used for testing circuit boards.
Worldwide FAE Meeting
Delivered by: Ken Filliter

21. Interconnect Faults Using On-Chip BSC’s for “Continuity Testing”
JTAG boundary scan cells (BSCs) can detect open & short circuits
Data is sent from a BSC on one chip and read by a BSC on another chip
One of the primary uses of JTAG is to check board interconnect integrity. The boundary scan cells (BSCs) allow output pins to be driven with a specific value (1 or 0) or the data on input pins captured (as 1 or 0). The data from the TDI-TDO serial chain is placed in the BSC registers so that 1’s and 0’s from one chip output can be driven and captured by any chips inputs which are connected to the net. In this way, “continuity tests” can be performed to find faults like poor solder joints, short circuits, etc. For complex nets a pattern of 1s and zeros may be necessary to find all faults.
In this example we can see a solder bridge, an open and shorts to Vcc and Gnd. One of the enormous advantages of JTAG testing is the pin-level diagnostics. These mechanical faults would not only be detected, but the operator would be informed of the faulty net (or pin) and the type of fault.
Worldwide FAE Meeting
Delivered by: Ken Filliter

22. Software Tools Automatic Test Pattern Generation (ATPG)
Boundary Scan Definition Language
Board Description – Net List
Device 1: pin 1 = output
pin 2 = input
pin 3 = JTAG pin TDI
Device 1, pin 1  Device 2, pin 3
Device 1, pin 3  Device 2, pin 2
Device 2, pin 1  Device 9, pin 12
Device 9, pin 3  Device 7, pin 7
BSDLs
Net List File
Device 2: pin 1 = I/O
pin 2 = JTAG pin TDO
pin 3 = input
How does the JTAG PC-based tester know what combinations of 1’s and 0’s to drive into the serial JTAG bus?
Manufacturers selling ICs with JTAG provide a JTAG boundary scan description language (BSDL) file which describes how the internal JTAG circuitry in the chip works and is connected.
The way the chips are connected is provided by the customer’s schematic design program as a netlist.
The automatic test pattern generation (ATPG) software takes these files and can then use an algorithm to generate the sequence of 1’s and 0’s driven through board’s serial JTAG bus to exercise and test the interconnect.
Various vendors provide ATPG software such as JTAG Technologies, ASSET Intertech, Gopel, Corelis and so-on. Some customers even develop their own ATPG tools.
BSDLs available on Website
ATPG Software
on PC
Board
Under
Test
… …
Worldwide FAE Meeting
Delivered by: Ken Filliter

23. Non-Test uses of JTAG FPGA & Flash Programming, Emulation
JTAG is very well supported as the programming port for all major FPGA suppliers.
JTAG is frequently used to program Flash. This is accomplished by using the JTAG registers of adjacent devices and updating address/data
JTAG is the standard choice for emulators for uPs and DSPs.
As the 4 (or 5) JTAG pins became added to more and more ICs manufacturers decided to take advantage of this well established protocol for other purposes.
FPGAs began using the JTAG port as one of the ways to program the devices. JTAG programmers have become a very popular development tool. The IEEE1532 standard was written after the fact to standardize this practice
Emulators followed a similar path and JTAG based emulators are very common and well supported.
Very few if any memory devices have JTAG but they are almost always connected to devices that do. As a result, people began programming Flash by loading the appropriate vectors into adjacent devices and accessing the data & address lines
Non-test use of JTAG may in fact be equal to the original purpose of digital test.
Worldwide FAE Meeting
Delivered by: Ken Filliter

24. Vector Formats
SVF – Serial Vector Format is the defacto standard for describing JTAG vectors. FPGA and Test vendors can all convert their proprietary formats to SVF.
SVF is a command line interpreted language
SVF instructions describe functions such as “shift data register X number of bits”
For use in embedded applications SVF instructions must be converted into binary JTAG bit streams --- This is what SCANEASE does
There are several vector formats used to describe JTAG instructions. The most common and widely used is SVF, Serial - Vector - Format. Although many ATPG and FPGA vendors have their own proprietary format, almost all formats can be converted to SVF
SVF is a command line interpreted language and therefore must be parsed by the tool running the JTAG vectors. This may be a PC or FPGA programmer.
SVF vectors describe operations such as “shift data register X number of bits,
update instruction register, and so-on.
When customers decide to use an embedded JTAG solution they need to store the JTAG vectors in a binary format. This is one of the tasks of NSC’s SCANEASE software, to convert SVF into a binary format, in our case “EVF”, Embedded Vector Format.
Worldwide FAE Meeting
Delivered by: Ken Filliter

25. 3rd Party Tool Vendors They make our job easier!
3rd party tool vendors provide the following customer services:
Generate test vectors using ATPG
(Auto-Test-Pattern-Generation)
Generate Flash programming vectors
Create headers & tailers necessary for addressing SCAN Bridges
Example vendors
ASSET Corelis
Goepel JTAG Technologies
There are several 3rd party tool vendors who provide software and hardware tools for JTAG testing and programming. Typical products are as follows:
1.) ATPG for generating test vectors
2.) Diagnostics and tools that calculate test coverage
3.) Generating vectors for JTAG based Flash programming
The established vendors have 15+ years in the business and have developed powerful and user-friendly products. Almost all of the vendors do an excellent job supporting our SCAN Bridge addressable mux devices. Customers should be encouraged to use these tools -- generating JTAG vectors by hand is a slow process --- and if something goes wrong and it doesn’t work -- we get the call !
3rd party tool vendors have automated and proven tools, and if something doesn’t work, they can generally find the problem.
Worldwide FAE Meeting
Delivered by: Ken Filliter

26. System Test Access Products
SCAN Path Management
System Test Access Products
There are several reasons why customers need multiple Scan chains (JTAG).
Given that multiple scan chains are desirable how they accomplish the necessary muxing is what we call “Scan Path Management”.
Worldwide FAE Meeting
Delivered by: Ken Filliter

27. JTAG Life Cycle Requirements
Development
Board Test
Integration
In the Field
Emulation X
FPGA & Flash Programming
Structural Test
At-Speed BIST
Diagnostics
Prognostics
This chart lists the typical uses of JTAG and where in the life cycle that particular capability is desirable. For example, during development emulation is very much required, but once the design is complete there is no need in factory test or integration. However this might again be useful for a “buggy” fielded system.
We encourage customers early in the development cycle to understand their total requirements – or “like-to-haves”. Then they can best design a JTAG architecture that is optimized for what they want to accomplish.
Worldwide FAE Meeting
Delivered by: Ken Filliter

28. NSC JTAG System Solutions
SCANSTA111/112 bridge partitions multi-card systems
High-speed
Card-to-Card Communication
(LVDS)
SCAN92LVxxxx
Embedded P running ScanEASE
IEEE Multi-Drop System
Test Bus {
Access to
IEEE Reconfigurable CPLD’s/FPGAs
SCANSTA101 Master drives test vectors
This busy slide shows the various NSC system level boundary scan capabilities. We have:
SCANSTA476 capable of measuring Analog voltages and downloading them through the digital JTAG chain
SCANSTA101 embedded JTAG Master capable of driving test or programming vectors
SCANEASE C code running on the resident uP and driving the STA101.
SCANSTA111 & STA112 addressable JTAG mux devices – known as SCAN Bridges to allow multiple JTAG chains in a system.
LVDS devices with IEEE differential boundary scan and Ser/des with JTAG initiated BIST.
Analog and Mixed-signal Test STA476
LVDS & TTL Backplane Interconnect test
Access to BIST and Embedded Test features
Worldwide FAE Meeting
Delivered by: Ken Filliter

29. Scan Path Management
IEEE
1149.1
FPGA µP
The JTAG standard is a serial bus and that works fine for short chains.
For complex systems – such as typically seen in Infrastructure, there are numerous devices and cards in the system. A long chain results in a very long test or programming time and also complicated the process or programming or emulation. One of the famous maxims of the test industry is “Divide and Conquer”. In other words, a number of small manageable chains is much more efficient then 1 long chain.
In the typical example shown, let’s assume we have multiple FPGAs that engineers want to debug using JTAG programmers, a uP that requires an emulation port and the test engineer would prefer multiple chains to optimize the test time and coverage.
One long chain is a poor solution for everyone, and multiple JTAG headers take up board area and add expense.
A Single Serial JTAG chain connecting all devices results in:
Large test vector files
Long test times
Limited fault isolation or device targeting
Worldwide FAE Meeting
Delivered by: Ken Filliter

30. Partitioning JTAG Chains
IEEE
1149.1
SCAN
STA
111 µP
FPGA
LSP1
LSP2
LSP3
The SCANSTA111 solves these problems – it is an addressable JTAG Multiplexer.
Long JTAG chains can be partitioned onto local scan ports (LSP) to reduce the size of the individual JTAG chains (divide and conquer).
FPGAs from a specific vendor can be placed on one chain to simplify the programming process.
DSPs or uPs can also be placed on a unique chain.
If FLASH is to be updated using JTAG this again is best placed on a small local chain.
The test engineer also has the flexibility to partition the system in a logical manner for efficient test – for example, optional daughters cards can be placed on a separate chain.
The SCANSTA111 JTAG Multiplexer partitions chains…
Smaller test vector sets – faster test times
Targeting specific devices for isolation
Faster configuration/programming times
Worldwide FAE Meeting
Delivered by: Ken Filliter

31. SCANBridge Multidrop & Mux
Here is a block diagram of the STA111.
Note that this device is both addressable and a complex JTAG mux.
Because it’s addressable a customer can place these devices in a multidrop configuration – such as a backplane. There are 7 address bits resulting in 121 unique addresses.
As a mux, this device supports 3 scan (JTAG) chains. So assuming a system with 10 cards, a customer could have an STA111 on each card and have a total of 3 X 10 = 30 scan chains. I refer to this device as a complex mux, because not only can any of the 3 chains be addressed, but if desired any combination of the 3 chains, for e.g. local ports 1 + 2, or or
Converts serial bus into a multidrop addressable environment
Supports up to 121 unique, 4 multicast, 1 interrogation, and 1 broadcast address.
3 configurable local ports.
Available in 48-pin TSSOP and 49-pin BGA.
Worldwide FAE Meeting
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32. Transparent Mode Target Emulation FPGA Configuration FLASH Programming
One of the primary modes of the device is “transparent mode”. In this case the device has been addressed and a chain selected. In transparent mode the device just acts as a buffer – typically for high-speed programming or emulation.
Worldwide FAE Meeting
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33. Bridge Mode Select Any Combination of SCAN Ports: Interconnect Test
Programming
Here is another example of how the device might be used; in this case we are accessing multiple local ports (LSPs) for interconnect testing between the 2 LSPs.
Worldwide FAE Meeting
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34. Park Mode
When Testing Chains involving multiple STA111s “PARK” is used as a stand-by state. Vectors are loaded into each chain and then “Parked”. A simultaneous EXTEST is then issued via Multicast. 1 X X 1 X
The final and most complex example is testing between cards. In this case test vectors can be loaded on both cards and put in a stand-by state known as “Park”. Then a multicast command is given to accomplish the board-to-board testing.
Note – this is necessary because of the serial nature of JTAG; we can only access one device over the backplane at a time.
Worldwide FAE Meeting
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35. STA111 Multi-drop Addressing
In this example we are showing 3 cards on a backplane. For multidrop use there are 121 unique addresses. The address is set by external pins. The address is sent down the JTAG serial chain, the Scan Bridge recognizes it’s unique address and turns on waiting for the next instruction. The other devices stand-by until they see their specific address.
IEEE
1149.1
Bus
7 bit address used to create 121 multidrop addresses
Worldwide FAE Meeting
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36. Simultaneous Programming
DUT
DUT
DUT
For multidrop applications it is possible to do simultaneous programming.
In this case the “multicast” address is used. Each Scan Bridge has a unique address, but it’s also possible to assign a multicast address as well.
Note that for simultaneous programming, the TDO serial return can not be verified. However the SCAN Bridge contains an LFSR that collects a signature. Each 32 bit signature can then be shifted out individually to verify the programming was correct.
IEEE
1149.1
Bus
Use multidrop addressing for simultaneous programming.
On-board LFSR used to collect signatures for verification.
Worldwide FAE Meeting
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37. From Board to System Test
The “Park” instruction allows 2 Scan Bridges to be included in a test, so it’s therefore possible to test point-to-point backplane connections and cables between cards.
It’s often convenient to place daughter cards on a separate scan chain, then if they are removed and it doesn’t affect any of the other scan chains.
Verify backplane, connectors and I/O with card to card backplane tests.
Test high speed card to card serial links
Test/Isolate optional daughter cards
Worldwide FAE Meeting
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38. STA111 Transparent Mode
In a multidrop application it’s still possible to support transparent. In this example to program the 3 FPGAs on the middle card, first the correct Scan Bridge is addressed, then the Bridge is placed in transparent, then the vectors sent.
IEEE
1149.1
Bus
Simple instruction connects single LSP for fast programming, configuration, and/or emulation.
Worldwide FAE Meeting
Delivered by: Ken Filliter

39. STA112 – 7 Port Addressable Scan Mux
7 Local Scan Ports
256 Multidrop Addresses
Transparent Mode for Emulation / Efficient ISP
Pass-Thru Bits support Flash ISP / eJTAG
Address masking for multi-master operation
TRST control for local or universal resets
Stitcher mode for manual LSP selection
100-Pin BGA, TQFP
So far we’ve been discussing our 3 port Scan Bridge, the STA We also have a more powerful device, the SCANSTA112. This device supports 7 local Scan chains.
The addressing and protocol between the devices is identical, however there are additional features on the STA112.
One important feature is that each local port on the device can be placed in transparent – for programming or emulation – via an instruction (software) or an external pin (hardware). This is especially handy in the lab.
Another popular feature is that one of the local ports can also be a “master” input. This is one way for the device to support both external or backplane masters and a local master.
Worldwide FAE Meeting
Delivered by: Ken Filliter

40. Programming FPGAs Connect to local port using either:
This slide is to emphasize the flexibility of 2 methods for the device to be placed in transparent mode. Especially in a lab setting having to load an address followed by a transparent instruction is inconvenient. External pins allow 1 or all of the local ports to be connected.
Connect to local port using either:
1.) External LSP enable pin
2.) Boundary Scan Instruction
Worldwide FAE Meeting
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41. STA Evaluation Kit Available on our website NOW!
Addressable STA111 cards
Perform card to card backplane and serial link testing
Backplane with IEEE and Signals
Interchangeable daughter cards
Our evaluation kit is available for sale on our website. It is example hardware to demonstrate the capabilities of the STA111/112 devices in a multidrop backplane.
It also shows off the at-speed BIST features of the LVDS SerDes.
This Evaluation kit requires software/hardware tools from a 3rd party ATPG vendor – see our website description for complete details.
Available on our website NOW!
Worldwide FAE Meeting
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42. Embedded 1149.1 Vector Delivery
Remote Test and Diagnostics
Remote (re)configuration
Embedded JTAG provides many attractive capabilities and is the most sophisticated use of the standard. Customers considering an embedded solution should have experience with JTAG and embedded system. This requires some development effort, but many of our customers are finding it worth the effort.
Worldwide FAE Meeting
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43. System & Embedded JTAG
Ability to remotely perform comprehensive testing including At-Speed BIST, interconnect, backplane and cable testing
Improved Reliability of the assembled product (system)
Better field diagnostics
Reduce No Fault - Found problem!
Potential for remote upgrades
Update Firmware, Boot code, add new features, respond to new standards.
Worldwide FAE Meeting
Delivered by: Ken Filliter

44. In-System SCAN Tester SCANSTA101 SCAN Master
/TRST
TMS
TCK
TDI
TDO
TAP
(Test Access Port)
SCAN
Tester
SCANSTA101
Embedded SCAN Test Master
SCANSTA101 works with microprocessor/controller plus memory to provide an embedded in-system SCAN tester
Enables
system self-test
system (re)configuration
system remote diagnostics & upgrades
The SCANSTA101 Embedded JTAG Test Master allows the customer to build an embedded JTAG tester. The SCANSTA101 in combination with a microcontroller or microprocessor plus memory can be embedded in the system to allow the system to perform self-diagnostics and (re)configuration. The SCANSTA101 interfaces between the microcontroller or microprocessor and the serial JTAG bus. It drives the JTAG bus and off-loads some work from the processor or controller.
This embedded “test master” is not as sophisticated as a PC loaded with ATPG software (these will still be required during manufacturing/test), but does enable a host of in-field features such as system level test, remote upgrades, reading of diagnostic registers, etc.
National provides SCANEASE software and also ANSI C drivers to simplify software development for the SCANSTA Embedded JTAG requires some knowledge of embedded systems so should only be encouraged of sophisticated customers who understand the requirements.
Worldwide FAE Meeting
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45. SCANSTA101 Block Diagram
16-bit Parallel to IEEE Serial data conversion
Dual port memory acts as a cache between PPI and SSI
On-board Sequencer, Compares, and Macros for multivector operations
3.3v Supply Voltage
49-pin BGA package
The SCANSTA101 is essentially a parallel to serial converter that understands IEEE protocol. The STA101 accepts 16 bit JTAG vectors from the uP and converts these into the serial JTAG vector format. The device contains an on-board FIFO to enable it to buffer the incoming vectors. The architecture of the device is intended to minimize the interaction with the uP.
Worldwide FAE Meeting
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46. SCANEASE
SCANEASE is our proprietary (freeware) software that converts test and programming vectors (SVF) into binary Embedded Vector Format (EVF)
SCANEASE also includes embedded C code for driving the STA101
When customers invest time and resources developing SCANEASE solutions this becomes an excellent barrier to competition for us !
Note that as Freeware – we don’t have an obligation (or resources) to support small opportunities.
SCANEASE is our proprietary software that supports the STA101.
SCANEASE includes a couple of different modules. One portion is SVF2EVF that converts SVF test or programming vectors into our proprietary embedded format EVF. A 2nd portion is ANSI C code and is loaded into the uP to enable the uP to interact with the STA101.
SCANEASE is freeware and is available from our website. Because this is freeware we need to be aware of the support needs of customers. For large opportunities we can assist with the use of SCANEASE (and the STA101), however for small opportunities we don’t have the resources necessary – (and this being freeware we do not have an obligation !)
SCANEASE is written exclusively around the STA101 architecture. Therefore as customer develop familiarity and expertise with SCANEASE this is a very powerful barrier for other vendors to overcome.
Worldwide FAE Meeting
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47. Embedded Development Process
CPLD Config File
BSDL
Net
List
Net
list
Vector Conversion
to EVF2
STA101
Knowledge
and
Format Conversion
1149.1
Knowledge
ATPG
Embedded Environment
JAM
SVF
Vector
Delivery
Engine
STA101 Drivers
(Reads EVF2)
The typical flow for vector generation is shown in this slide. For test vectors, the device specific BSDL models and the board net list are input to the ATPG tool that generates a vector file in SVF (or some other format). In the case of programming files they also are created and/or converted into SVF. For non-embedded applications these SVF files are run on a programmer or JTAG tester.
For embedded applications the SVF is converted by SCANEASE into our binary EVF format for storage in the system. SCANEASE is also loaded into the embedded uP to provide the drivers for the STA101
SCANEase
v2.0
I/O Drivers
(Talks to hardware)
1149.1
1149.1
External
Embedded
Worldwide FAE Meeting
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48. Embedded Test Solution
MEMORY
FPGAs
ASICS uP
STA101
Here’s an example of how an Infra-structure customer might set up his system JTAG solution. First lets’ assume the customer wants access for a variety of purposes during different stages of the product life.
JTAG test is required during manufacturing using ICT or PC based testers. Once in the field the customer would like to have this same test capability but using stored vectors driven by the local STA101 Master.
FPGA programming at boot will use the JTAG Master and the on-board Flash memory.
At other times for redundancy, or perhaps to load different code or a different vector set, vectors may be supplied over the backplane.
If the Flash code needs to be updated, this could also be accomplished using vectors downloaded and sent via the backplane.
Connector
External Tester
STA112
Backplane Bus
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49. Embedded Test – Factory Test
MEMORY
FPGAs
ASICS uP
STA101
This is the factory test set-up, the Orange arrows represent the test vectors being driven by an external tester. Note that the uP and STA101 are also tested via JTAG.
Connector
External Tester
STA112
Backplane Bus
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50. FPGA Programming in the Field
MEMORY
FPGAs
ASICS uP
STA101
Now we’re looking at a fielded system. Programming vectors (Orange) are taken from local memory, driven by the STA101 and used to program the FPGA chain.
Connector
External Tester
STA112
Backplane Bus
Worldwide FAE Meeting
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51. Test in the Field (local vectors)
MEMORY
FPGAs
ASICS uP
STA101
Cards in the field may be tested at start-up, periodically or in the event of a failure. Typically test files are relatively small and can be stored locally.
This arrangement can test all of the card (orange vectors) – with the exception of the STA101 and uP.
A typical test would involve BIST on all the complex digital devices, with a pass /fail signature and interconnect testing. If an STA476 was on board this could also include power supplies.
Connector
External Tester
STA112
Backplane Bus
Worldwide FAE Meeting
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52. Field Test or Programming (Remote Vectors)
MEMORY
FPGAs
ASICS uP
STA101
In this example we are getting vectors over the backplane.
Perhaps there is a fault in this cards JTAG Master capability.
Or the card is off-line and we are testing the uP and STA101 chain with a redundant card (that chain can not test itself).
We may be using alternate FPGA code from a different source, or different or expanded test vectors.
In any case we have the flexibility to accomplish all of the above.
Connector
External Tester
STA112
Backplane Bus
Worldwide FAE Meeting
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53. Updating Local Flash (Remote Vectors)
MEMORY
FPGAs
ASICS uP
STA101
The ability to remotely update Firmware is very useful in Infrastructure. In this case we are reprogramming the Flash on this card with vectors obtained remotely and sent down the backplane.
Few Flash devices support JTAG so the process requires using the JTAG chain in the adjacent devices to drive the memory address and data busses.
Connector
External Tester
STA112
Backplane Bus
Worldwide FAE Meeting
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54. Testing Differential Signals
Now let’s discuss the challenges using JTAG to test differential signals.
IEEE1149.6
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55. Testing Differential Signals
Typical high-performance card may have hundreds or thousands of differential connections.
Functional pass/fail testing can only identify a fault condition (no diagnostics)
Structural Diagnostics are needed to immediately identify failing component.
IEEE was designed for static TTL testing
Fault models not sufficient for transmission lines.
Extensive use of AC coupling renders IEEE unsuitable for differential signals.
High-speed differential signals have become the backbone of modern Infrastructure. A single high performance FPGA may have over 100 LVDS diff pairs, thus a complex card may have over 1,000 differential nets.
Functional testing can generally detect a fault condition but without diagnostics.
IEEE is an excellent tool for testing and diagnosing digital nets, but was designed for static TTL level nets. AC coupling is used extensively in high-speed differential rendering IEEE (dot 1) unsuitable.
Clearly a new approach is needed for differential nets.
Worldwide FAE Meeting
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56. Differential Fault Spectrum
LVDS
Driver Rt
LVDS
Rcvr F5 F8 F2 F6
Here we see pictorially the types of faults boundary scan (JTAG) is expected to detect. On the left hand side we have single ended TTL signals, and F1, F2 and F3 indicate shorts (F1), open (F2) and short between lines (F3). In the TTL world these faults can be modeled as “static faults” with no time domain consideration. There are excellent well established fault models and test patterns for detecting these faults.
It gets more complicated once we get into differential signals. Note that F4 thru F9 are the same types of faults, opens & shorts, but what has changed is this is now a transmission line environment. The length of the traces or cables introduce a time dependent variable not taken into consideration with the single ended TTL fault models. F3
LVDS
Driver
LVDS
Rcvr Rt F7 F9
TTL
LVDS
TTL
Worldwide FAE Meeting
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57. Fault: Open at +Tx terminal
Upon switching, line capacitance will draw i even with open
Sensitive Receiver may only require 30mV spike to switch F7 F7 Tx Rx
F7 represents an open on a single LVDS channel.
Let’s see how this defect affects operation. Initially as the device switches and the negative channel turns on, the driver sees only a capacitive load and current will flow to charge the line. The receiver will see this current and typical sensitivity is in the 10s of mV. 250uA of current would generally be sufficient to switch the receiver. When the device switches to the opposite polarity the current would then discharge and switch the receiver.
Depending on the frequency of operation and the capacitance of the line this circuit might appear to operate correctly even with a gross fault such as an open.
Testing this circuit with patterns of ones and zeros at JTAG speeds of 1 to 10 MHz would likely not uncover this time dependant fault.
Typical patterns of 1s and 0s will not always detect F7
Worldwide FAE Meeting
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58. IEEE 1149.6 New standard compatible with pervasive IEEE1149.1
Developed to tackle two specific existing test problems with differential signals:
Insufficient coverage of conventional dot 1.
Use of AC Coupling that makes dot 1 tests completely ineffective.
As described in the previous slide, static tests developed for single ended circuits are ineffective in transmission lines – i.e. differential circuits.
An even more serious problem comes when these circuits are AC coupled, in that case static (DC) tests are completely ineffective. AC coupling is a very common technique for high-speed signaling above 1 Gbps and is specified in as a requirement in many of the high-speed standards. (e.g. PCIe, ATCA).
Cisco recognized this several years ago and pushed for a new standard for differential signaling, compatible with dot1 and delivering the same speedy fault detection and excellent diagnostics…..this became IEEE1149.6
Worldwide FAE Meeting
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59. DC Coupled State Transmitter Receiver TX RX Update DR Select DR
Capture DR
Here we see a DC coupled circuit and a transmitter switching low to high; there is some small line and prop delay and then the receiver follows switching low to high. If this was a boundary test the BSR register in the receiver would record this result. If you recall the TAP state machine there are often several states that must be sequenced thru before the actual flipflop is updated i.e. “Capture DR” This delay doesn’t matter however because the receiver value stays constant.
Next we look at the AC coupled situation.
Transmitter
Receiver
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60. AC Coupled C State Transmitter Receiver TX RX Update DR Select DR
Capture DR
Same scenario as last slide, the receiver transitions Low to High, however in this case we have a coupling capacitor. The cap passes the (high f) edge but then blocks the DC component. At the receiver we see a spike from the edge and then a decay based on the RC time constant.
If this was a boundary scan test the TAP would be moving thru the state machine as shown. However in this case depending on the clock (TCK) speed the result changes as the signal decays.
An IEEE test methodology is unreliable.
Transmitter
Receiver
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61. IEEE1149.6 – New STD Edge Detectors Pulse Generator & BSR VREF
An IEEE working group studied the problem and developed a solution for differential (and AC coupled) that became IEEE1149.6
The solution was to use edge detectors in the receiver and to have the BSC in the transmitter send pulses (rather then static HIs/LOs)
Edge detectors were also added to both polarities of the differential pair to improve the diagnostic capability.
Because the BSC in the receiver is now searching for edges, the test methodology works for AC coupled nets.
A very important consideration is that IEEE uses the exact same protocol and TAP as IEEE1149.1, making it completely compatible.
Pulse Generator & BSR
Supports IEEE Interconnect
Edge Generation/Detection for AC coupled tests
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62. Tx Rx AC Extest Waveform
This slide shows the IEEE (dot 6) waveforms as they leave the transmitter and then the waveform at the receiver after passing thru the coupling capacitor. Tx Rx
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63. Defects Targeted by Dot6
TX1 pin1 open
C1 pin2 open
RX1 pin1 open
TX1 pin1 short to VDD
TX1 pin1 short to GND
TX1 pins 1,2 shorted together
C1 pins 1,2 shorted together
8. C1 pin1 short to C2 pin2
9. RX1 pin1 short to VDD
10. RX1 pin1 short to GND
11. RX1 pins 1,2 shorted
12. TX1 pin1 short to TX2 pin1
13. RX1 pin1 short to RX2 pin1
14. R pin1 open
Here we see a standard AC coupled termination scheme and the various “stuck-at” defects that might occur.
The intent of the IEEE standard was to not only be able to detect these faults but provide very accurate diagnostic information.
Worldwide FAE Meeting
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64. IEEE1149.6 Fault Dictionary Both lines low Static low
F11. T+ short to R-
Shorted cap NOT detected
IN-
IN+
F10. T+ short to R+
Failure on TR+
F9. R+ short to VDD
F8. R+ short to GND
F7. R+ short to GND
F6. R+ open after RTERM
TR+ 180o out of phase, TR+ = TR-
F5. R+ open bef. RTERM
F4. T+ short to VDD
F3. T+ short to GND
F2. T+ short to T-
F1. T+ open
Comments
TR-
TR+
Faults
This chart shows the type of fault followed by the response expected at the 2 edge detectors. Vendors creating diagnostics for IEEE use this table to create diagnostics – based on the response of the two edge detectors the specific defect can be established.
Worldwide FAE Meeting
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65. Fault Response F3 (T+ to GND)
This slide looks complicated but if we examine the waveforms from the top down we’ll get a good understanding of how IEEE works.
In this example we are showing the IEEE test response to a fault at the transmitter, the positive terminal being shorted to Ground.
The top waveforms show the positive and negative waveforms at the transmitter. The T+ signal stays close to zero (due to the short), while the T- switches normally.
The 2nd set of waveforms are at the Rx. As expected they follow the Tx+ and Tx- waveforms.
The 3rd waveform is the output of the Rx. As discussed earlier the Rx responds to a very small differential and follows the Tx. To an observer looking at the Rx output nothing appears wrong.
In the 4th set of waveforms we see the response of the R- edge detectors. They respond to both positive and negative edges of the waveform.
The bottom signal is the R+ response and the edge detectors detect no signal indicating a fault condition.
The diagnostic software would then review these results and be able to identify the fault conditions that would cause this response.
Worldwide FAE Meeting
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66. (Differential Signals)
Devices with IEEE1149.6
(Differential Signals)
We currently offer 4 devices with IEEE Infrastructure designers are generally encouraged to select devices with JTAG and especially IEEE
These dot 6 devices have an ASP premium and are much harder to replace by our competition.
Worldwide FAE Meeting
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67. DS15MB200 & SCAN15MB200 (Redundancy for High Availability Systems)
Separate Pre-emphasis control for each channel
Enable for each channel allows electronic keying
Replaces Four 2*2 crosspoints
14 ps typical total jitter at 1.5 Gbps
IEEE (SCAN15MB200)
DS15MB200(1 channel)
SWITCH FABRIC
LINE CARD
Primary
The Mux-Buffer function is intended to support the redundancy requirements of high-availability equipment. As shown in the example, signals are routed to and from redundant switch cards from each line card, so the system can operate in the event any one card failed. The mux buffer function is optimized and is much more efficient then crosspoints that are often used in this capacity. Note, this device replaces 4 2 X 2s or 2 4 X 4s.
The SCAN15MB200 has extremely low jitter, selectable pre-emphasis for driving lossy media, separate enables for each line enabling electronic keying (as required by ATCA for e.g.)…..and IEEE !
Back-Up
Normal Operation
Failover Mode
Worldwide FAE Meeting
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68. SCAN90CP02 LVDS Crosspoint Switch
1.5 Gbps, low jitter data path
Non-blocking architecture
Pin-configurable pre-emphasis for longer drive distance
IEEE & JTAG
3.3V supply
32 LQFP & 28 pin LLP package
Available NOW
We also offer dot 6 on our SCAN90CP02. We now offer much higher performing 2 X 2s such as the DS10CP152/DS25CP102 so this device is attractively priced and offers moderate performance.
IEEE and selectable pre-emphasis are the major features.
Worldwide FAE Meeting
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69. SCAN90004 - Quad LVDS Buffer with Pre-emphasis & 1149.6
1.5 Gbps data rate per channel
Configurable pre-emphasis drives lossy backplanes and cables
LVDS/CML/LVPECL compatible input
On-chip 100Ω input terminations
8 kV ESD protection
IEEE and compliant
Fault Insertion
Industrial -40 to +85°C temp range
Small TQFP Package Footprint
Evaluation Kit Available
For non-JTAG version, see DS90LV004
The SCAN90004 is a Quad LVDS Buffer – a very popular function.
Major features are pre-emphasis, High ESD, wide LVDS common mode, and of course IEEE1149.6
Worldwide FAE Meeting
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70. SerDes SCAN25100 CPRI Base Station SerDes
The CPRI Ser/des is targeted at 3G base stations and offers a variety of compelling features including remote delay calibration for external radio heads.
CPRI = Common Public Radio Interface
RRH = Remote Radio Head
Worldwide FAE Meeting
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71. Mixed Signal testing with IEEE1149.1
Analog Testing
Mixed Signal testing with IEEE1149.1
IEEE (dot 1), JTAG is a very powerful solution for digital test and has become hugely successful. There is one drawback and that is there is no provision for Analog testing.
A parallel effort was launched in the early 90s for an Analog standard and that became IEEE The dot 4 standard is still being worked on and doesn’t look like it will ever be a commercially viable standard.
There is another approach – using an ADC to measure Analog signals and putting the digital result in a JTAG register for use with the digital test results.
This approach is available from NSC and is the SCANSTA476.
Worldwide FAE Meeting
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72. Test Options for Digital Boards
Analog
Comments
ICT
Expensive fixtures, moderate coverage
Clumsy and time consuming but tried and true approach
PC Inexpensive NONE ! Risky - No Analog Test
PC +ICT Inexpensive Expensive Two test steps
Let’s look at the options available for testing digital boards. ICT is the standard approach and ICT can support both JTAG and standard test points, Digital and Analog. ICT is limited in the number of channels and is not the most efficient solution – also requires expensive fixtures and lengthy development time
An alternative tried by some companies is to use cheap PC based JTAG testers. These are fine for digital testing and offer many advantages. One big problem though is no analog testing – such as power supplies. If there is an Analog problem there is zero test coverage & zero diagnostic help.
PC and ICT can be combined, using the cost effective PC for the digital JTAG portion and ICT for the non-JTAG and Analog testing. This requires 2 test steps.
A 4th option is to use the SCANSTA476 to measure the Analog portion – typically power supplies on a digital board. In this case we use the quick and efficient PC based tester to cover both Digital and Analog test – and eliminate the ICT.
PC Inexpensive Inexpensive Brilliant – eliminate ICT !
Worldwide FAE Meeting
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73. SCANSTA476 IEEE1149.1 (JTAG) Analog Voltage Monitor
Eight selectable Analog input channels
Analog full-scale input range 0V to VDD
Small package footprint in 16-lead, 5 x 5 x 0.8 mm LLP
Single +2.7V to +5.5V supply operation
IEEE (JTAG) compliant interface
Analog
Inputs
Digital
Output
The SCANSTA476 is an 8 channel Analog Voltage Monitor that has 8 analog inputs, selectable via a mux, fed to an ADC and the digital result stored in a JTAG register.
This device is fully compliant with the digital IEEE (dot 1) standard and can sample the full rail from 0 Volts to Vdd.
The tiny 16 pin LLP is 5 mm square.
Worldwide FAE Meeting
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74. SCANSTA476 IEEE1149.1 (JTAG) Analog Voltage Monitor
Inputs
Digital
Output
Eight unique instructions select each of the inputs for sampling
Digitized output is 12 bits.
Due to parallel to serial conversion and TAP overhead, 20 MHz TCK results in 1 Msps sampling rate.
A unique JTAG instruction triggers the sampling of each of the 8 channels and the effective sampling rate is a maximum of 1 Msps.
The ADC is a 12 bit SAR.
Worldwide FAE Meeting
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75. Advanced Packaging Small Footprint Essential
The SCANSTA476 is offered in a small LLP and is supported with an EVK.
Small Footprint Essential
Package shown is 5 mm on a side
Worldwide FAE Meeting
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76. Typical Applications
Power supply measurement for Boundary Scan only Test solutions. (Eliminate ICT !)
Voltage Measurement Capability during board/system environmental testing.
Access to Analog nodes without physical access
On-line testing for Health Monitoring and Prognostics.
This device is used by both Nokia and Motorola in 3G base stations for monitoring power supplies during board level testing. Complex boards often require numerous supplies – 5, 3.3, 2.5, 2.2, 1.8V etc., and dedicated supplies for some components. One card had 16 supplies and 2 SCANSTA476s were used to monitor the card.
Assuming the system had embedded JTAG capability then the STA476 could also be used for monitoring voltages in the field, to identify & diagnose field failures but possibly predict failures due to voltage drift….the area of prognostics.
Worldwide FAE Meeting
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77. Summary
Our infrastructure customers currently use JTAG extensively for a variety of purposes
NSC offers a comprehensive solution that supports multiple scan chains, embedded JTAG master, software support for vector conversion, IEEE1149.6, and Analog Test !
Often customers have different requirements and priorities – our flexible solution supports a wide spectrum of needs – and is well supported by 3rd party software vendors.
Worldwide FAE Meeting
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78. Worldwide FAE Meeting
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79. Differential Signals are best tested using…
System Level JTAG
Differential Signals are best tested using…
IEEE1149.1
IEEE1149.4
IEEE1149.6
IEEE1532
Answer: C 10
Worldwide FAE Meeting
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80. IEEE1149.1 (JTAG) is often used for ….
System Level JTAG
IEEE (JTAG) is often used for ….
Digital TEST
FPGA & Flash Programming
Emulation of DSPs and uPs
All of the Above
Answer: D 10
Worldwide FAE Meeting
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81. 10 System Level JTAG ATPG (Auto-Test-Pattern-Generation)
SCANEASE is used for
ATPG (Auto-Test-Pattern-Generation)
Converting SVF vectors to EVF
Emulation
All of the Above
Answer: B 10
Worldwide FAE Meeting
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82. SCANSTA476 Analog Voltage Monitor supports…
System Level JTAG
SCANSTA476 Analog Voltage Monitor supports…
Analog test with digital IEEE std.
Analog JTAG standard IEEE1149.4
Doesn’t use JTAG but allows Analog Test
Ross Perot
Answer: A 10
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83. The weakness of Functional testing is
System Level JTAG
The weakness of Functional testing is
lack of diagnostics
development time
requires expensive hardware
lengthy test time
Answer: A 10
Worldwide FAE Meeting
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84. 10 System Level JTAG a download from the website created by SCANEASE
The protocol to address and configure an NSC SCAN Bridge (STA111 or STA112) is..
a download from the website
created by SCANEASE
is a simple but manual process
generated by 3rd party ATPG
Answer: D 10
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85. FLASH Programming via the JTAG bus uses..
System Level JTAG
FLASH Programming via the JTAG bus uses..
internal JTAG registers
STA476 and SCANEASE
JTAG registers from an adjacent device
IEEE and SCANEASE
Answer: C 10
Worldwide FAE Meeting
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86. Which FPGA vendor(s) promote JTAG programming
System Level JTAG
Which FPGA vendor(s) promote JTAG programming
Xilinx
Altera
Lattice
All of the above
Answer: D 10
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87. The STA112 SCAN Bridge does NOT support
System Level JTAG
The STA112 SCAN Bridge does NOT support
multidrop scan chains
multiple scan chains
multiple I/O levels
multiple JTAG Masters
Answer: C 10
Worldwide FAE Meeting
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88. Analog testing is NOT possible with
System Level JTAG
Analog testing is NOT possible with
IEEE and a PC with ATPG tools
ICT with JTAG conversion kit
SCANSTA476
IEEE and associated hardware
Answer: A 10
Worldwide FAE Meeting
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89. Worldwide FAE Meeting
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90. Team Scores
Team 1
Team 2
Team 3
Team 4
Team 5