1. SERIAL MULTIPLIER Part 1
Lab 5 Preview
SERIAL MULTIPLIER
Part 1

2. Objective To design the components of a Serial Multiplier, namely:
A 4-bit Full Adder
A Control Unit
A Modulus-5 Counter
A Shift Register

3. Part A
A 4-bit Full Adder

4. How to start? Sketch the black box view of a 1-bit Full Adder.
Design a 1-bit Full Adder (Or, you can also use the same one from your Lab 3 Multiplier).
Symbol it.

5. 4- bit FA Black Box View Cin A0 4 Bit Adder S0 A1 S1 A2 S2 A3 S3 B0
Cout

6. Design a 4-bit Full Adder (by cascading the previous 1-bit FA)
Cin
Sum
Cout A0 A1 A2 A3 B3 B2 B1 B0
Cin
Connections??!!
Hints :
Sum o/p from each FA is connected to your S o/p.
Cout o/p is from your MSB Cout FA.
Cin for each FA is from Cout of previous FA. S0 S1 S2 S3
Cout

7. Then…
Create a default Symbol for your 4-bit FA.
Simulate your design.

8. Simulation Requirements
Your simulation is by adding 2 numbers (each is 4-bits wide)
Fix your A input (Example : = 910)
Vary your B input (0 to 15)
Your simulation should add the number accordingly.
9+0= 0
9+1=10
9+2=11
9+3=12
9+4=13 ……
9+15=24

9. Part B
A Control Unit

10. Control Unit State Diagram_ X
011
010
001
000
101
100
LOM = 1
LOD = 1
LO = 1
SHIFT = 1
READ = 1
Control Unit State Diagram
If reset = 1 
go to state 001 for
all states.
Only high outputs are shown for every state, the rest consider as ‘0’.

11. Control Unit Black Box View
Inputs are: CLK, RESET and X.
Outputs from FFs are: Q2, Q1 and Q0.
Other outputs are: LOM, LO, LOD, SHIFT and READ.
CONTROL
UNIT

12. Control Unit State Table
From the state diagram given, produce a State Table, using ___ flip-flop.
3-bits output with X as its control input.

13. Control Unit Block Diagram
CLK
D-FF Q2 Q0 Q1
LOM LO
LOD
READ
SHIFT
RESET X
Connections!!??
Create as symbol
Simulate your design
Hints:
LOM = High when Q2,Q1 and Q0 = 000
LO = High when Q2,Q1 and Q0 = 001
LOD = High when Q2,Q1 and Q0 = 010
SHIFT = High when Q2,Q1 and Q0 = 100
READ = High when Q2,Q1 and Q0 = 101

14. Control Unit Simulation Results
Your simulation should look similar to this
Input is clk, x and reset (predetermined by you)
When x is 0 = Q(2..0) will count from 1 to 4 only
When x is 1 = Q(2..0) will count from 1 to 5, and will stay at 5 until reset is = 1
LOM=High when Q(2..0) = 0
LOD=High when Q(2..0) = 1
LO = High when Q(2..0) = 2
SHIFT = High when Q(2..) = 4
READ = High when Q(2..0) = 5 and condition x=1

15. Part C
A Modulus-5 Counter

16. Modulus-5 Counter State Diagram
If reset = 1 
go to state 001 for
all states.
Only high outputs are shown for every state, the rest consider as ‘0’.

17. Modulus-5 Counter Black Box View
Inputs:
CLK and RESET
Outputs:
Y0, Y1, Y2 (from FFs) and X.
MODULUS-5
COUNTER

18. Modulus-5 Counter State Table
From the state diagram given, produce a State Table, using ___ flip-flop.
This counter will count from 0,1,2,3,4 and stays at 4 until reset is HIGH.
Once Reset is HIGH it will count back from 0.
X is the output to drive your X input of the Control Unit.
X is HIGH when counter is at 4 (100).

19. Modulus-5 Counter Block Diagram
CLK
TFF Y0 Y0
RESET Y1 Y2
TFF X Y1
Connections!!??
Create as symbol
Simulate your design
Hints :
X = High when Y2,Y1 and Y0 = 100
TFF Y2

20. Modulus-5 Counter Simulation Results
Your simulation should look similar to this:
Your counter should count from 0 to 4 (MOD-5) but stays at 4 until reset = 1.
Reset =1 at anytime shouldl also bring the counter back to start counting from 0.

21. Part D
A Shift Register

22. Shift Register reVieW How many bits? _____ ? Shift to the ______ ?
Name the Shift Register below = ______ ?
MI[3..0]
IN[4..0]

23. Shift Register Black Box View
LOM = load MI [3..0] into register
LO = load IN [3..0] into register.
SHIFT = work as clock for register.
RESET = set to initial state.
MI = input multiplier
IN = output from 4 bit adder
RESET
LOM
SHIFT LO
IN [4..0]
MI [3..0]
O [8..1]
LSB]
SHIFT REGISTER

24. Shift Register Schematic Diagram

25. Shift Register Simulation Results
Fix your input for MI and IN, e.g. MI = 9 and IN = 7
Output is Q8, Q7……Q1 and LSB:
Once LOM = 1; 910 or will be loaded into Q[3..0].
Once LO = 1; 710 or will be loaded into Q[8..4].
Every PGT of SHIFT, the Output Q[8..0] will SHIFT RIGHT.
Untill all shift occurs, Q[8..0] will be zero.

26. gOOd LucK