1. Multi-level Inverter Prepared by : Anas Ibrahim Yazeed Hawasheen
Waleed Barri
Supervisor:
Dr.Raed Jaber

2. Chapter 1 : Introduction
1.1 : Back ground
1.2 : Topology.
1.3: Modulation methods :
1.3.1 : staircase modulation.
1.3.2 : pulse width modulation.

3. 1.3 : Modulation methods 1.3.1 : staircase modulation :
The basic idea of the staircase modulation is to pre-determine the switching angle for each module to get the sinusoidal waveform at the output.

5. 1.3.2 : pulse width modulation
This modulation technique compared between two signals (triangular and sinusoidal )
Triangular : controlled the duty cycle of each pulse .
Sinusoidal : controlled the frequency of the output wave .

7. Chapter 2 : working principle
Positive output voltage :

8. Negative output voltage :

9. Chapter 3 : Methodology 3.1: staircase modulation .
3.1.1 : five level inverter .
3.1.2 : nine level inverter .
3.2: compression between five and nine level inverter s
3.2.1 : Fourier series of five level inverter .
3.2.2 : Fourier series of nine level inverter .

10. 3.1 : staircase modulation
Staircase modulation is a very suitable technique for multilevel inverter :
employing this technique along with the multilevel topology will decrease the total harmonic distortion (THD).
as the number of levels increases the total harmonic distortion will decreases because the signal becomes more similar to the sine wave.

12. 3.1.1: Five level inverter
In five level inverter the idea is to produce five different output voltage levels.
Applying an odd symmetry will eliminate the even harmonics component.

17. 3.1.2: Nine level inverter
The procedure that we follow in nine level inverter will not be differ but here we allowed to produce 0V,12V, 24V, 36V, 48V,-12V,-24V,-36V and-48V over a complete cycle, so the number of levels increases this will reduce the total harmonic distortion.

22. 3.2: compression between five and nine level inverters
The main advantage of using nine level inverter over five level inverter is to reduce the total harmonic distortion (THD).
The total harmonic distortion is the degree to which a waveform deviates from its pure sinusoidal values as a result of the summation of all these harmonic elements and it is defined as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency.

24. 3.2.1: Fourier series for five level inverter.
For voltage :

26. For current:

27. 3.2.2 : Fourier series for nine level inverter
For voltage :

29. For current :
In the previous four figures we see clearly that the total harmonic distortion was reduced by 10%for voltage and 6% for current.

30. Chapter 4 : power calculations
4.1: Apparent power 4.2:Output and input real power 4.3: Power factor 4.4:Motor Efficiency

31. a single phase motor will be added to calculate the real power and power factor and efficiency.
the dc voltage from the two sources will changed to 36V and 108V respectively to meet the ratings of the chosen motor.
The motor rating

32. 4.1 : Apparent power
In this case we are dealing with a signal which have a lot of harmonics so it’s not true to say that Vrms is peak voltage divided by the square root of 2 .

33. Where :

35. By using matlab simulink :

36. 4.2: input real power

37. 4.3 : power factor
Power factor is the ratio between real power and apparent power in a circuit. The formula for power factor s:

38. 4.4 : Motor efficiency
In general, efficiency is a measurable concept, quantitatively determined by the ratio of output to input .

40. Chapter 5 : Effects of harmonics on a single motor :

41. Chapter 6 : Method of harmonic elimination
This method is based on changing the switching angle in order to reduce the total harmonic distortion. In 9 level inverter there are 4 switching angle that can be adjusted so that the harmonics with higher losses can be eliminated, the Fourier series for the output of nine level inverter can be shown below

42. Know we try to eliminate the harmonics with higher losses or to reduce as possible which is 3th, 5th and 7thharmonic so we need 4 equations:

43. Where V1max is the voltage due to the fundamental component
Where V1max is the voltage due to the fundamental component. After solving the above four equations using matlab it will gives the following results:

44. The output voltage and current waveform and the total harmonic distortion for the current and voltage wave form after elimination can be seen in the following figures:

46. 6.1 : Effect of THD reduction
We can see clearly that the harmonic distortion of the voltage and current waveform reduced by 50% approximately, as a result of increasing the peak of the fundamental component and decreasing the amplitude of the fifth, third and seventh harmonics. The losses due to increasing of the stator and rotor resistances becomes smaller approximately becomes 2-4watt, so the efficiency must be increase

48. Chapter7: Mosfet power losses calculation

49. Pconduction(avg)= duty cycle * * on-state resistance
Conduction losses are the losses that occur while the mosfet or freewheeling diode is on and conducting current, the total power dissipation during conduction is computed by multiplying the on-state resistance and the on-state current. In switching applications the conduction loss must be multiplied by the duty factor to obtain average power dissipation.
Pconduction(avg)= duty cycle * * on-state resistance
For irf830 mosfet the on state resistance = 0.7 ohm this value can be calculated from the slope of the carve that shows the relation between Vds(on) and drain current in the mosfet datasheet.
For rms current equal 2.9A) simulation result)
The duty cycle will be equal =Ton/T total but we have different values because of different width of the cycles. So to calculate the losses due to conduction we have to divide the width of each pulse when the mosfet is on over the overall width.

50. Referring to the following table the first mosfet as an example is turned on five times but with different pulse time so the power dissipated by the first mosfet can be calculated as the following:

51. Pconduction1 = Pat 10V+ Pat 30V+ Pat 40V+Pat -20V+ Pat -30V
The pulse width of each cycle can be shown in the following table, where the frequency is 60HZ so the total width is second.

52. P 1 at 10V = 0.067**0.7 = 0.39 Watt
P 1 at 30V = **0.7 = 0.8 Watt
P 1 at 40V = **0.7 = 0.94 Watt
P 1 at -20V = **0.7 = 0.58 Watt
P 1 at -30V = *2.9*0.7 = 0.8 Watt
The power dissipated through the first mosfet due to conduction losses can be calculated as:
P1 conduction = ( ) = 3.5 Watt

53. The following table shows conduction losses due to each mosfet:

54. Chapter 8: Dead time effect
8.1 :Gate resister effect
8.2:Effect of drain current

55. Sometimes dead time will be calculated from typical datasheet values just multiplying by a safety factor from field experience. This method will work in some cases but is not precise enough in general. With measurements shown here, a more precise approach will be presented.

57. 8.1:Gate resister effect
The choice of gate resistor will have significant impact on switching delay time. Generally to say, the larger the resistor is the longer the delay time will be. It is recommended to measure delay time with dedicated gate resistor in application. A typical switching time vs. gate resistor value diagram is shown in the following figure

59. 8.2:Effect of drain current

60. Tdead-time = 1.2*(Toff-max-Ton-min)
Know the question is how to calculate the correct dead time?
This can be done by connecting the gate resistance that we selected which is 10 ohm to the ir2110 gate driver and seeing the output of the mosfet at no load when it’s switched- off after that we will multiply by a safety factor equal 1.2:
Tdead-time = 1.2*(Toff-max-Ton-min)

61. From the figure shown above the time needed for mosfet to switch off is 125ns and the minimum time needed to switch on from the datasheet of irf830 mosfet is 8.2ns substitute this values into the equation below the time needed to provide is:
Tdead-time=1.2*( ) = 140ns

62. Chapter 8:Hardware Design
8.1:Gate driver selection
8.2:Bootstrap circuit design
8.3:Gate resistor selection
8.4:Gate source resistor selection
8.5:PCB circuit

63. 8.1:Gate driver selection
We need gate driver because the maximum voltage that can supplied by arduino is only 5 volt which is not enough to operate the mosfet at saturation region.
The gate signal must referenced to the source which can be provided by the driver .

64. 8.2:Bootstrap circuit
One of the most widely used methods to supply power to the high-side drive circuitry of a gate driver IC is the bootstrap power supply. The bootstrap power supply consists of a bootstrap diode and a bootstrap capacitor; this circuit is illustrated in Figure (7.3).

65. Bootstrap Operation
The working principle of the bootstrap circuit is very simple the bootstrap capacitor will charge during Q2 is on and Q1 is off through the power supply VDD and bootstrap diode D1 the current flows shown in figure

66. When Q2 is off and Q1 is on the bootstrap capacitor is disconnected from the supply VDD because of the reverse biasing of D1 and the current will pass through the mosfet Q1 to maintain the high side drive operation, this can be seen clearly in figure shown below

67. Selecting bootstrap component
While it is a simple circuit, the bootstrap can be problematic if not designed correctly. In particular, care must be taken to ensure low CB ripple to avoid triggering the driver's under voltage lockout, which can halt converter operation; additionally, the refresh period must be sufficient to fully charge CB

68. QC = Qg+ (D.C * Tcycle * current from bin VB)
The information must be taken from the ir2110 gate driver where the under voltage lockout is 7V and maximum current supplies by pin VB equal 0.34mA under VCC voltage equal 12V the gate charge for irf830 mosfet is 40nc.
Q5 mosfet will remain open for 7ms (worst case) and the cycle time is 0.02s
Duty cycle = 0.35
So the minimum bootstrap charge needed is:
QC = Qg+ (D.C * Tcycle * current from bin VB)
QC = 40 + (0.35 * 0.02 * 0.34) = 2500nc
As we said before the voltage drop on the bootstrap capacitor must be under the minimum voltage of bin VB so in our design we choose it to be 5% from VCC voltage:

69. 8.3:Gate resister selection :

70. from the datasheet of 2110 gate driver the value of the on resistance is 1 ohm and off resistance is 0.5 ohm
From this equation RG=5 ohm
From this equation RG=5.5ohm

71. So the RG must be more tham 5.5 ohm
In our design we select RG=10 ohm

72. 8.4:Gate source resistance

73. 8.5:schimatic circuit for one leg

74. 8.6:Full inverter PCB layout

75. The output voltage for full inverter :

76. Chapter 10 :project cost

77. Thank you