IBM Mainframes Assembler

IBM Mainframes Assembler

Presentation Thanks for using this presentation. You are free to use it. I appreciate if you refer to the author when using it. I’m sorry about the language errors; my english isn’t so good; I’ll appreciate if you send me any corrections and suggestions to optimize the comprehension to the reader. The same is valid for any technical error; please help me to make this an error-free text. Alberto Romano Schiesari – São Paulo - Brazil

Summary Architecture IBM Mainframes architecture Data format
Instruction format Assembler language Assembly flow Assembler program structure Statement Assembler elements Statement types Assembler commands Machine Instructions Hints and tips Instructions by group Instructions Macro Instructions Appendix - Links Appendix - Instructions summary (by op code) (by mnemonic) Appendix - Some EBCDIC characters Some ASCII characters Appendix - Questions Answers

Summary Assembler commands (alphabetically) AMODE CCW CCW0 CCW1 CNOP
COPY CSECT CXD DC DROP DS DSECT DXD EJECT END ENTRY EQU EXTRN ICTL ISEQ LOCTR LTORG OPSYN ORG POP PRINT PUNCH PUSH REPRO RMODE SPACE START TITLE USING WXTRN These aren’t in the scope of this course: AREAD, MACRO, MEXIT, MEND ACTR, AGO, AIF, ANOP, GBLA, GBLB, GBLC, LCLA, LCLB, LCLC, MHELP, MNOTE, SETA, SETB, SETC

Summary Machine instructions (alphabetically) A AH AL ALR AP AR BAL
BALR BAS BASR BASSM BC BCR BCT BCTR BSM BXH BXLE C CDS CH CL CLC CLCL CLI CLM CLR CP CR CS CVB CVD D DP DR ED EDMK EX IC ICM IPM L LA LCR LH LM LNR LPR LR LTR M MC MH MP MR MVC MVCIN MVCL MVI MVN MVO MVZ N NC NI NR O OC OI OR PACK S SH SL SLA SLDA SLDL SLL SLR SP SPM SR SRA SRDA SRDL SRL SRP ST STC STCK STCM STH STM SVC TM TR TRT TS UNPK X XC XI XR ZAP

Architecture SYSTEM ARCHITECTURE

Architecture – some components
System CPU (CISC, RISC, hybrid) CISC = Complex Instruction Set Computer Variable length instructions In each instruction, explicitly or implicitly, one must specify: - The operation to be done - The operands used (places with data to process and places to store results): their address! - Operands’ length - Data format RISC = Reduced Instruction Set Computer Fixed length instructions; e.g. 4 bytes; the execution (average) is faster

Note that... Mainframes and PC’s = CISC

Storage byte addressing (access) Real storage? Virtual Storage? In virtual storage systems, hardware must talk with software to achieve the use of virtual storage

In symbolic languages, the reference to a field is made:  Using its name (variable or constant) or  Using its contents (literal) MOVE 1 TO NPAGE NPAGE = 1

In machine language, referencing a field is made using its address, one must specify a number (hexadecimal / binary) which is the field’s address. There is NO reference to names. This is called ADDRESSING. The hexadecimal number must have 6 or 8 digits. With 6 digits, if we have to store the address in a storage field, at least 3 bytes are needed. With 8 digits, if we have to store the address in a storage field, 4 bytes are needed. (in many of our examples we use smaller numbers, with 2 or 3 digits, just to simplify the visual and the computing)

Storage bytes addressing (access) Program Instructions Areas F830B004C82F 1C 00 MOVE instruction in machine language, indicating : (a) it is MOVE [F8]; (b) Sender [literal 1] length 0 (meaning = 1 byte) (c) Receiver [NPAGE] length 3 (meaning 4 bytes) (d) Sender [literal1] address C82F (e) Receiver [NPAGE] address B004 For now forget why and how, but believe me: x’B004’ is the NPAGE address and x’C82F’ is the literal address. Sender field [literal with contents 1] It has an address ! Receiver field [NPAGE variable]

Storage bytes addressing (access) Real storage X Virtual Storage Add 1 to the contents of field at address x’2B40’ If the contents of the field at address x’2B40’ is not in the real storage, then we (operating system + hardware) must: - Convert address from real to virtual storage - Fetch the contents from the virtual storage to the real storage - Execute the instruction (Remember also that it can happen with the instruction, and with any or all of the operands, too...)

Storage bytes addressing (access) Direct addressing? Indirect addressing? Direct addressing example  Add 1 to the field at address x’00002B40’ Indirect addressing example  Add 1 to the field at address x’2000’ + x’0B40’ Notes: (a) in fact, the field address is x’2B40’; it is expressed in a different way (x’2000’ + x’0B40’) (b) the number x’2000’ may be in a place, the number x’0B40’ in another place Indirect addressing example  Add 1 to the field at the address x’2000’ + x’0B00’ + x’0040’ Notes: (a) in fact, the field address is x’2B40’; it is expressed in a different way (x’2000’ + x’0B00’ + x’0040’) (b) the number x’2000’ may be in a place, the number x’0B00’ in another place, and x’0040’ elsewhere...

 Storage bytes addressing capacity Storage length; how many “bits” does the mainframe’s CPU have?

 Storage bytes addressing capacity Address Bus = to refer to the addresses To address storage up to 64K, address bus must be 16-bit wide. To address storage up to 16MB, address bus must be 24-bit. etc Data Bus = to transfer data between components To transfer (simoutaneously) a half-word, data bus must be 16-bit wide. To transfer (simoutaneously) a full-word the data bus must be 32-bit. Eetc... CPU Storage Data Bus Address Bus Storage address refer Data transfer

 CPU Instruction Set – types and characteristics How many, what are the instructions of a CPU Instruction Set?

CPU instruction execution How is the instruction execution process?

 CPU instruction execution – generic process  FETCH (CPU fetchs the instruction from RAM storage to a CPU internal area; “problem”: variable length instructions  Decode = Analysis : what is the instruction length? (not needed in RISC Cpu), what is the operation to be done (wrong code? We could dubb this situation with the name 0C1...), what are the operands, etc Error? Pass control to the operating system, to solve it  OK? Operand(s) data FETCH  If they are in real store, good! (Else, lots of things to do...)  Operand contents Validation Error? How about dubb it as 0C7?...  Execution : in some cases (math operations mostly), results must be stored temporarily in CPU areas OK? If needed, STORE results back in RAM storage

Other architectural components

OTHER architectural components  Interruption system What are the interruptions? E.g. Time, program error (0Cx...)  I/O sub-systems How does the comm work between controller, storage, CPU and software? Which information does software receive after I/O operations?  Storage protection system How does the storage protection work? Is it possible to a program to invade another?  Virtual storage system Which is the process? What are the page-in & page-out algorithms?

IBM Mainframes Architecture

Tribute We own our jobs to him! Gene Myron Amdahl (1922-)

IBM Mainframes : architectural main components CPU ALU GR0 GR1 GR2 GR3 GR4 GR5 GR6 GR7 GR8 GR9 GR10 GR11 GR12 GR13 GR14 GR15 16 General Registers (fixed point registers) 4 bytes each FPR0 FPR2 FPR4 FPR6 4 Floating Point registers (8 bytes each) 1 Special 8 byte Register named PSW (Program Status Word) PSW etc... (cache...) Storage (RAM)

IBM Mainframes : architectural main components CPU PSW cc nia etc PSW : special 8 bytes length register. 2 important “fields" :  CONDITION CODE (*) : 2 BITS. They indicate, after some instructions execution, some condition inherent to the executiosn., e.g., comparison result. (*) Remember that this is NOT the operating system RETURN CODE (program-finish status indicator ; may be tested using JCL tool)  next instruction address (to be executed – 3 or 4 bytes, depending on the type of addressing mode/PSW)

BC mode PSW BYTE 0 BITS = channel masks BIT = channel 6 and above masks BIT = external mask BYTE 1 BITS = protection key BIT = 0 = Basic Control Mode BIT = machine-check mask BIT = 1 = wait state BIT = 1 = problem program state BYTES 2-3 (BITS 16-31) = Interruption code BYTE 4 BITS = ILC = Instruction length code BITS = CC = Condition code BITS = program mask BYTES 5-7 (BITS 40-63) = Instruction address

EC mode PSW BYTE 0 BIT = BIT = PER mask BIT = BIT = BIT = BIT = translation mode BIT = I/O mask BIT = external mask BYTE 1 BITS = protection key BIT = 1 = Extended Control Mode BIT = machine check mask BIT = 1 = wait state BIT = 1 = problem program state BYTE 2 BIT = BIT = BITS = CC = condition code BITS = program mask BIT 20 = fixed-point overflow mask BIT 21 = decimal-overflow mask BIT 22 = exponent underflow mask BIT 23 = significance mask BYTE 3 (BITS 24-31) = BYTE 4 (BITS 32-39) = BYTES 5-7 (BITS 40-63) = Instruction address

XA mode PSW BYTE 0 BIT = BIT = PER mask recording BIT = BIT = translation mode BIT = I/O mask BIT = external mask BYTE 1 BITS = protection key BIT = BIT = machine-check mask BIT = 1 = wait state BIT = 1 = program problem state BYTE 2 BIT = address space mode (together with bit 5) BIT = BITS = CC = condition code BITS = program mask BIT 20 = fixed-point overflow mask BIT 21 = decimal-overflow mask BIT 22 = exponent underflow mask BIT 23 = significance mask BYTE 3 (BITS 24-31) = BYTE 4 BIT = 0 = 24 bit addressing = 1 = 31 bit addressing BYTE 4/5/6/7 (BITS 33-63) = Instruction address

ESA mode PSW BYTE 0 BIT = BIT = PER mask BIT = BIT = translation mode BIT = I/O mask BIT = external mask BYTE 1 BITS = protection key BIT = BIT = machine-check mask BIT = 1 = wait state BIT = 1 = program problem state BYTE 2 BIT = address space control = 00 = Primary space mode (bit 5 = 1) = 01 = Access-register mode (bit 5 = 1) = 10 = Secondary space mode (bit 5 = 1) = 11 = Home space mode (bit 5 = 1) BITS = CC = condition code BITS = program mask BIT 20 = fixed-point overflow mask BIT 21 = decimal-overflow mask BIT 22 = exponent underflow mask BIT 23 = significance mask BYTE 3 (BITS 24-31) = BYTE 4 BIT = 0 = 24 bit addressing = 1 = 31 bit addressing BYTE 4/5/6/7 (BITS 33-63) = Instruction address

IBM Mainframes : special areas HALFWORD = area with 2 bytes and address multiple of 2 WORD ou FULLWORD = area with 4 bytes and address multiple of 4 DOUBLEWORD = area with 8 bytes and address multiple of 8 QUADWORD = area with 16 bytes and address multiple of 16 •QW •DW •FW •HW etc.

IBM Mainframes : program error interruptions (0Cx) Code Reason 0008 FIXED POINT OVERFLOW = The instruction uses a general register as result operand, but it isn’t large enough to fit the result 0009 FIXED POINT DIVIDE = Binary fixed-point division with zero divisor. 000A DECIMAL OVERFLOW = In an operation with packed fields, the receiver field isn’t large enough to fit the result 000B DECIMAL DIVISION = Packed decimal division with zero divisor. 000C EXPONENT OVERFLOW = Binary floating-point operations. 000D EXPONENT UNDERFLOW = Binary floating-point operations. 000E SIGNIFICANCE = Binary floating-point operations. 000F FLOATING`POINT DIVISION = Binary floating-point division with zero divisor. Code Reason 0001 OPERATION = the operation code is invalid (it doesn’t refer to any executable instruction) 0002 PRIVILEGED OPERATION = the program tried to execute a privileged instruction. 0003 EXECUTE = Execute of another Execute instruction 0004 PROTECTION = A program instruction tried to store data outside its authorized range 0005 ADDRESSING = A program instruction referenced a non-existent address 0006 SPECIFICATION = The instruction specified something with error; e.g., an odd floating-point register 0007 DATA = The fields an instruction refers to aren’t in the correct format; e.g., adding 2 packed fields, and one of them (or both) does not meet the packed format rules.

IBM Mainframes IBM : addressing It is needed to address : registers and storage bytes (Remember that a storage field address is the address of its leftmost byte)  DIRECT addressing : only for registers: General Registers = 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F Floating Point Registers = 0,2,4,6  There is NO DIRECT addressing to storage The INDIRECT addressing may be:  Base + Displacement  Index + Base + Displacement

IBM Mainframes IBM : addressing Note that, in reality, ALL addresses specified are “real storage” addresses, as if they were in a mirror refleting the address space. But remember that the things in real life aren’t so nice Try this way: was once a kingdom where for each address space there was a real storage exactly equal...

Base + Displacement Instructions to Main Avenue Postman : Go to the “Caliente” Restaurant Walk 850 meters, you arrived at the house where the envelope must be delivered! This is the BASE, an initial reference to start identifying the deliver address Walk 850 meters = Displacement

Base + Displacement Hex number in a General Register (by this time dubbed base register) Hex number (from x’000’ up to x’FFF’) in the instruction, dubbed displacement Hex number : this is the Address + = Note: the interrupted line box means that the number (address) IS NOT in a general register, but in an internal CPU area !!!

Base + Displacement : specification (2 bytes) x y Base register Displacement 3 5 A C x Base Register = 3 Displacement = 5AC Address = Register 3 contents + x’5AC’ D 8 x Base register = 13 (D) Displacement = 08D Address = Register D contents + x’08D’

Base + Displacement x y Base register Displacement Then: Maximum displacement = x’FFF’ = 4095

Base + Displacement : examples Base Register Base register Contents Displacement “Direct” address (it would be necessary 4 bytes to specify it) “Indirect” Address (Base + displacement : 2 bytes are enough to specify it) 4 B40 00002B40 4B40 00B2F02C 1A2 00B2F1CE 41A2 15 DB4 00000DB4 FDB4 0046B28C 114 0114 The contents of register zero is NOT CONSIDERED computing an address !!!

Base + Displacement : Hints and tips You must use it to address “normal” addresses. What are “normal” addresses? Give me a break! (Those we can express using an ... Expression)

Base + Displacement : Hints and tips What is an expression? Again!? (see in the “Assembler elements” chapter)

Index + Base + Shift Instructions to Main Avenue Postman : Go to the “Caliente” Restaurant. Walk 850 meters, you’ll arrive at the condo. In the condo, walk 50 meters then you’ll arrive at the house where the envelope must be delivered! This is the BASE, an initial reference to start identifying the deliver address Walk 850 = Displacement Walk 50 = Index

Index + Base + Shift Binary number in a General Register (by this time dubbed base register) Hex number : this is the Address + = Hex number (from x’000’ up to x’FFF’) in the instruction, dubbed displacement Binary number in a General Register (by this time dubbed index register) Note: the interrupted line box means that the number (address) IS NOT in a general register, but in an internal CPU area !!!

Index + Base + Displacement : specification (21/2 bytes) Base register Displacement Index register x y z Index register = 7 Base Register = 3 Displacement = 5AC Address = register 7 contents + register 3 contents + x’5AC’ 3 5 A C 7 F B x Index Register = 11 (B) Base Register = 5 Displacement = FAC Address = register B contents + register 5 contents + x’FAC’

Index + Base + Displacement : specification (21/2 bytes) x y Base register Displacement z Index register Then: Maximum displacement = x’FFF’ = 4095

Index + Base + Displacement : examples Index Register Index register Contents Base Register Base Register Contents Displacement “Direct” address (it would be necessary 4 bytes to specify it) “Indirect” Address (Base + displacement : 2 ½ bytes are enough to specify it) 12 4 B40 00102B40 C4B40 00F4CAFE 10 000C8B00 1F0 000C8CF0 0A1F0 1A2 0000E1A2 441A2 15 00C42B06 002 00C42B08 FC002 The contents of register zero is NOT CONSIDERED computing an address !!!

Index + Base + Displacement : hints and tips In general, one uses to address “abnormal” addresses. What is an abnormal address? (I’m kidding...) A good example: the elements of a table.

Index + Base + Displacement : hints and tips Example: addressing elements of a table BR US UK IT FR ES AR CA BE AU GE DE PT GR IR Initial table address : Symbol = TBSTATS (converted by assembler to base + displacement) Target element address (8th element) = Initial table address + [element length * (number of elements – 1) ] = TBSTATS + [ 2 * (8 – 1) ] = TABSTATS + 2 * 7 = TBSTATS + 14 Base+Displacement of TBSTATS + Index Register (e.g. 17C0A = Index reg=1, Base reg = 7, displacement = C0A) TBSTATS address : in the instruction, with format Base + Displacement = X’7C0A’ (assembler finds out base register and displacement; let’s suppose Base reg = 7, displacement = X’C0A’) Contents of Index register : e.g. Reg 1 (it’s our program’s responsibility to prepare) with contents = X’ E’ TBSTATS address in Index+base+displacement format = X’17C0A’

IBM Mainframes IBM : addressing X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’000000A0’ X’000000B0’ X’000000C0’ X’000000D0’ X’000000E0’ X’000000F0’ Suppose this 256 bytes storage

IBM Mainframes IBM : addressing * X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’000000A0’ X’000000B0’ X’000000C0’ X’000000D0’ X’000000E0’ X’000000F0’ The number in the base register indicates byte *. If the desired target address is x’ ’: Q: Using register 12 as base register and with its contents being x’ ’, how many bytes one has to “walk” (shift) to, leaving the byte pointed by base register, arrive at the target byte? A: x’048’ = displacement (blue dotted line)

IBM Mainframes IBM : addressing X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’ ’ X’000000A0’ X’000000B0’ X’000000C0’ X’000000D0’ X’000000E0’ X’000000F0’ The number in the base register indicates byte *. If the desired target address is x’000000E8’: Q: Using register 12 as base register and with its contents being x’000000A0’, how many bytes one has to “walk” (shift) to, leaving the byte pointed by base register, arrive at the target byte? A: x’048’ = displacement (blue dotted line) *

IBM Mainframes IBM : addressing See this case: Target byte = x’ ’ ; Base register = C (contents = x’ ’) + (Displacement) x’048’ Remember that Maximum displacement allowed = x’FFF’ In other words: general register C, while used as base register (in this example), with x’ ’ as contents, can only be used as base register to refer to addresses from x’ ’ to x’00000FFF’.

IBM Mainframes IBM : addressing Maximum displacement allowed = x’FFF’ If an instruction needs to address 2 fields: The first with address x’ ’, and the second with address x’00001CB0’, at the time of its execution, IT’S NEEDED MORE THAN 1 BASE REGISTER correctly prepared. We can set, for example, register C (12) with x’ ’ and register D (13) with x’ ’ .

IBM Mainframes IBM : addressing Maximum displacement allowed = x’FFF’ The first field is addressed by base register 12: C048  Base register C (contents = x’ ’) + Displacement x’048’ The second field is addressed by base register 13: DCB0  Base register D (contents x’ ’) + Displacement x’CB0’ THERE’S NO WAY in a single instruction (and, by extension, in a program range) to use only 1 base register addressing fields with addresses far from each other longer than x’FFF’.

IBM Mainframes IBM : addressing Summary: At the same time, one can use a maximum of 15 base registers (remember that the contents of register zero is not considered when computing an address). This means that the biggest program size addressable simultaneously is (4K * 15) = 60K

IBM Mainframes IBM : addressing Summary: Using (almost) all registers as base registers: YOU WILL HAVE PRACTICALLY NO WORK REGISTER (only R0) ! Be careful!

Mainframes IBM : endereçamento WOW ! What if the program is bigger (than 20K)?

IBM Mainframes IBM : addressing One (there are lots of them) alternative: Think about what general registers you’ll use as base registers in your program. For example: R3, R4, R5, R6 and R7 They are 5 registers. This is enough to address (5 x 4K) = up to 20K In a 20K “piece” of the program, you (must) set the registers up with the right contents, and use only things (areas and instructions) belonging to this piece. In another 20K piece, set the registers up with the other contents and use only things of the new piece. And so on...

IBM Mainframes IBM : addressing Program 60K storage 0K 4K 8K 12K 16K 20K 24K 28K 32K 36K 40K 44K 48K 52K 56K R3 = x’ ’ R4 = x’ ’ R5 = x’ ’ R6 = x’ ’ R7 = x’ ’ R3 = x’ ’ R4 = x’ ’ R5 = x’ ’ R6 = x’ ’ R7 = x’ ’ R3 = x’0000A000’ R4 = x’0000B000’ R5 = x’0000C000’ R6 = x’0000D000’ R7 = x’0000E000’

Register usage: idea, hints

Register usage: idea, hints Reg Use Avoid using; used by the access methods and operating system routines 1 Avoid using; used by the access methods and operating system routines; used by TRT and EDMK instructions. 2 Avoid using; use for work; used by TRT instruction 3 Use as base register 4 5 6 7

Register usage: idea, hints Reg Use 8 Use as work register 9 10 11 12 13 Avoid using; used as save area by the interface routines between softwares 14 Avoid using; used to save the return address when calling a routine by the caller 15 Avoid using; used as initial base register for called routines, mainly in the access methods

Data format Data format

Data format Data format
Alphanumeric data EBCDIC standard  Numeric data Fixed point binary (arithmetic operations : registers or storage) Floating point binary (arithmetic operations : registers or storage) Packed decimal (arithmetic operations : storage) Zoned decimal (arithmetic operations : NOT ALLOWED)

Data format - Alphanumeric data
Alphanumeric Data EBCDIC standard

1 byte each character example: to represent the word “ALBERTO” Curiosity: in ASCII A L B E R T O C1 D3 C2 C5 D9 E4 D6 A L B E R T O 41 4C 42 45 52 54 4F

1 byte each character example: to represent the word “Alberto” Curiosity: in ASCII A l b e r t o C1 93 82 85 99 A4 96 A 1 b e r t o 41 6C 62 65 72 74 6F

Data format - Numeric data
Numeric data Formats: Zoned decimal or - Packed decimal or - Fixed point binary or - Floating point binary

ZONED DECIMAL byte each algarism, up to 16 bytes = up to 16 algarisms Each byte : left half = x’F’ right half = algarism Rightmost byte : left half = sign positive number or zero : x’F’ or x’C’ negative number : x’D’ IMPORTANT !!! 1  With this format, it’s NOT allowed to do arithmetic operations, it’s just to receive data (e.g. terminal data entry) or to format output data (e.g. terminal, printer). 2  Numbers: only INTEGERS.

ZONED DECIMAL F1 F2 F3 Number 123 : 3 bytes needed F1 F2 D3 Number –123 : 3 bytes needed Atention !!! : if printed (or seen), in character mode this configurations corresponds to the letter “L”

ZONED DECIMAL Number 123 in a 5 bytes length field F0 F1 F2 F3 Number -123 in a 5 bytes length field F0 F1 F2 D3 Atention !!! : if printed (or seen), in character mode this configurations corresponds to the letter “L”

PACKED DECIMAL ½ byte each algarism, ½ byte for the sign Up to 8 bytes = up to 15 algarisms Rightmost byte : right half : sign positive number or zero : x’F’ or x’C’ negative number : x’D’ IMPORTANT !!! 1  In this format arithmetic operations are only allowed with storage fields (there is NO instructions to manipulate packed decimal data in registers) 2  Numbers: only INTEGERS.

PACKED DECIMAL 02 3F Number 23 : 2 bytes needed 02 3C 02 3D Number - 23 : 2 bytes needed Atention !!! : if printed (or seen), in character mode these configurations corresponds to “other” characters

PACKED DECIMAL 12 3F Number 123 : 2 bytes needed 12 3C 12 3D Number -123 : 2 bytes needed Atention !!! : if printed (or seen), in character mode these configurations corresponds to “other” characters

PACKED DECIMAL Number 123 in a 5 bytes length field 00 12 3C Number -123 in a 5 bytes length field 00 12 3D Atention !!! : if printed (or seen), in character mode these configurations corresponds to “other” characters

FIXED POINT BINARY Only fixed length fields: bytes (1 bit for sign + 15 bits for the number) or 4 bytes (1 bit for sign + 31 bits for the number) or 8 bytes (1 bit for sign + 63 bits for the number) The quantity of algarisms (in the equivalent decimal numbers) depends on the number being represented (see next slide table) Leftmost bit = sign positive number or zero : ; negative number : 1 BUT If positive, it’s the number’s representation If negative, the contents is the complement to the next 2 power IMPORTANT !!! 1  In this format arithmetic operations are only allowed with data in registers or in registers and storage fields (there is NO instructions to manipulate fixed point binary numbers only in storage; one of the operands must be in register) 2  Numbers: only INTEGERS.

FIXED POINT BINARY Bytes Magnitude Sample use Numbers that may be represented 2 Thousands (32K) Person’s age, line counter From –32,768 to 32,767 4 (US Bilions) (2G) Employee salary, Part code, Customer code From –2,147,483,648 to 2,147,483,647 8 (US Quintillions) (9Exa) Company revenues, World population, astronomical distances From –9,223,372,036,854,775,808 to 9,223,372,036,854,775,807

FIXED POINT BINARY Why complement? in binary = –123 in binary = Subtracting 1 step by step... See (0 – 1) subtraction 4 - 1 ----- 3 -1 ---- 2 - 1 1 -2 -3 Etc... -122 -123

FIXED POINT BINARY How to convert a decimal negative number to binary?  Convert the correspondent positive number to binary (consider only the significant digits)  Invert them: 1 becomes 0 and 0 becomes 1  Add 1  Fill to the left with 1’s to complete a half-word, a full-word or a double-word Example: let’s suppose decimal –123; is  Convert the correspondent positive number to binary  Invert them: 1 becomes 0 and 0 becomes  Add  Fill to the left with 1’s to complete a half-word, a full-word or a double-word F F F F F F F F F F F F F F F F

FIXED POINT BINARY How to convert a binary negative number to decimal?  Subtract it from X’....FFFFFF’ (the 1st X’...F’ number greater than the number to be converted)  Add 1; result is the POSITIVE desired number. Convert it to negative Example: let’s suppose X’FFE8’  Subtract FFFF FF A  Add A B  X’7B’ is the hexadecimal equivalent to decimal  Desired number is decimal -123

FIXED POINT BINARY Number 123 In a half-word X’007B’ In a full-word X’ B’ In a double-word X’ B’

FIXED POINT BINARY Number - 123 In a half-word X’FF85’ In a full-word X’FFFFFF85’ In a double-word X’FFFFFFFFFFFFFF85 ’

FLOATING POINT BINARY Sorry... It isn’t in the scope of this course

Instruction format INSTRUCTION FORMAT

Instruction formats Instructions : main formats
RR = 2 bytes  RX = 4 bytes  RS = 4 bytes  SI = 4 bytes  SS = 6 bytes 2 bytes : operation codes between x’00’ and x’3F’ (b’ ’ a b‘ ’) 4 bytes : operation codes between x’40’ and x’BF’ (b’ ’ a b‘ ’’) 6 bytes : operation codes between x’C0’ and x’FF’ (b’ ’ a b‘ ’)

Instruction formats Instructions : main formats
RR – generally 2 operands, both in general registers  RX – 2 operands: general register storage field : address specification : Index + [ Base + Displacement ]  RS – 3 operands, 2 registers and 1 storage field registers (they may indicate a range) storage field : address specification: [ Base + Displacement ]  SI – 2 operands, both in storage immediate storage (only 1 byte, within the instruction; no need to address it) storage field : address specification : [ Base + Displacement ]  SS – 2 operands, both storage fields Both addresses specified as [ Base + Displacement ]

Instruction formats 5 E F Instructions : main formats CO R1 R2
RR – (normally) 2 operands, both registers x CO 1st. Operand registerx 2nd. Operand register Operation code R R2 5 E F x Operation code = X’05’ 1st operand register = X’E’ (register 14) 2nd operand register = X’F’ (register 15)

2nd. Operand Index Register
Instruction formats Instructions : main formats RX – 2 operands: of them: register The other one : storage (address specified via Index register + [ Base register + Displacement ] x CO 1st. Operand registerx 2nd. Operand Index Register Operation code R X2 B D2 2o. Operand Base + Displacement D D2 4 5 E x 3 C 2 8 Operation code = X’45’ ; 1st operand register = X’E’ (register 14) ; 2nd operand index register = X’0’ (register 0); 2nd operand base register = X’3’ (register 3); 2nd operand displacement = X’C28’

2o. Operand Base + Displacement
Instruction formats Instructions : main formats RS – 3 operands, 2 of them are registers, the other one in storage (address specified via [ Base register + Displacement ] ) x CO 1st. Operand Register 3rd. Operand Register Operation code R R3 B D2 2o. Operand Base + Displacement D D2 9 8 E C x D Operation code = X’98’ ; 1st operand register = X’E’ (register 14) ; 3rd operand register = X’C’ (register 12); 2nd operand base register = X’D’ (register 13); 2nd operand displacement = X’000’

1st. Operand Base + Displacement
Instruction formats Instructions : main formats  SI – 2 operands, both in storage of them is immediate operand = 1 single byte (it is the instruction 2nd byte) The other one in storage: address specified via [ Base register + Displacement ] x CO Immediate Operand (2nd. Operand) Operation code I2 B D1 1st. Operand Base + Displacement D D1 9 2 5 C x 6 D Operation code = X’92’ ; 2nd operand (immediate operand) = X’5C’ ; 1st operand base register = X’5’ (register 5); 1st operand displacement = X’6D2’

1st and 2nd operands length
Instruction formats Instructions : main formats  SS-L – 2 operands, both in storage; 1 length specified (valid for both operands). Both addresses are specified as [ Base register + Displacement ] x CO Operation code L B D1 1st. Operand Base + Displacement D D1 B D2 D D2 2o. Operand 1st and 2nd operands length - 1 4 F x 3 B 9 6 2 A D Operation code = X’D2’ ; Both operands length = X’4F’ (80 bytes); 1st operand base register = X’3’ (register 3); 1st operand displacement = X’B94’; 2nd operand base register = X’6’ (register 6); 2nd operand displacement = X’F2A’

Instruction formats F 8 4 3 7 E D 6 2 Instructions : main formats CO
 SS-L1/L2 – 2 operands, both of them in storage; 2 lengths specified (1 for each operand). Both addresses are specified as [ Base register + Displacement ] x CO Operation code L1 L2 B D1 1st. Operand Base + Displacement D D1 B D2 D D2 2o. Operand 1st. Operand length - 1 2nd. Operand length - 1 F 8 4 3 7 E D 6 2 Operation code = X’F8’ ; 1st operand length = X’4’ (5 bytes) ; 2nd operand length = X’0’ (1 byte); 1st operand base register = X’3’ (register 3); 1st operand displacement = X’77E’; 2nd operand base register = X’4’ (register 4); 2nd operand displacement = X’D62’

See the result here ONLY after trying hard to solve it
Instruction formats Exercise Solve Exercise 301 See the result here ONLY after trying hard to solve it

Assembler Language ASSEMBLER LANGUAGE

Assembly / linkedit / execution flow
LOADER Storage SYSLIB Macros/Copys SYSIN Source prog SYSUT1 Work IEV90 SYSPUNCH Object prog SYSGO SYSPRINT List SYSLIN Control stmts Other inputs IEWL SYSLMOD Executable LINKLIB

Assembler program structure

It can be this way... Program I (Instructions) A (Areas) LOAD POINT = ENTRY POINT

Or this way... Program A (Areas) I (Instructions) LOAD POINT ENTRY POINT

This way too... Program I LOAD POINT = ENTRY POINT A

Even like this ... Program LOAD POINT = ENTRY POINT I A

Or like this... Program LOAD POINT A I ENTRY POINT

Remember that a reentrant program may be like this... P1 Program An .... A3 A2 A1 P1 instructions ( manipulating A1, and, concurrently or in parallel, manipulating A2, manipulating A3, etc... manipulating An) P1 is in fact: P1 areas (A1 or A2 or etc) +

In fact, an Assembler program’ structure may be ... Anyway ! If you do not branch (GO TO / Jump ) , CPU will try to “execute” areas as they were instructions... It is the von Newman architecture... See the blue stripe and the branch just before...

Statement Assembler STATEMENT

Statement Positon 1 : With an *, the whole statement is a comment
Position 1 to 8 : Symbol Position 9 to 14 : Instruction Mnemonic Code Position 16 to 71: Operands and comments; continuation must begin from position 16 Position : If filled with any character, indicates that this statement continues in the next one Positions 73 a 80: Identification & sequence * THIS WHOLE STATEMENT IS A COMMENT FILLING MVC PRAREA,=CL133‘ ' COMMENT = CLEARS PRAREA XI *+5,X’F0’ COMMENT = FORCE BRANCH BC 0,TOGGLE COMMENT = SOMETIMES NOP * SOMETIMES BRANCH HERE EQU * WMESSAGE DC C’AJK001A – FILE BEING OPENED HAS NO DD STATEMENT IN THE– JCL. WAKE UP AND INCLUDE IT!.’ HERE WE HAVE A COMMEN Symbol Instruction Operands & Comments Continuation

Start smelling Assembler way of life...
Statement Start smelling Assembler way of life... INIT TITLE ‘INITIALIZATION ROUTINE' SEGINIT DFHEIENT CODEREG=7,DATAREG=(10,11),EIBREG=9 B BEGIN SKIP CONSTANTS DC C‘HI! COPYRIGHT ARS 2001' DC CL17'***VERSION 1.0***' DC CL28'***LAST UPDATE 10/23/2001***' BEGIN EXEC CICS ADDRESS CWA(R13) L R12,DFHEICAP LOAD COMMAREA ADDRESS ST R13,TWSVCWA SAVE CWA ADDRESS LA R2,TWAREA LOAD R2 WITH TWAREA ADDRESS LA R3,JREND R3 = JREND ADDRESS SR R3,R COMPUTE LENGTH STH R3,TWLENGTH STORE LENGTH SPACE 2

... back to program structure ...
Statement “Smell” #2 (yellow = Instructions, blue = areas, white = commands to the assembler) ... COPY COVER CWA DSECT USING *,R13 COPY CWAREA COPY TADSECT COMMAREA DSECT USING *,R12 COPY TWAREA DFHEISTG DSECT DFHEISTG DFHEIEND EJECT T TITLE ‘SAMPLE PROGRAM‘ SPACE 2 ENTRYPT DFHEIENT CODEREG=(7,9),DATAREG=(10,11),EIBREG=5 B BEGIN SKIP CONSTANTS DC C‘HI! COPYRIGHT ARS 2001' DC CL17'***VERSION 1.0***' DC CL28'***LAST UPDATE 10/23/2001***' BEGIN L R12,DFHEICAP L R8,TWSVTERM L R13,TWSVCWA ... back to program structure ...

Statement “Smell” #3 (yellow = Instructions, blue = areas, white = commands to the assembler) ... * ================================================================== * * SEQUENCE OF INSTRUCTIONS TO BE EXECUTED * * ================================================================== * LA R2,TRLT TRLTLOOK CLI 0(R2),X'FF' TABLE END ? BE ERROR TRLT NOT IN TABLE CLC TWDBL(6),0(R2) IS TRANSACTION CODE IN THE TABLE? BE TRL YES SR R15,R CLEAR REGISTER IC R15,40(R2) LOAD R15 WITH INPUT LENGTH N R15,=F'127' ZERO LEFTMOST BIT OF REGISTER AR R2,R POINT TO NEXT ITEM IN THE TABLE B TRLTLOOK BACK TO THE SEARCH TRL0100 MVC TWTRLT,0(R2) MOVE TRLT TO TWA EXIT EXEC CICS RETURN RETURN ERROR LA R2, WRONG CODE OI TWSW,X'01' TURN ON CANCEL SWITCH LA R3, R3 = MESSAGE LENGTH LA R1,TWMSG R1 = MESSAGE WORKAREA ADDRESS STC R2,0(R1) STORE SG NUMBER TO WORKAREA B EXIT RETURN LTORG

Statement “Smell” #4 (yellow = Instructions, blue = areas, white = commands to the assembler) ... * ================================================================== * * MY MACROS USED TO DEFINE MY CONVERSION DATA * * ================================================================== * TRLT TRLT CODE=000301, X TIT=‘NORMAL CREDIT ', X MAPN='NOT', X PTCM=01, X SPEC=14, X MNEM=‘NCR' TRLT CODE=000302, X TIT=‘NORMAL DEBIT ', X MAPN=‘YES', X PTCM=02, X SPEC=14, X MNEM=‘NDB' END ENTRYPOI

Assembly program Assembler elements

Element 1 = Location Counter
Assembly program Element 1 = Location Counter

There’s 1 for each Section (Control and Dummy)
Assembly program Location Counter There’s 1 for each Section (Control and Dummy) It is a counter beggining at x’ ’ and it is Incremented each time storage is allocated (e.g. by declaring areas or by specifying instructions) Changed when explicitly demanded by the use of any Assembler command that affects it (e.g. ORG) BLOCO1 EQU * DS CL4096 ORG BLOCO1 DS CL1024 A DS CL16 B DS CL16 40 * DC S(A) DC S(B) C DC S(C,D,E,F) 00042C DC S(G,H,I,J) 45 * D20F MVC A,B 00043A D MVC C,D D22B C C MVC E,F D MVC G,H 00044C D MVC I,J

(some of the things listed are also present in the object program)
Assembly program Element 2 = Output List (some of the things listed are also present in the object program)

External Symbol Dictionary :
Assembly program External Symbol Dictionary : List of elements that must be treated by the Linkage Editor and Loader EXTERNAL SYMBOL DICTIONARY SYMBOL TYPE ID ADDR LENGTH LD ID FLAGS PROGDEMO SD AF FORA ER 0002 Z LD SUBROT ER 0003

Assembly program Program List
LOC OBJECT CODE ADDR1 ADDR2 STMT SOURCE STATEMENT 49 * VOU MUDAR PARA PRINT DATA PRINT DATA 00003B C1D3C2C5D9E3D DC CL7'ALBERTO' C1D3C2C5D9E3D65C DC CL8'ALBERTO*' 00004A C1D3C2C5D9E3C9D DC CL10'ALBERTINHO' C8D6 54 * VOU RESTAURAR O DEFAULT PRINT NODATA C1D3C2C5D9E3D DC CL7'ALBERTO' 00005B C1D3C2C5D9E3D65C DC CL8'ALBERTO*' C1D3C2C5D9E3C9D DC CL10'ALBERTINHO' 59 * 60 * PRINT ON/OFF

Relocation Dictionary : more work to the Linkage Editor and Loader
Assembly program Relocation Dictionary : more work to the Linkage Editor and Loader RELOCATION DICTIONARY POS.ID REL.ID FLAGS ADDRESS C B9 C C C C C C C A4 C A8 A46

Cross Reference / Symbol Table
Assembly program Cross Reference / Symbol Table It is being built each time a statement with its own symbol is encountered. Length attribute Symbols (labels) Addresses CROSS REFERENCE SYMBOL LEN VALUE DEFN REFERENCES AAALIN A ANO AE6 0319 ARIMP C A A A A A C A A A C BYTE ****UNDEFINED**** BYTEON FF 0085 CAMPO A CAMPO ****DUPLICATE**** COCIENTE DATA AE2 0316 .

If you use a symbol that will be converted to a
Assembly program Remember forever and ever: If you use a symbol that will be converted to a BASE + DISPLACEMENT address and the conversion isn’t possible (the assembler is not able to do it): ADDRESSABILITY ERROR = There is no base register to “serve” this address.

Assembly program Diagnostics THE FOLLOWING STATEMENTS WERE FLAGGED
DIAGNOSTIC CROSS REFERENCE AND ASSEMBLER S THE FOLLOWING STATEMENTS WERE FLAGGED 30 STATEMENTS FLAGGED IN THIS ASSEMBLY WAS HIGHEST SEVERITY CO OVERRIDING PARAMETERS- LINECOUNT(50),XREF(FULL) OPTIONS FOR THIS ASSEMBLY DECK, NOOBJECT, LIST, XREF(FULL), NORENT, NOTEST, NOBATCH, ALIGN, ESD, R FLAG(0), SYSPARM() NO OVERRIDING DD NAMES 312 CARDS FROM SYSIN CARDS FROM SYSLIB 572 LINES OUTPUT CARDS OUTPUT

Assembly program Element 3 = Expressions

Set of terms with a value and maybe will be used as an address.
Assembly program EXPRESSIONS Set of terms with a value and maybe will be used as an address. If it’s an address, it may be converted to base + displacement format.

(decimal, binary, character or hexadecimal) - Length attributes
Assembly program EXPRESSIONS May contain: - Symbols - Self-defining terms (decimal, binary, character or hexadecimal) - Length attributes Location Counter reference Arithmetic operators ( + - * / ) Paired parenthesis

Assembly program EXPRESSIONS Examples
Expression The resulting value corresponds to the LPOUP leftmost byte of LPOUP (Suppose LPOUP address = x’000A000C’; the value of expression LPOUP is x’000A000C’) This expression : only 1 term: a symbol [LPOUP] LPOUP+0 leftmost byte of LPOUP (Suppose LPOUP address = x’000A000C’; the value of expression LPOUP+0 is x’000A000C’) This expression : 2 terms: 1 symbol [LPOUP] and 1 decimal self-defining term [0]

Assembly program EXPRESSIONS
Expression The resulting value corresponds to the LPOUP+3 4th byte of LPOUP (Suppose LPOUP address = x’000A000C’; the value of expression LPOUP+3 is x’000A000F’) This expression : 2 terms: 1 symbol [LPOUP] and 1 decimal self-defining term [3] LPOUP th. byte of LPOUP (Suppose LPOUP address = x’000A000C’; the value of expression LPOUP+15 is x’000A001B’) 1 decimal self-defining term [15]

Expression The resulting value corresponds to the LPOUP+B’1111’ 16th. byte of LPOUP (Suppose LPOUP address = x’000A000C’; the value of expression LPOUP+B’1111’’ is x’000A001B’) This expression : 2 terms: 1 symbol [LPOUP] and 1 binary self-defining term [B’1111’] LPOUP+C’F’ th. byte of LPOUP (Suppose LPOUP address = x’000A000C’; the value of expression LPOUP+C’F’’ is x’000A00D2’) 1 character self-defining term [C’F’] Note that C’F’ = X’C6’ X’000A000C’ + X’C6’ = X’000A00D2’

Expression The resulting value corresponds to the WAREA+50+X’100’+B’1100’+C’ ’ 383th. byte de WAREA (Suppose WAREA address= x’000A000C’; the value of expression WAREA+50+X’100’+B’1100’+C’ ‘ is x’000A018A’) This expression : 5 terms: 1 symbol [WAREA] 1 decimal self-defining term [50] 1 hexadecimal self-defining term [X’100’] 1 binary self-defining term [B’1100’] 1 character self-defining term [C’ ‘] Note that : Decimal 50 = X’32’; B’1100’ = X’C’ ; C’ ‘ (space) = X’40’ X’32’ + X’100’ + X’C’ + X’40‘ = X’17E’ = decimal 382 X’000A000C’ + X’32’ + X’100’ + X’C’ + X’40’ = X’000A018A’

Expression The resulting value corresponds to the WAREA+L’WAREA 1st byte after (whole) WAREA This expression : 2 terms: 1 symbol (WAREA) and 1 length attribute [L’WAREA] WAREA+1 1st byte after the beginning of WAREA (2nd byte of WAREA) 1 decimal self-defining term [1] WAREA+L’WAREA-1 last byte of (whole) WAREA This expression : 3 terms: 1 symbol (WAREA) and

Expression The resulting value corresponds to the WAREA+L’FIXDLEN+1000 This expression : 3 terms: 1 symbol (WAREA) + 1 length attribute [L’FIXDLEN] + 1 decimal self-defining term [1000] Suppose WAREA is composed by  an area named FIXDLEN +  an area with 1000 bytes The value of this expression WAREA+L’FIXDLEN+1000 corresponds to the first byte after whole WAREA (WAREA + FIXDLEN length )

Expression The resulting value corresponds to the L’WATERM1+L’WATERM2+L’WATERM3 This expression : 3 terms: 3 length attributes [L’WATERM1, L’WATERM2, L’WATERM3] length of WATERM1 area + length of WATERM2 area + length of WATERM3 area Suppose length of WATERM1 is 1000 bytes, length of WATERM2 is 2000 bytes, length of WATERM3 is 3000 bytes (Total length is 6000 bytes [decimal]) The value of the expression L’WATERM1+ L’WATERM2+ L’WATERM3 is X’1770’

Expression The resulting value corresponds to the *+1 address in the location counter + 1 This expression : 2 terms: 1 Location Counter reference (*) + 1 decimal self-defining term [1] *+L’WAREA address in the location counter + x bytes (x = WAREA length) 1 length attribute [L’WAREA] L’COMM+L’REGTYP1 COMM length + REGTYP1 length This expression : 2 terms: 2 length attributes [L’COMM, L’REGTYP1]

Element 4 = Explicit and Implicit Operand reference
Assembly program Element 4 = Explicit and Implicit Operand reference

Explicit and implicit operand reference
Assembly program Explicit and implicit operand reference Registers: allways referenced explicitly AR 1,6 LR R5,R14 LR 5,14 LR R5, Syntax OK if there is R5 EQU 5 , but... * Don’t do that! Why reg 5 with symbol * and reg 15 don’t? LR 5,R Syntax OK if there is R14 EQU 14 , but... * Don’t do that! Why reg 14 with symbol * and reg 5 don’t?

Assembly program Explicit and implicit operand reference Storage: explicitly or implicitly referenced RX instructions : Explicit reference: op reg1st,disp2nd(index2nd,base2nd) L ,12(13) L R14,12(R13) IF EQUATES PROVIDED ST 7,96(8) ST 7,96(R8) IF R8 EQU PROVIDED Implicit reference: op reg1st,expression (assumed index register = 0) or op reg1st,expression(index2nd) L ,SAVE14 L ,SAVEAREA+12 ST 7,WSAVEA(7) ST 7,WSAVAREA+(7*4)

Assembly program Explicit and implicit operand reference Storage: explicitly or implicitly referenced RS Instructions : Explicit reference : op reg1st,reg3rd,disp2nd(base2nd) LM 14,12,12(13) STM 7,11,0(R12) Implicit reference : op reg1st,expression LM 14,12,SAVEAREA+12 STM 14,12,THERE

Assembly program Explicit and implicit operand reference Storage: explicitly or implicitly referenced SI Instructions : Explicit reference : op disp1st(base1st),immed2nd MVI 10(R12),C’*’ XI 0(15),X’FF’ OI 15(R8),X’80’ Implicit reference : op expression1st,immed2nd MVI FLAGS+77,C’*’ XI TOGGLE,X’FF’ OI PRINTED,X’80’

Assembly program Explicit and implicit operand reference Storage: explicitly or implicitly referenced SS/L Instructions : Implicit reference : op expression1st,expression2nd (assumed length = length of 1st operand) MVC ARIMP+77,C’*’ T-A-K-E C-A-R-E!!! * I THINK THIS IS NOT YOU WANNA DO !!! MVC ARIMP+77,=C’*’ * I THIS THIS IS NOT ALSO ... !!! MVC ARIMP+77(1),=C’*’ * WOW ! PROBABLY IT’S THE RIGHT OPTION !!! CLC AGENTCOD,CODWANT (length implicit = length of AGENTCOD) CLC IVSAM(3),CODWANT (length = 3 = explicitly indicated) CLC IVSAM+68(3),CODWANT (length = 3 = explicitly indicated) CLC IVSAM+68,CODWANT (length implicit = length of IVSAM)

Assembly program Explicit and implicit operand reference Storage: explicitly or implicitly referenced SS/L Instructions : Explicit reference : op disp1st(lengthboth,base1st), disp2nd(base2nd) MVC 0(18,7),=C’ERROR’ (length = 18 = explicitly indicated) CLC AGENTCOD,25(14) (length assumed = length of AGENTCOD) CLC AGENTCOD+33,25(14) (length assumed = length of AGENTCOD) CLC AGENTCOD+33(2),25(14) (length = 2= explicitly indicated) CLC 3(22,8),7(15) (length = 22 = explicitly indicated)

Assembly program Explicit and implicit operand reference Storage: explicitly or implicitly referenced SS/L1-L2 Instructions : Implicit reference : op expression1st,expression2nd (1st operand assumed length = length of 1st operand; 2nd operand assumed length = length of 2nd operand) AP COUNTLIN,=P’1’ ZAP TOTVAL,=P’0’ AP BIGTOT,SUBTOT MP WNUM,=P’12’ MP WNUM+44(3),=P’12’

Assembly program Explicit and implicit operand reference Storage: explicitly or implicitly referenced SS/L1-L2 Instructions : Explicit reference : op disp1st(length1st,base1st), disp2nd(length2nd,base2nd) AP 0(4,3),=P’1’ ZAP 17(16,12),=P’0’ AP BIGTOT,127(2,5) MP WNUM+44(8),222(3,R6)

Assembly program Statement types - Assembler commands - Machine instructions - Macro-instructions

Assembly program Assembler commands
- Area definition: DC, DS, CCW, CCW0, CCW1 - Program sectioning and linking : START, CSECT, DSECT, DXD, CXD, COM, ENTRY, EXTRN, WXTRN - Base register control: USING, DROP Listing control: TITLE, EJECT, SPACE, PRINT - Misc control: ICTL, ISEQ, PUNCH, REPRO, ORG, EQU, OPSYN, PUSH, POP, LTORG, CNOP, COPY, END, LOCTR, AMODE, RMODE - Macro instruction definition: AREAD, MACRO, MEXIT, MEND - Conditional assembly (normally used to do macro instructions): ACTR, AGO, AIF, ANOP, GBLA, GBLB, GBLC, LCLA, LCLB, LCLC, MHELP, MNOTE, SETA, SETB, SETC

(Some) Machine instructions
Assembly program (Some) Machine instructions Storage to Storage move : MVC, MVZ, MVN, MVI, MVO, ZAP, MVCL, PACK, UNPK, MVCI - Register to Storage move : ST, STH, STM, STC, STCM, CVD - Storage to Register move : L, LH, LM, IC, ICM, CVB Register to Register move : LR, LPR, LNR, LCR, LTR - Arithmetic with Storage fields in the packed format : AP, SP, MP, DP, SRP - Arithmetic with Registers (fixed point binary) : AR, SR, MR, DR, ALR, SLR Arithmetic with Register and Storage (fixed point binary) : A, S, M, D, AH, SH, MH, AL, SL - Compare : CP, CLC, CLI, CLCL, C, CH, CL, CLM, CR, CLR - Branch : BC, BCR - Loop Control : BCT, BCTR, BXH, BXLE - Edition : ED, EDMK - Byte Translation and test: TR, TRT - Register Shift : SLL, SRL, SLDL, SRDL, SLA, SRA, SLDA, SRDA - Boolean Algebra : N, O, X, NR, OR, XR, NI, OI, XI, NC, OC, XC - Load and branch : BALR, BAL, BAS, BASR, BASSM, BSM - Misc : LA, TM, EX, SVC, MC, SPM, IPM, STCK, TS, CS, CDS

Assembly program Macro-instructions Installation’s e.g. ASCEBC, etc... IBM’s (from operating system, access methods) DCB (to declare datasets) OPEN, CLOSE, GET, PUT, READ, WRITE GETMAIN, FREEMAIN, ATTACH, DETACH etc... IBM’s (specific for CICS, DB2, etc...) DFHMSD, DFHMDF, etc...

Assembler commands Assembler commands

Instructions to the assembler - commands
Assembler commands (alfabetically) AMODE CCW CCW0 CCW1 CNOP COM COPY CSECT CXD DC DROP DS DSECT DXD EJECT END ENTRY EQU EXTRN ICTL ISEQ LOCTR LTORG OPSYN ORG POP PRINT PUNCH PUSH REPRO RMODE SPACE START TITLE USING WXTRN These aren’t in the scope of this course): AREAD, MACRO, MEXIT, MEND ACTR, AGO, AIF, ANOP, GBLA, GBLB, GBLC, LCLA, LCLB, LCLC, MHELP, MNOTE, SETA, SETB, SETC

Instructions to the assembler - commands
Assembler commands (by group) Source statement and listing control: TITLE, EJECT, SPACE, PRINT, PUNCH, REPRO, ICTL, ISEQ - Program sectioning and linking : START, END, CSECT, DSECT, COM, - Base register control: USING, DROP, POP, PUSH - Direct Location Counter manipulation: ORG, EQU, CNOP, LOCTR - Use of external objects or external use of internal objects: ENTRY, EXTRN, WXTRN, DXD, CXD - Misc: AMODE, RMODE, COPY, OPSYN - Declare literals: LTORG - Area definition: DC, DS, CCW, CCW0, CCW1 - Macro instruction definition: AREAD, MACRO, MEXIT, MEND - Conditional assembly (normally used to do macro instructions): ACTR, AGO, AIF, ANOP, GBLA, GBLB, GBLC, LCLA, LCLB, LCLC, MHELP, MNOTE, SETA, SETB, SETC

Assembler commands - AMODE
AMODE (Adressing Mode) This command is used to indicate to the assembler the addressing mode associated to a Control Section. [symbol] AMODE n n may be 24 or 31 or ANY. Symbol is optional. If omitted, the addressing mode will be associated to the blank (no name) Control Section that must exist in the program. If specified, the addressing mode will be associated to the Contro,l Section with the same name as indicated in the symbol. The operand indicates the addressing mode that must be associated with the Control Section. One must specify 24 (24-bit addressing), 31 (31-bit addressing) or ANY (the Control Section isn’t sensitive to the addressing mode). There must be only one AMODE for each Control Section. The AMODE command may be specified at any point in the program. AMODE 24 is not compatible with RMODE ANY. Commands

Assembler commands - AMODE
AMODE (Adressing Mode) If only AMODE or RMODE is specified (or even none of them) the defaults are: Specified Assumed None AMODE 24 and RMODE 24 AMODE RMODE 24 AMODE RMODE 24 AMODE ANY RMODE 24 RMODE AMODE 24 RMODE ANY AMODE 31 Commands

Assembler commands – CCW / CCW0 / CCW1
CCW / CCW0 / CCW1 (Channel Command Word) Sorry. It’s not in the scope of this course. Commands

Assembler commands - CNOP
CNOP (Conditional Nop) CNOP command aligns the Location Counter to a Half-word boundary. The skipped bytes are filled with X'0700' (NOPR instruction). Syntax: CNOP a,b Where: a - 0, 2, 4 or 6. Indicates to what byte positition in a Full-Word or Double-Word the Location Counter must be advanced. b - 4 (full-word) or 8 (double-word). Example: CNOP ,4 • 0,8 • 2,8 • 4,8 • 6,8 • 0,4 • 2,4 • 0,4 • 2,4 Commands

Assembler commands - COM
COM (Blank Common Control Section) This command identifies and allocates a commom storage area. It can be referred to by independent modules linkedited and loaded as a unique program. No symbols nor operands are allowed. Only one COM is allowed in each program, although many COM commands may be issued, the first one indicating the COM beginning, and the others indicating the continuation(s). Sintax: COM Example: CSPRG START . A DS CL3 B DS CL4 END Commands

Assembler commands - COPY
COPY command copies source statements from a source library. Syntax: COPY symbol The symbol refers to the name of the library member to be copied. Among the copied commands, the commands ICTL or ISEQ are not allowerd. Example: COPY EQUREG Commands

Assembler commands - CSECT
CSECT (Control Section) CSECT command identifies the beginning or the continuation of a Control Section. [symbol] CSECT CSECT command have no operands. If symbol is specified, it names the CSECT. Commands and instructions specified after CSECT command will be part of it, up to another CSECT or DSECT command. Many CSECT commands with the same symbol may appear in a program. The first one names the CSECT (and is the range of its first “piece”). The others identify their continuations (the other “pieces”). To “interrupt” a DSECT, use another DSECT command or a CSECT command. Commands

CSECT (Control Section) PROG CSECT . END Is the same as PROG START (In both cases) there is a Location Counter (for PROG1 section). Commands

CSECT (Control Section) PROG1A START . PROG1B CSECT END There is a Location Counter for PROG1A section, another for PROG1B section, and a 3rd to PROG1C section. Is the same as PROG1A CSECT Commands

CSECT (Control Section) A CSECT CSECT A = CSECT B = 2 CSECT C = B CSECT . C CSECT A CSECT END There is a Location Counter for A section, another for B section, and a 3rd for C section. Commands

CSECT (Control Section) CSECTs of last slide is the same as this set of CSECTs: A START CSECT A = CSECT B = 2 CSECT C = B CSECT . C CSECT A CSECT END There is a Location Counter for A section, another for B section, and a 3rd for C section. Commands

Assembler commands - CXD
CXD (Control Section) CXD command defines a Full-Word. Linkage Editor (ou o Loader) will put in this full-word the length of all external DSECTs specified in the source programs (being linkedited or loaded) using this DSECTs. Syntax: symbol CXD No operands are allowed. Example: TOTALLEN CXD Commands

Assembler commands - DC
DC (Define Constant) See detailed description Commands

Assembler commands - DROP
DROP (Por de lado, Deixar) DROP command indicates to the assembler that one (or more) register(s) previously assigned as base registers (via USING command) is (are) no longer base register(s) (teh assembler must drop them from the base register table). Syntax is: DROP [R1[,R2,R R16]] Where R R16 is the list of registers not to be used as base registers anymore. Example: DROP ,8 If no operand is specified, all base registers will be unassigned. Commands

Assembler commands - DS
DS (Define Storage) See detailed description Commands

Assembler commands - DSECT
DSECT (Dummy Section) DSECT command defines a section used to do address convertions to Base+Shift format; it doesn’t allocate areas, it’s just used by the assembler to build the symbol table and determine the displacements of the fields it contains. It’s often used to describe an area ‘ structure., without phisically allocating storage for it. Syntax is: symbol DSECT DSECT command have no operands. The symbol names the DSECT. Many DSECT commands with the same symbol may appear in a program. The first one names the DSECT (and is the range of its first “piece”). The others identify their continuations (the other “pieces”). To “interrupt” a DSECT, use another DSECT command or a CSECT command. Example: Commands

Assembler commands - DSECT
DSECT (Dummy Section) CSN START . DSN DSECT A DS CL2 B DS CL20 C DS D DS CL10 CSN CSECT END To use the DSECT fields as instruction’s operands, it’s the programmer’s responsibility to set the base(s) register(s) up with the correct value(s), and, at codeing time, provide the assembler with the information about what is the base register(s) for the DSECT (USING command). Commands

Assembler commands - DXD
DXD (Define Dummy External) DXD command defines an external DSECT. Syntax: symbol DXD operand Symbol must be referenced as operand ina Q-type constant. It is the external DSECT’ first byte address, and its length attribute is 1. The operand has the same syntax as in the DS command. Assembler computes the amount of storage and the alignment required by the external DSECT, based on the area specified as operand. Example: CONST DXD F . DISPLAC DC Q(CONST) Commands

Assembler commands - EJECT
EJECT command causes a page skip in the sorce listing. No operands allowed. Commands

Assembler commands - END
END command must be the last source statement. Syntax: END [Symbol] If symbol is omitted, the first byte of the program is assumed as the ENTRY POINT. If symbol is specified, the ENTRY POINT is the address indicated by te expression specified as ioperand. END INICIO Commands

Assembler commands - ENTRY
This command identifies the symbols defined in the program, abd used externally (in another program). Syntax: ENTRY symbol[,symbol...] In the external program that uses the symbol, it must be defined with an EXTRN command. * ROUTINE IS DEFINED HERE IN PROG1 PROG START . ROUTINE EQU * ENTRY ROUTINE END * ROUTINE IS REFERENCED HERE IN PROG2 PROG START CONST DC A(ROUTINE) EXTRN ROUTINE Commands

Assembler commands - EQU
EQU (Equate - Igualar) EQU command associates an expression (value / address) to a symbol, adding them (symbol + value) to the symbol table. Syntax: Symbol EQU a Symbol EQU a,b Symbol EQU a,b,c Symbol EQU a,,c Where: a – expression whose value must be associated to the symbol. b – auto-defined term indicating the length attibute desired to be associated to the symbol.. If b is omitted, the length of the first (or only) term of the expression is assumed to be the length attribute of the symbol: --- If it is a Location Counter reference (*), an auto-defined term or a length attribute reference (L’x), 1 is assumed. --- If it is a symbol used in a DC or DS, it’s assumed the symbol’s length attribute. --- If it’s a symbol used in a machine instruction, the length of the instruction is assumed as length attribute (2,4 or 6 Bytes) --- If it’s a symbol used in a assembler command (except DC, DS and CCW), 1 is assumed. c – auto-defined term indicatiing the type attribute desired to be associated to the symbol. If omitted, U assumed. Commands

EQU (Equate - Igualar) Examples: R EQU 5 ... LA R5,TABLE Normally one uses to equate the registers numbers (addresses) to a symbol (e.g. R0 up to R15 to the general registers, and FP0 etc to the floating point registers), to “force” the references to them to be listed in the cross-reference produced by the assembler. INST EQU * LA R13,SAVEAREA Is often used rather than INST LA R13,SAVEAREA Note that the address will probably be the same: the location counter has the same value in both cases, unless in the first case there’s an area definition with odd nymber of bytes. The choice for the use of QUE is just for “elegance purposes”. Note that with the EQU the length attribute for INST symbol is 1, and using the symbol in the LA instruction the length attribute is 4 (LA instruction length). Commands

EQU (Equate - Igualar) Examples: OFF EQU X'00' ON EQU X'FF' PAID EQU X'80‘ This type of use is common also due to the listing of symbols in the cross-reference. If one uses the symbols rather than the values in instructions that need a mask, it’s easier to find (via cross-reference) which are the instructions manipulating the masks; if the auto-defined terms are used, no references are listed in the cross-reference. NI FLAGUSED,OFF RESET USE FLAG OI FLAGERR,ON SET ERROR FLAG TM FLAGPAY,PAID TEST PAYMENT Rather than NI FLAGUSED,X’00’ RESET USE FLAG OI FLAGERR,X’FF’ SET ERROR FLAG TM FLAGPAY,X’80’ TEST PAYMENT Commands

Assembler commands - EXTRN
EXTRN (External - Externo) This command identifies the symbols referred to in the program, but defined externally (in another program). EXTRN symbol[,symbol...] In the program that defines the symbol therre must be an ENTRY command for the symbol. * ROUTINE IS DEFINED HERE IN PROG1 PROG START . ROUTINE EQU * ENTRY ROUTINE END * ROUTINE IS REFERENCED HERE IN PROG2 PROG START CONST DC A(ROUTINE) EXTRN ROUTINE Commands

Assembler commands - ICTL
ICTL (Input Control) As seen in the assembler statements syntax: --- Symbol must begin at position 1 --- Last position is 71 --- Continuation (if exists) must begin at position 16 ICTL command, if used, must be the first statement in the source program (only 1 ICTL in the source program), and it’s used to change the structure above remembered. Syntax: ICTL a or ICTL a,b or ICTL a,b,c Where: a – specifies the 1st position of the symbols. May be from 1 up to 40. b – specifies the last position of an instruction (from 41 up to 80); if omitted, 71 is assumed. It must be greater than or equal to a+1. c –specifies the continuation position. It may be from 2 up to 40. If omitted or if 80 is specified assembler assumes that continuation is not allowed. ICTL ,70,71 Commands

Assembler commands - ISEQ
ISEQ (Input Sequence) Indicates to the assembler to validate the input sequence of the source statements.Syntax: ISEQ [a,b] Where: a – sequence field 1st position b - sequence field last position OBS:- a <= b Wow! It was used when the source statements were in cards, to assure that they weren’t messed! Commands

Assembler commands - LOCTR
LOCTR (Multiple Location Counters) This command is used to specify multiple location counters to a Control Section. Syntax: symbol LOCTR The first location counter of a section is automatically defined when assembler gets each first START, CSECT, DSECT and COM, and it works as if the assembler gets the section name and uses it as the counter’s name . Using the LOCTR command, one specifies another name, used to christen the 2nd location counter of the section, and so on. If one specifies a name already used, the location counter use is resumed. See the example following Commands

Assembler commands - LOCTR
LOCTR (Multiple Location Counters) PROGRAM Active Loc.Counter PGM CSECT PGM1 part 1 PGM1 part 1 X LOCTR X part 1 AREA1 DS CL X part 1 AREA2 DS CL X part 1 PGM LOCTR PGM1 part 2 PGM1 part 2 Y LOCTR Y part 1 TAB DS CL Y part 1 TAB DS CL Y part 1 PGM LOCTR PGM1 part 3 PGM1 part 3 X LOCTR X part 2 AREA11 DC C'*' X part 2 AREA12 DC F'0' X part 2 PGM LOCTR PGM1 part 4 LTORG PGM1 part 4 END Generated Object CSECT PGM1 (with “7 parts”) PGM1 = (part 1 of loc counter PGM1) + (part 2 of loc counter PGM1) + (part 3 of loc counter PGM1) + (part 4 of loc counter PGM1) + (part 1 of loc counter X) + (part 2 of loc counter X) + (part 1 of loc counter Y) Commands

Assembler commands - LTORG
LTORG command causes the declaration of all literals so far referenced. Before definition, Location Counter is aligned to a boundary 8 address. Because of this characteristic, you’ll sometimes find 2 LTORGS one followed by another: the first to align and declare all literals, and the second one just to align the location counter. One could use , instead of the 2nd LTORG, a CNOP 0,8 or a DS 0D. No symbol nor operands are allowed. LTORG , DECLARING LITERALS LTORG , ALIGNMENT Note that to insert the coments, as no operands are allowed, one must insert the comma before the comments to indicate the operands absence. Commands

Assembler commands - LTORG
MVC E,DSEKCOP3 IEV044 *** ERROR *** UNDEFINED SYMBOL 00047C D B MVC G,DSEKCPO4 D B02C C MVC I,DSEKCPO5 D20A B037 B MVC DSEKCPO6,DSEKCPO7 63 * 00048E 41C0 7FFF FFF LA 12,Z-1 LA 12,Z+1 IEV034 *** ERROR *** ADDRESSABILITY ERROR LA 12,Z 00049A 58C0 34A A L ,=A(Z) 00049E D20F AC AC MVC A,=C'*' 69 * 0004A LTORG , 0004A =A(Z) 0004AC 5C =C'*' 73 * 0004AD 00 0004AE D20F E E MVC A,=C'*' 0004B LA 12,Z 0004B8 58C0 40E E L ,=A(Z) Commands

Assembler commands - OPSYN
OPSYN (Operation Synonim) The OPSYN command establishes an equivalence between a symbol and an operation code of a machine instruction or an Assembler command. Syntax: Symbol OPSYN [code] Where: Symbol – any valid Assembler symbol or operation code (if the operand is omitted). Code – any valid operation code. If omitted, the command unassigns the operation code previously assigned as symbol. The OPSYN command must be inserted after ICTL (if ICTL is present) and can br preceded only by EJECT, ISEQ, PRINT, SPACE and TITLE. Example: MYMOVE OPSYN MVC MVC OPSYN Commands

Assembler commands - ORG
The ORG command alters the value of the Location Counter, setting it up with the value of the expression specified as operand. Syntax: symbol ORG [expression] If the operand is omitted the value set in the Location Counter is the highest it has reached. Example: Note: the symbols used as ORG operands must be defined before ORG command. Loc.Counter Loc.Counter Before After 0AB84C AB94C TABNUM DC X'FF' Location Counter reaches 0AB94C 0AB94C AB93C ORG TABNUM Return to 0AB93C 0AB93C AB DC X'00' Reaches 0AB946 0AB AB94C ORG Return to the highest so far: 0AB94C Commands

Assembler commands - POP
The POP command restores the PRINT and/or USING status saved by PUSH command. Syntax: POP PRINT POP USING POP PRINT,USING POP USING,PRINT Commands

Assembler commands - PRINT
The PRINT command is used to control the contents of the listing the assembler produces. Syntax: PRINT options The options must be specified separeated by commas, and they indicate to the assembler what must be printed or not. Valid options are: ON Listing is produced OFF Listing not produced (at least until next PRINT ON) GEN Macro-instruction-generated instructions must be listed. NOGEN Macro-instruction-generated instructions mustn’t be listed. DATA The contents of the defined areas must be listed. NODATA The contents of the defined areas must have its first (or max) 8 bytes listed. PRINT OFF,DATA If no PRINT command is specified (or until it is specified) it is assumed PRINT ON,GEN,NODATA One can use as many PRINT commands as necessary / desired. Commands

Assembler commands - PUNCH
The PUNCH command indicates to the Assembler to write to the object file 1 record which value is the value specified as the PUNCH operand. Syntax: PUNCH a Where a is a string from 1 to 80 characters between apostrophes. If the character is an apostrophe (') or an ampersand (&), it must be twice specified. Example: PUNCH ' CATALR MOD' The result record is: pos : spaces pos : CATALR pos : spaces pos : MOD pos : spaces Commands

Assembler commands - PUSH
The PUSH command saves the status of PRINT and USING. Syntax: PUSH PRINT PUSH USING PUSH PRINT,USING PUSH USING,PRINT Commands

Assembler commands - REPRO
The REPRO command indicates to the Assembler to write to the object file 1 record which value is the value of the statement following the REPRO command. No symbol nor operands are allowed. CATALR MOD At this point a record with “CATALR MOD” is written to the SYSPUNCH file. Commands

Assembler commands - RMODE
RMODE (Residence Mode) This command is used to indicate to the assembler the residence mode associated to a Control Section. [symbol] RMODE n n may be 24 or ANY. Symbol is optional. If omitted, the residence mode will be associated to the blank (no name) Control Section that must exist in the program. If specified, the residence mode will be associated to the Contro,l Section with the same name as indicated in the symbol. The operand indicates the residence mode that must be associated with the Control Section. One must specify 24 (24-bit residence = the CSECT must reside bellow the 16MB line), or ANY (24-bit or 31-bit residence = the CSECT may reside bellow or above the 16MB line). There must be only one RMODE for each Control Section. The RMODE command may be specified at any point in the program. RMODE ANY is not compatible with AMODE 24. Commands

Assembler commands - RMODE
RMODE (Residence Mode) If one specifies only AMODE or RMODE (or even none of them) the defaults are: Specified Assumed None AMODE 24 and RMODE 24 AMODE RMODE 24 AMODE RMODE 24 AMODE ANY RMODE 24 RMODE AMODE 24 RMODE ANY AMODE 31 Commands

Assembler commands - SPACE
The SPACE command, when detected by the assembler, results in a skip of n lines in the SYSPRINT listing, where n is specified in the operand (if omitted, 1 is assumed). SPACE [n] Example: SPACE Commands

Assembler commands - START
This command sets the initial value in the LOCATION COUNTER. It must be one of the first commands in the source program (it can’t have any instruction or command that alters the Location Counter before the START command). The syntax is: [symbol] START a where: Symbol: START command defines the first Control Section (CSECT) of the program. If the symbol is specified, it will be the section’s name. If not specified, the first control section is considered as no name. a = Auto-defined term = its value must be multiple of 8.Tit indicates the initial value of the Location Counter. If omitted, zero is assumed. PROG START X'308' START If START command is omitted, START is assumed. Commands

Assembler commands - TITLE
The TITLE command specifies the title of the listing produced by the Assembler. Syntax: [symbol] TITLE a Symbol --- in VSE : 1 to 4 characters (it will be used to fill positions 73 to 76 of the object program records). a -- 1 to 100 characters string between apostrophes. If a character must be an apostrophe (') or an ampersand (&), it must be twice specified. Example: P TITLE 'EMISSAO NOTAS FISCAIS' At each TITLE command a page skip is provided. Commands

Assembler commands - USING
USING (Usando) The USING command is used to provide addressability to symbols, by indicating to the Assembler: a) The value of the 1st base register (1st operand) b) The base register(s) of the program (2nd operand, 3rd operand and so on) Syntax: USING a,1br[,2br,[3br] [16br]] Where a is an expression indicating to the Assembler the value the first base register [1br] is assumed to have when the program is running. If a second base register [2br] is specified, it is assumed to have a when program is running. If a third base register [3br] is specified, it is assumed to have a when program is running. And so on. USING *,3,8 In this example: registers 3 and 8 are the base registers. Register 3 is assumed to have the value of the Location Counter when the program is running. Register 8 is assumed to have the value of the Location Counter+4096 when the program is running. Note that the USING command only warns the Assembler about the value at execution time; it DOES NOT LOAD the value. It’s the programmer’s responsibility to load the correct value (in the example corresponding to the values of the Location Counter and Location Counter+4096. Normally one uses the BALR instruction to load the first base register and LA to load the other ones. For DSECTs : specify the DSECT symbol as the first operand. Commands

Assembler commands - WXTRN
WXTRN (Weak Extrn) This command is similar to the EXTRN command, but: - with the EXTRN command the Linkage Editor searches autoimatically the libraries to find the modules that contains the symbols specified as operands in teh EXTRN command(s). - with the WXTRN command no auto search is provided. The references will be solved by the Linkage Editor only if the specified symbols are defined: -- in a module link-edited and loaded together with the program with the WXTRN command OR -- in a module linked from a library because it has an EXTRN command in another module (linkedited and loaded together with the program with WXTRN). Syntax: WXTRN symbol[,symbol ] Example: WXTRN MOD Commands

Assembler commands - Defining areas

DC = Define Constant to define areas WITH contents (storage allocation, with contents, with a name [symbol], address [value], length attribute and type attribute) DS = Define Storage to define areas WITHOUT contents (storage allocation, with a name [symbol], address [value], length attribute and type attribute) Commands

What does exactly mean to allocate an area without contents (without an initial value)? (e.g. DS in Assembler, or a field declared without the VALUE clause in Cobol) LOADER ??????????? Executable Storage Instructions Areas with contents (DC) Areas without contents (DS) Commands

General syntax: Da = duplication attibute: how many areas to define Type = contents (value) type; it’s used to attribute the value and to establish the length attibute if La is not specified. NO validation is done at assembly time. La = Length attribute Ic = initial contents (value) [name] DC [Da]type[La]Ic [name] DS [Da]type[La][Ic] Commands

Examples: [name] DC [Da]type[La]Ic SEPARAT1 DC 132CL1’*’ Da=132;Type=C;La=L1;Ic=‘*’ * Declares 132 areas, 1 byte each (all 132 bytes with *) SEPARAT2 DC CL132’*’ Da=omitted;Type=C;La=L132;Ic=‘*’ * Declares 1 area, length=132 bytes ( 1st byte has * all others with spaces ) CONTLIN DC PL2’99’ Da=omitted;Type=P;La=L2;Ci=‘99’ * Declares 1 area 2 bytes long (value=99 in packed decimal) ADRSTAB DC A(TABAGE) Da=omitted;Type=A;La=omitted;Ic=(TABAGE) * Declares 1 área 4 bytes long (value = address of TABAGE) Commands

Examples: [name] DS [Da]type[La][Ic] SEPARAT1 DS 132CL1 Da=132;Type=C;La=L1;Ic=omitted * Declares 132 areas, 1 byte each (NO INITIAL CONTENTS) SEPARAT2 DS CL Da=omitido;Type=C;La=L132;Ic=omitted * Declares 1 area, length=132 bytes (NO INITIAL CONTENTS) CONTLIN DS PL Da=omitted;Type =P;La=L2 ;Ic=omitted * Declares 1 area 2 bytes long (NO INITIAL CONTENTS) ADRSTAB DS A Da=omitted;Type =A;La=omitted ;Ic=omitted * Declares 1 area 4 bytes long (NO INITIAL CONTENTS) Commands

Defining areas – DC (define constant)
Area WITH value (initial contents) Commands

Assembler commands - Defining areas - Summary
Area types - summary Type Length assumed Alignment Valid Length Constants p/operand Filled From-To Filled with Truncated at Valid characters Each char C enough byte 1 to 256 1 LR spaces Right qualquer 1 byte X multiple RL X’0’ Left 0 to F ½ byte B B’0’ 0 to 1 1 bit F 4 bytes FullWord 1 to 8 (1) + - 0 to 9 (2) (4) H 2 bytes HalfWord (3) (4) P Byte 1 to 16 ½ byte (5) Z C’0’ D 8 bytes DoubWord -x- A 1 to 4 expression Y 1 to 2 S 2 remarks:- (1) 0's if positive number; 1's if negative number (2) Up to 2**31 - 1 (3) Up to 2**15 - 1 (4) Decimal-point does not use any space (5) The sign uses 1/2 byte Commands

Defining areas – Type C (character)
C-type DC (character) [name] DC [Da]C[La]Ic DC/DS Summary

Defining areas – Type C (character)
Each character occupies 1 bytes (EBCDIC format) If no length attribute specified: assumed (the default is) the enough to fit the initial contents. If length attribute (La) specified: the La will be considered rather than the enough to fit the value. If La specified is greater than the enough to fit the value, the remaining bytes to the right will be filled with spaces (X'40'). If the length attribute specified is less than the enough to fit the value specified, the rightmost characters of the value will be truncated (error will be flagged). Se o tamanho for insuficiente, será feito truncamento à direita (e será indicado erro). Maximum length = 256 bytes. When the desired character in value is apostrophe (“’”) or ampersand (“&”) it is needed to specify it twice. DC CL1'*' C DC CL1'*' C5C DC CL1'*' C DC CL2'*' C40 DC CL2'*' C405C40 DC C'ABC' C1C2C3 DC CL1'ABC' C1 DC C'A&&B' C150C2 DC C‘JO''S' D1D67DE2 DC C'''' D DC/DS Summary

Defining areas – Type X (hexadecimal)
X-Type DC (hexadecimal) [name] DC [Da]X[La]Ic DC/DS Summary

Defining areas – Type X (hexadecimal)
Valid characters: hexadecimal algarisms (0 to F) Each hexadecimal algarism occupies ½ byte. Field is filled from right to left. If La specified is greater than the enough to fit the value, the remaining half-bytes to the left will be filled with x’0’. If La specified is less than the enough to fit the value, the leftmost half-bytes will be truncated. Maximum length = 256 bytes. Multiple definitions per constant are allowed (see last example). DC XL1'0B' B DC X'5C' C5C5C DC XL3'5C' C DC XL2'AB0C14' 0C14 DC X'1A2' A2 DC X'00A,B,5A8' 000A0B05A8 DC/DS Summary

Defining areas – Type B (binary)
B-type DC (binary) [name] DC [Da]B[La]Ic DC/DS Summary

Defining areas – Type B (binary)
Valid characters: binary algarisms (0 and 1) Each binary algarism occupies 1 bit. Field is filled from right to left. If La specified is greater than the enough to fit the value, the remaining bits to the left will be filled with binary zeros. If La specified is less than the enough to fit the value, the leftmost bits will be truncated. Maximum length = 256 bytes. Multiple definitions per constant are allowed (see last example). DC BL1'0' DC BL2' ' 0089 DC B'0101' DC BL2'1' DC B'1' DC B'1,00101,001' DC/DS Summary

Defining areas – Type F (full word)
F-type DC (full-word) [name] DC [Da]F[La]Ic DC/DS Summary

Defining areas – Type F (full word)
The value must be specified in decimal (Assembler will convert it to binary to fill the full-word) If no sign is specified, number will be assumed positive. If sign is specified, it must be unique, and must come before the value. If no La is specified, ALIGNMENT will be done to next address multiple of 4, before the area allocation. If La is specified, NO ALIGNMENT will be done. Maximum length = 256 bytes. Multiple definitions per constant are allowed (see last example). DC F'138' A DC F'+138' A DC F'-138' FFFFFF76 DC F'4,392' DC/DS Summary

Defining areas – Type H (half word)
H-type DC (half-word) [name] DC [Da]H[La]Ic DC/DS Summary

Defining areas – Type H (half word)
The value must be specified in decimal (Assembler will convert it to binary to fill the half-word) If no sign is specified, number will be assumed positive. If sign is specified, it must be unique, and must come before the value. If no La is specified, ALIGNMENT will be done to next address multiple of 2, before the area allocation. If La is specified, NO ALIGNMENT will be done. Maximum length = 256 bytes. Multiple definitions per constant are allowed (see last example). DC H'138' A DC H'+138' A DC H'-138' FF76 DC H'4,392' DC/DS Summary

Defining areas – Type P (packed)
P-type DC (Packed) [name] DC [Da]P[La]Ic DC/DS Summary

Defining areas – Type P (packed)
The value must be specified in decimal. Each decimal algarism occupies ½ byte, plus ½ byte to the sign. Maximum length = 16 bytes (31 algarisms). Field is filled from right to left. If La specified is greater than the enough to fit the value, the remaining half-bytes to the left will be filled with binary zeros. If La specified is less than the enough to fit the value, the leftmost half-bytes will be truncated. If no La is specified, it will be allocated the enough to fit the value (including ½ byte for the sign). Remember that if you specify an even number of algarisms, it will be needed one more half-byte to complete the field. Multiple definitions per constant are allowed (see 3rd example). DC P'122' C DC P'10' C DC P'-345,45,21.6,7' 345D045C216C7C DC P'0' C DC P'+66' C DC PL3'1' C DC PL2'43556' C DC P'1' C1C1C DC/DS Summary

Defining areas – Type Z (zoned)
Z-type DC (zoned) [name] DC [Da]Z[La]Ic DC/DS Summary

Defining areas – Type Z (zoned)
The value must be specified in decimal. Each decimal algarism occupies 1 byte. Maximum length = 16 bytes (16 algarisms). Field is filled from right to left. If La specified is greater than the enough to fit the value, the remaining half-bytes to the left will be filled with zoned zeros (x’F0’). If La specified is less than the enough to fit the value, the leftmost bytes will be truncated. If no La is specified, it will be allocated the enough to fit the value. Multiple definitions per constant are allowed (see 2nd example). DC Z'122' F1F2C2 DC Z'-345,45' F3F4D5F4C5 DC Z'+66' F6C6 DC ZL3'1' F0F0C1 DC ZL2'43556' F5C6 DC Z'1' C1C1C1 DC/DS Summary

Defining areas – Type A (address)
A-type DC (address) [name] DC [Da]A[La]Ic DC/DS Summary

The value must be specified as an expression (Assembler will convert it to a value / address to fill the full-word) If no La is specified, ALIGNMENT will be done to next address multiple of 4, before the area allocation. If La is specified, NO ALIGNMENT will be done. Multiple definitions per constant are allowed (see last example). DC A(TABELA) DC A(TABELA-50) DC A(*) DC A(259) CAMPO DC 3A(*-CAMPO) DC A(TCABC+28*52) DC A(FIM-COMECO) DC A(1,2,3) DC/DS Summary

IMPORTANT: Addresses with relocatable values (green) are updated by Linkage Editor and Loader; the absolute addresses (red) keep unchanged . DC A(TABELA) DC A(TABELA-50) DC A(*) DC A(259) CAMPO DC 3A(*-CAMPO) DC A(TCABC+28*52) DC A(FIM-COMECO) DC A(1,2,3) DC/DS Summary

Example: (part of a program) 0008A0 47F0 38AC AC B IHB0004A 008A IHB0004 EQU * 0008A B DC A(ENTRA) 0008A B DC A(SAI) 008AC IHB0004A EQU * (part of the RELOCATION DICTIONARY of the program) RELOCATION DICTIONARY POS.ID REL.ID FLAGS ADDRESS C B9 C C C C C C C A4 C A8 A46 A48 A54 A56 DC/DS Summary

Example: ... VVV DC A(VALIDS) VALIDS DC C’AEIOUaeiou’ Souce program (VALIDATE routine; suppose that VALIDS address is X’00001BC0’) 00001BC0 C1C5C9D6E A4 Object program to be called (suppose length = 4K = X’1000’) Caller : from X’0000’ to X’9FFF’) Executable CALL VALIDATE Caller (main) object program (suopose length = 40K = X’A000’) Called routine: starting address = X’A000’ : occupies in the executable from X’A000’ to X’AFFF’ Assembler Lked Adds called routine to the caller program and ADJUSTS the relocatable address variables. VVV contents is adjusted to X’0000BBC0’ 0000BBC0 DC/DS Summary

Example: Loader Loads the executable program into storage (e.g. at address X’0BC40000’) and ADJUSTS the relocatable address constants. VVV contents is adjusted to X’0BC40000’ + X’0000BBC0’ = X’0BC4BBC0’ Executable program ... 0000BBC0 Storage Executable program loaded (LOAD POINT) at address X’0BC40000’ 0BC4BBC0 Load Point = X’0BC40000’ DC/DS Summary

Defining areas – Type Y (2-byte address)
Y-type DC (address with 2 bytes) [name] DC [Da]Y[La]Ic DC/DS Summary

Defining areas – Type Y (2-byte address)
The value must be specified as an expression (Assembler will convert it to a value / address to fill the half-word) If no La is specified, ALIGNMENT will be done to next address multiple of 2, before the area allocation. If La is specified, NO ALIGNMENT will be done. Multiple definitions per constant are allowed (see last example). Note that the maximum allowed value is x'FFFF‘. DC Y(TABELA) DC Y(TABELA-50) DC Y(*) DC Y(259) DC Y(TCABC+28*52) DC Y(FIM-COMECO) DC Y(1,2,3) IMPORTANT: Addresses with relocatable values are updated by Linkage Editor and Loader; the absolute addresses keep unchanged . DC/DS Summary

Defining areas – Type S (Base+Shift address)
S-type DC (base + shift address) [name] DC [Da]S[La]Ic DC/DS Summary

Defining areas – Type S (Base+Shift address)
The value must be specified as an expression (Assembler will convert it to a base+shift addres to fill the half-word) If no La is specified, ALIGNMENT will be done to next address multiple of 2, before the area allocation. If La is specified, NO ALIGNMENT will be done. Multiple definitions per constant are allowed (see last example). DC S(TABELA) DC S(TABELA-50) DC S(*) DC S(TCABC+28*52) DC S(*,*+2,*+4) DC/DS Summary

Defining areas – Type V (external address)
V-type DC (external address) [name] DC [Da]V[La]Ic DC/DS Summary

Defining areas – Type V (external address)
It is analogue to the A-type constant, with the difference that the address is not possible to be solved at assembly time due to external symbol reference (e.g. an external routine). The value is set to zero, and is filled in the object program at linkedit / load time. DC V(ROUTINE) DC/DS Summary

Defining areas – Type Q (external DSECT address)
Q-type DC (external DSECT shift) [nome] DC [ad]Q[at]ci DC/DS Summary

Defining areas – Type Q (external DSECT address)
This constant is used to do reference to a shift in an external DSECT. The value is set to zero, and is filled in the object program at linkedit time. The value must be specified as an expression (Assembler will conThe symbol refered to in the value must be previously externally defined as a DXD symbol or as a DSECT. DC Q(DUMMYEXT) DC/DS Summary

Areas WITHOUT initial contents
Defining areas - DS DS - Define Storage Areas WITHOUT initial contents DC/DS Summary

DS command is used to define an area without initial contents.
Defining areas - DS DS command is used to define an area without initial contents. The syntax is analogue to the DC command. WARNING! If initial contents is specified it WON’T BE CONSIDERED. DS CL3 DS XL4 DS PL4'0' DS CL8 DC/DS Summary

DS command allows zero (0) duplication attribute. Examples:
Defining areas - DS DS command allows zero (0) duplication attribute. Examples: READAREA DS CL80 CODE DS CL10 DATE DS CL8 NAME DS CL50 CITY DS CL12 The duplication attribute does not define any area, it only “warns” that the next 80 bytes will be the area named READAREA (READAREA length attribute is 80). In other words, the field starting at the byte pointed by the Location Counter is 80 bytes length and is named READAREA. DC/DS Summary

The duplication attribute zero is often used to do alignment:
Defining areas - DS The duplication attribute zero is often used to do alignment: FLDWITH4 DS F BYTE DS CL1 BYTE DS CL1 BYTE DS CL1 BYTE DS CL1 In this case, the assembler: - aligns to the next boundary 4 address (address multiple of 4) due to the F-type specified), and then allocates the fields BYTE1, BYTE2, BYTE3 e BYTE4. DC/DS Summary

Another example of alignment use:
Defining areas - DS Another example of alignment use: ALFA DC F’0’ BETA DC C’XYZ’ DS 0H GAMA DS CL1 DELTA DS CL1 ALFA is aligned because the F-type constant do the alignment. BETA is aligned due to the alignment and length of ALFA. GAMA, if it was declared just after BETA, won’t be aligned because BETA has 3 bytes. To align GAMA (to a boundary 2 address) it was included the H-type DS declaration with duplication attribute of zero. Delta Gama (no name) Beta Alfa DC/DS Summary

Defining areas - DS Another use of DS command is to redefine areas (to attribute different names to same physical areas). See bellow: AREA DS CL80 A1PART1 DS CL10 A1PART2 DS CL10 A1PART3 DS CL10 A1PART4 DS CL10 A1PART5 DS CL10 A1PART6 DS CL10 A1PART7 DS CL10 A1PART8 DS CL10 ORG , RETURN TO AREA1 ADDRESS AREA DS CL80 A2PART1 DS CL20 A2PART2 DS CL20 A2PART3 DS CL20 A2PART4 DS CL20 AREA DS CL80 A3PART1 DS CL5 A3PART2 DS CL5 A3PART3 DS CL20 A3PART4 DS CL30 A3PART5 DS CL3 A3PART6 DS CL4 A3PART7 DS CL13 DC/DS Summary

Machine Instructions MACHINE INSTRUCTIONS

Machine Instructions – Hints and Tips

Machine Instructions – Hints and Tips 1
1 - STORE = FROM register TO storage 2 - LOAD = FROM storage TO register 3 - xxxxR = RR instruction, operands are both registers Example: AR,SR, LR, MR, DR, LTR 4 - xxxxI = SI instruction, 1 operand is an immediate operand; it is the 2nd byte of the instruction, and is specified via an self-defining term (1 byte length) Example: MVI, SI, NI, OI, XI, etc 5 - xxxxP = SS instruction, decimal packed operands, 2 lengths specification Example: AP, SP, MP, DP, ZAP 6 - xxxxH = RX instruction, operands are 1 register and 1 halfword storage field Example: LH, SH, AH

7 - Nxxxx = boolean instruction AND Example: NI, NC, N, NR 8 - Oxxxx = boolean instruction OR Example: OI, OC, O, OR 9 - Xxxxx = boolean instruction Exclusive OR Example: XI, XC, X, XR Most instructions (except CVD and the STORE ones STC, ST, STH, STCM, STM): symbol instruction receiver_operand,emitter_operand STORE and CVD instructions: symbol instruction emitter_operand,receiver_operand

12 - SS-L instructions (only one length) are: MVN, MVC, MVZ, NC, CLC, OC, XC, TR, TRT, ED, EDMK, MVCIN Maximum length of each operand is 256 bytes. 13 - SS-L1/L2 instructions (2 lengths) are: MVO, PACK, UNPK, ZAP, CP, AP, SP, MP, DP Maximum length for each operand is 16 bytes. 14 – SRP instruction is an exception in the SS group: it has a reference to a length (1st half of the 2nd byte), and a round (in the other half of the 2nd byte)

15 – Use of Boolean instructions: OR = To force bits to 1 (turn ON bits) This can be used to (for instance) : (a) Set program flags to ON (b) Transform lowercase leters into uppercase letters (mask : note in an EBCDIC table that the difference between lowercase and uppercase letters is always x’40’ (b’ ’); turning the 2nd bit ON one can transform a lowercase letter into an uppercase letter. (c) Transform a binary number into the nearest high odd number (turning rightmost bit ON) Example: is decimal 254. Turning rightmost bit ON: it becomes decimal 255

15 – Use of Boolean instructions: AND = Force bits to 0 (turn bits OFF) This can be used to (for instance) : (a) Set program flags to OFF (b) Transform uppercase leters into lowercase letters (mask : note in an EBCDIC table that the difference between uppercase and lowercase letters is always x’40’ (b’ ’); turning the 2nd bit OFF one can transform an uppercase letter into a lowercase letter. (c) Transform a binary number into the nearest low even number (turning rightmost bit OFF) Example: is decimal 255. Turning rightmost bit OFF: it becomes decimal 254

15 – Use of Boolean instructions: XOR (ou exclusivo) = To invert bit setting (turns OFF if it is on, turns ON if it is OFF) This can be used to (for instance) : (a) Inverte program flags (toggle flags) (b) Transform lowercase into uppercase letter and vice-versa (mask ) : letter x1xx xxxx becomes x0xx xxxx letter x0xx xxxx becomes x1xx xxxx (c) Transform binary even numbers into odd numbers and vice-versa: (mask ) : rightmost bit is inverted (d) Exchange the contents of 2 area without a 3rd auxiliary area : XOR A,B XOR B,A XOR A,B (e) “Clear” (move binary zeros) an area : XOR A,A

16 – Arithmetic and bit shift operations (algebraic / logic operations): Unless othewise stated, these operations are done algebraically. This is always true for decimal packed fields. For binary fixed point numbers (in storage and/or registers) some operations that work algebraically and other operations work logically. Algebraic operations uses: 15-bit binary numbers + 1 bit sign for 2 byte numbers 31-bit binary numbers + 1 bit sign for 4 byte numbers 63-bit binary numbers + 1 bit sign for 8 byte numbers Logical operations assume numbers are always positive and uses: 16-bit binary numbers for 2 byte numbers 32-bit binary numbers for 4 byte numbers 64-bit binary numbers for 8 byte numbers

Machine instructions (alphabetically)
AH AL ALR AP AR BAL BALR BAS BASR BASSM BC BCR BCT BCTR BSM BXH BXLE C CDS CH CL CLC CLCL CLI CLM CLR CP CR CS CVB CVD D DP DR ED EDMK EX IC ICM IPM L LA LCR LH LM LNR LPR LR LTR M MC MH MP MR MVC MVCIN MVCL MVI MVN MVO MVZ N NC NI NR O OC OI OR PACK S SH SL SLA SLDA SLDL SLL SLR SP SPM SR SRA SRDA SRDL SRL SRP ST STC STCK STCM STH STM SVC TM TR TRT TS UNPK X XC XI XR ZAP

(Some) Machine instructions (by group)
Storage to Storage move : MVC, MVZ, MVN, MVI, MVO, ZAP, MVCL, PACK, UNPK, MVCIN - Register to Storage move : ST, STH, STM, STC, STCM, CVD - Storage to Register move : L, LH, LM, IC, ICM, CVB Register to Register move : LR, LPR, LNR, LCR, LTR - Arithmetic with Storage fields in the packed format : AP, SP, MP, DP, SRP - Arithmetic with Registers (fixed point binary) : AR, SR, MR, DR, ALR, SLR Arithmetic with Register and Storage (fixed point binary) : A, S, M, D, AH, SH, MH, AL, SL - Compare : CP, CLC, CLI, CLCL, C, CH, CL, CLM, CR, CLR - Branch : BC, BCR - Loop Control : BCT, BCTR, BXH, BXLE - Edition : ED, EDMK - Byte Translation and test: TR, TRT - Register Shift : SLL, SRL, SLDL, SRDL, SLA, SRA, SLDA, SRDA - Boolean Algebra : N, O, X, NR, OR, XR, NI, OI, XI, NC, OC, XC - Load and branch : BALR, BAL, BAS, BASR, BASSM, BSM - Misc : LA, TM, EX, SVC, MC, SPM, IPM, STCK, TS, CS, CDS

Machine Instructions Hints: what instruction do I have to use to move data from a place to another? Origin Destination Instruction Storage MVC Register LR Storage (zoned) Storage (packed) PACK UNPK (maybe, additionally, MVZ / OI) ST Storage (binary) L Register (binary) CVB CVD (address) LA [ or L reg,=A(address) ] Storage (contents=address) LA + ST [ or L + ST ]

Machine Instructions - A
A (ADD) Machine Instruction Code 5A (RX Instruction) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions 0005,0008 Instruction A adds algebraically the binary number in the 1st operand and the bynary number in a storage field (2nd operand – a full-word). Result is loaded into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register 1st operand after nd operand after A 5,=F'259' BF.D 00.00.C0.D A 7,FULL D A 7,4(2,8) FF.FF.FE 07.FF.FF.FF A 7,4(2) FF.FF.FF FF.FF.FF.FF 07.FF.FF.FE FF.FF.FF.FF A 7,4(,8) FF.FF.FF.FF FF.FF.FF.FF FF.FF.FF.FF Mach.Inst.Summary

Machine Instructions - AH
AH (Add Halfword) Machine Instruction Code 4A (RX Instruction) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions 0005,0008 This instruction adds algebraically two binary numbers. One of them is in the register specified as 1st operand, and the other is a storage half-word specified as 2nd operand. Before the operation is executed, the half-word is internally expanded to 32 bits by repeating (to the left) the leftmost bit (sign bit). Result is loaded into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register 1st operand after nd operand after AH ,=H'259' B.C C.C AH ,HALF D D A D AH ,4(2,8) (decimal ) (decimal –30584) (decimal ) AH ,4(2) (decimal ) (decimal ) (decimal ) Mach.Inst.Summary

Machine Instructions - AL
AL (Add Logical) Machine Instruction Code 5E (RX Instruction) Condition code 00 Result = 0, sign not lost 01 Result <> 0, sign not lost 10 Result = 0, sign lost 11 Result <> 0, sign lost Possible Interruptions 0005 This instruction adds logically two binary numbers. One of them is in the register specified as 1st operand, and the other is a storage full-word specified as 2nd operand. Both numbers are considered as positive 32-bit numbers. Result is loaded into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register 1st operand after nd operand after AL ,=F'259' AL ,FULL B0.C4.E 00.B0.C4.E AL ,4(2,8) 7F.FF.FF.FF AL ,4(2) FF.FF.FF.FF AL ,4(,8) Mach.Inst.Summary

Machine Instructions - ALR
ALR (Add Logical Register) Machine Instruction Code 1E (RR Instruction) Condition code 00 Result = 0, sign not lost 01 Result <> 0, sign not lost 10 Result = 0, sign lost 11 Result <> 0, sign lost Possible Interruptions No interruptions occur This instruction adds logically the contents of two binary numbers, both located in registers. Both numbers are considered as positive 32-bit numbers. Result is loaded into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register 1st operand after nd operand after ALR 7, B0.C4.E 00.B0.C4.E ALR 8, F.FF.FF.FF ALR 10, FF.FF.FF.FF ALR 10, Mach.Inst.Summary

Machine Instructions - AP
AP (Add Packed) Machine Instruction Code FA (SS Instruction – L1 e L2) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions 0001,0004,0005,0007,000A This instruction adds the contents of two packed numbers, both located in storage fields. Both numbers must be in the decimal packed format. Result is stored into 1st operand field. Examples: AP FLDA,FLDB before after FLDB C C FLDA C C AP FLDA,FLDA FLDA C C See more examples following: Mach.Inst.Summary

Machine Instructions - AP
AP (Add Packed) Machine Instruction Code FA (SS Instruction – L1 e L2) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions 0001,0004,0005,0007,000A Suppose the operands with the length and values shown in the “before” line 1st operand before nd operand before 1st operand after nd operand after AP HOWMANY,=P'1' F C C C AP ARL+2(5),ARL+7(2) C C C C AP TOTAL,2(3,7) C D C D AP 4(3,8),WALFA F C C C AP 7(07,8),14(2,3) C 00.5C C 00.5C AP GRANDTOT,SMALLTOT C C C Mach.Inst.Summary

Machine Instructions - AR
AR (Add Register) Machine Instruction Code 1A (RR Instruction) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions 0008 This instruction adds the contents of two binary numbers, both located in registers. The value of the register 2nd operand is added to the value of the register 1st operand. Result is stored into register 1st operand. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register 1st operand after nd operand after AR 7, FF.FF AR 2, FF.FF FF.FF 00.01.FF.FE FF.FE Mach.Inst.Summary

Machine Instructions – BAL
BAL (Branch And Link) Machine Instruction Code 45 (RX Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur BAL instruction is similar to the BALR instruction; the difference is that the address where the branch is to be made to (specified by the 2nd operand) is the instruction address in the base+displacement format (rather than the address in the register as in the BALR instruction). Note that to load the next instruction address (generally used as the return address when branching to execute a routine) BAL loads the last 4 bytes of PSW into 1st operand register. Examples: BAL loads the address of instruction labeled RETINS into register 9 BAL ,ROUTINE BAL ,WRTHDR BAL ,2(5) BAL (,8) BAL ,2(5,8) ... BAL 9,ROUTINE RETINS EQU * continuation ROUTINE ST 9,SAVEREG9 .... L 9,SAVEREG9 BR 9 Save register 9 (return address) into SAVEREG9 Restore return address Goback (to RETINS) Mach.Inst.Summary

Machine Instructions - BALR
BALR (Branch And Link Register) Machine Instruction Code 05 (RR Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur BALR instruction is similar to the BAL instruction; the difference is that the address where branch is to be made to (specified by the 2nd operand) is the value of the register 2nd operand (rather than the address in the base+displacement format as in the BAL instruction). Important: if the second operand is register zero, branch won’t be executed. Note that to load the next instruction address (generally the return address) BALR loads the last 4 bytes of PSW. Examples: BALR loads the address of instruction labeled RETINS into register 14 BALR ,0 BALR ,15 ... LA 15,ROUTINE BALR 14,15 RETINS EQU * continuation ROUTINE ST 14,SAVEREG .... L 14,SAVEREG BR 14 Save register 14 (return address) into SAVEREG LA loads the address of instruction labeled ROUTINE into register 15 Restore return address Goback (to RETINS) Mach.Inst.Summary

Machine Instructions - BAS
BAS (Branch And Save) Machine Instruction Code 4D (RX Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur The address of the next instruction (following BAS) is loaded in the register 1st operand: Bytes 5, 6 and 7 (last 3 bytes of PSW) are loaded into bytes 1, 2 and 3 of the register Leftmost byte of register 1st operand is set to zero (this is the difference between BAS and BAL) After loading the address, there’s a branch (jump) to the instruction specified in the 2nd operand. Example: BAS 14,ROUTINE BAS loads the address of instruction labeled RETINS into register 9 bytes 1,2,3 and sets byte 0 with zero ... BAS 9,ROUTINE RETINS EQU * continuation ROUTINE ST 9,SAVEREG .... L 9,SAVEREG BR 9 Save register 9 (return address) into SAVEREG Restore return address Goback (to RETINS) Mach.Inst.Summary

Machine Instructions - BASR
BASR (Branch And Save Register) Machine Instruction Code 0D (RR Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur The address of the next instruction (following BASR) is loaded in the register 1st operand: Bytes 5, 6 and 7 (last 3 bytes of PSW) are loaded into bytes 1, 2 and 3 of the register Leftmost byte of register 1st operand is set to zero (this is the difference between BASR and BALR) After loading the address, there’s a branch (jump) to the instruction specified in the 2nd operand. Example: BASR 14,15 BASR sets register 14 byte 0 with zero and loads the address of instruction labeled RETINS into bytes 1,2,3 of register 14 ... LA 15,ROUTINE BASR 14,15 RETINS EQU * continuation ROUTINE ST 14,SAVEREG .... L 14,SAVEREG BR 14 LA loads the address of instruction labeled ROUTINE into register 15 Restore return address Save register 14 (return address) into SAVEREG Goback (to RETINS) Mach.Inst.Summary

Machine Instructions - BASSM
BASSM (Branch And Save and Set Mode) Machine Instruction Code 0C (RR Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur The address of the next instruction (following BASSM) is loaded in the register 1st operand: Bytes 4, 5, 6 and 7 (last 4 bytes of PSW) are loaded into bytes 0, 1, 2, 3 of the register 1st operand The value of register 2nd operand is loaded into bytes 4-7 of PSW; it includes leftmost bit (addressing mode) and (next) instruction address. Due to this, the addressing mode is (re)set and a branch is provided. Example: BASSM 14,15 BASSM : - Sets register 14 with the address of instruction labeled RETINS into register 14 (taken from PSW) Loads contents of register 15 into PSW bytes 4-7 (Addressing mode is set [from reg. 15 into PSW] ) and (Branch to ROUTINE is executed) LA loads the address of instruction labeled ROUTINE into register 15 LA 15,ROUTINE ICM 15,8,AMODE BASSM 14,15 RETINS EQU * continuation ... ROUTINE ST 14,SAVEREG .... L ,SAVEREG BR 14 ICM sets addressability mode into register 15 bits Restore return address Save register 14 (return address) into SAVEREG Goback (to RETINS) Mach.Inst.Summary

Machine Instructions - BC
BC (Branch on Condition) There are 2 branch instructions: BC (RX Instruction) and BCR (RR Instruction). But they have many auxiliary mnemonic codes, named extended mnemonic codes. The branch instruction execution is based upon the status of Condition Code (remember? Those 2 bits of PSW) and the mask provided in the instruction (in the left half of its 2nd byte). The 4 different status Condition Code can be are: 00, 01, 10 and 11. For each one of them there is a corresponding code: STATUS CODE 00 8 01 4 10 2 11 1 The MASK occupies half byte and indicates the condition in which branch MUST be done. It can vary from X'0' to X'F' (decimal 0 up to 15). MASK 8, CC B'00‘ = Branch executed MASK 4, CC B'01‘ = Branch executed MASK 2, CC B'10“ = Branch executed MASK 1, CC B’11’ = Branch executed Mach.Inst.Summary

BC (Branch on Condition) One can do a combination of the masks, by adding their value. For instance, if mask is X'C', it means that branch must occur if Condition Code is in the 8 or 4 status (8 + 4 = 12). If mask is zero, no branch will be done (NOP/NOPR = no operation). If mask is 15 (X'F') branch will be done no matter waht is the Condition Code setting, because 15 = all codes added ( ); it is an unconditional branch. Branch instructions with masks from 1 to 14 are conditional branches: the branch will only be done if Condition Code is apropriately set. See in the following slide the list of mnemonic codes, the valid masks and the extended mnemonic codes. Mach.Inst.Summary

BC (Branch on Condition) USE MNEMONIC MEANING BC/BCR EQUIVALENCE General B or BR Allways branches BC 15 or BCR 15 NOP or NOPR Never branches BC 0 or BCR 0 After BH or BHR Branch if A > B BC 2 or BCR 2 Compare BL or BLR Branch if A < B BC 4 or BCR 4 BE or BER Branch if A = B BC 8 or BCR 8 BNH or BNHR Branch if A < or = B BC 13 or BCR 13 BNL or BNLR Branch if A > or = B BC 11 or BCR 11 BNE or BNER Branch if A not = B BC 7 or BCR 7 After BO or BOR Branch if overflow BC 1 or BCR 1 Arithmetic BP or BPR Branch if R > BC 2 or BCR 2 Instructions BM or BMR Branch if R < BC 4 or BCR 4 BZ or BZR Branch if R = BC 8 or BCR 8 BNP or BNPR Branch if R < or = 0 BC 13 or BCR 13 BNM or BNMR Branch if R > or = 0 BC 11 or BCR 11 BNZ or BNZR Branch if R not = 0 BC 7 or BCR 7 After TM BO or BOR Branch if all bits 1 BC 1 or BCR 1 BM or BMR Branch if mixed BC 4 or BCR 4 BZ or BZR Branch if all bits 0 BC 8 or BCR 8 BNO or BNOR Branch if some are 1 BC 14 or BCR 14 Notes: A = 1st operand ; B = 2nd operand ; R = 1st operand after compute Mach.Inst.Summary

BC (Branch on Condition) The extended menmonic codes are: B = Branch NOP = No Operation BH = Branch High BL = Branch Low BE = Branch Equal BNH = Branch Not High BNL = Branch Not Low BNE = Branch Not Equal BO = Branch If Overflow BP = Branch If Plus BM = Branch If Minus BZ = Branch If Zero BNP = Branch If Not Plus BNM = Branch If Not Minus BNZ = Branch If Not Zero BO = Branch If Ones BM = Branch If Mixed BZ = Branch If Zeros BNO = Branch If Not Ones Mach.Inst.Summary

BC (Branch on Condition) BC (Branch on Condition) Machine Instruction Code 47 (RX Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur This instruction branches (or not) to another instruction. The format is: 1st byte = operation code = 47 2nd byte – 1st half = mask 2nd byte – 2nd half = index register for 2nd operand (branch instruction address) 3rd and 4th byte = 2 bytes with base+displacement of 2nd operand (branch instruction address) 1st operand is the mask; it indicates the condition branch must be done (or not). 2nd operand address is the address to branch to. If condition indicated by the mask is not satisfied, branch is not done, the execution resumes on the next intruction (instruction following BC). If condition indicated by the mask is satisfied, branch is done, the execution resumes on the intruction addressed by the 2nd operand. Mach.Inst.Summary

BC (Branch on Condition) BC (Branch on Condition) Machine Instruction Code 47 (RX Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur If one uses the mnemonic code, only one “operand” must be specified: the address to branch to; in this case the mask is implicit in the mnemonic. Example: BC ,AGAIN is the same as BE AGAIN BE is the same as BC 8. In this case, the branch will be done when condition code is 00. Other examples: B READ same as BC 15,READ BH AGAIN same as BC 2,AGAIN BL COMPARE same as BC 4,COMPARE BE 0(2) same as BC 8,0(2) BE 0(,4) same as BC 8,0(,4) BE 0(2,4) same as BC 8,0(2,4) NOP TOGGLE same as BC 0,TOGGLE1 Mach.Inst.Summary

BC (Branch on Condition) BC (Branch on Condition) Machine Instruction Code 47 (RX Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur Other examples: B READ same as BC 15,READ BNH LOOP same as BC 13,AGAIN BNL LOOP same as BC 11,COMPARE BNE 0(2) same as BC 7,0(2) BZ 0(,4) same as BC 8,0(,4) BNZ 0(2,4) same as BC 7,0(2,4) BM BTAB(15) same as BC 4,BTAB(15) Mach.Inst.Summary

Machine Instructions - BCR
BCR (Branch on Condition Register) BCR (Branch on Condition Register) Machine Instruction Code 07 (RX Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur BCR instruction is similar to BC instruction. SEE BC INSTRUCTION. The format is: 1st byte = operation code = x’07’ 2nd byte – 1st half = mask (1st operand) 2nd byte – 2nd half = register 2nd operand containing the branch instruction address 1st operand is the mask; it indicates the condition branch must be done (or not). 2nd operand register must contain the address to branch to. If condition indicated by the mask is not satisfied, branch is not done, the execution resumes on the next intruction (instruction following BCR). If condition indicated by the mask is satisfied, branch is done, the execution resumes on the intruction addressed by the 2nd operand. If one uses the mnemonic code, only the register 2nd operand must be specified. See examples following: Mach.Inst.Summary

Machine Instructions - BCR
BCR (Branch on Condition Register) BCR (Branch on Condition Register) Machine Instruction Code 07 (RX Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur BCR ,15 is the same as BER BER is the same as BCR 8. In this case, the branch will be done when condition code is 00. Other examples: BCR ,10 same as BHR 10 BR same as BCR 15,R7 BNER same as BCR 7,R10 BLR same as BCR 4,R15 Mach.Inst.Summary

Machine Instructions - BCT
BCT (Branch on CounT) Machine Instruction Code 46 (RX Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur This instruction has 2 operands: the first one is a register, and the second is an instruction address. BCT subtracts 1 from the register 1st operand and after it compares the resulting number with zero. · If result not equal to zero, it will provide a branch to the instruction referred in the 2nd operand · If result is zero the branch won’t be done, processing will resume at the next instruction after BCT. Examples: ... L 11,=F’200’ AGAIN CLC 0(3,5),CODE BE FOUND BCT 11,AGAIN NOTFND EQU * .... FOUND EQU * BCT 5,AGAIN BCT 2,0(4,7) BCT 2,0(4) BCT 2,0(,7) L loads into register 11 number of times loop must be repeated At the end of the set of loop instructions, BCT subtracts 1 from register 11. If zero not reached, branchs to AGAIN. If zero, resumes execution at NOTFND Mach.Inst.Summary

Machine Instructions - BCTR
BCTR (Branch on CounT Register) Machine Instruction Code 06 (RX Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur BCTR instruction has 2 operands, both in registers. BCTR subtracts 1 from the register 1st operand and after it compares the resulting number with zero. · If result not = zero, a branch is provided to the instruction whose address is in the register 2nd operand · If result is zero the branch won’t be done, processing will resume at the next instruction after BCTR. IMPORTANT: If 2nd operand is register zero, branch won’t be done; this is often used just to subtract 1 from a register, rather than, for instance, the S or SH instructions. Examples: LA 15,AGAIN L 11,=F’200’ AGAIN CLC 0(3,5),CODE BE FOUND ... BCTR 11,15 NOTFND EQU * .... FOUND EQU * BCTR 2,7 BCTR 4,0 L loads into register 11 number of times loop must be repeated LA loads into register 15 the address of AGAIN instruction At the end of the set of loop instructions, BCTR subtracts 1 from register 11. If zero not reached, branchs to AGAIN. If zero, resumes execution at NOTFND Mach.Inst.Summary

Machine Instructions - BSM
BSM (Branch and Set Mode) Machine Instruction Code 0B (RR Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur The PSW’s addressing mode (bit 32) is loaded into bit 0 of the register 1st operand; bits 1-31 remain unchanged , and after that PSW’s Bytes 4-7 is loaded with contents of register 2nd operand (including addressing mode bit and next instruction address) Thus a addressing mode setting is done followed by a branch. If 2nd operand is register zero, branch is not executed. Example: BSM 14,15 Mach.Inst.Summary

Machine Instructions - BXH
BXH (Branch on indeX High) Machine Instruction Code 86 (RX Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur 1st and 2nd operands are registers. 3rd operand is an instruction address. (a) The contents of register 2nd operand is added to the contents of register 1st operand, the result set into register 1st operand. (b) Result is compared with: · Contents of register 2nd operand (if it is an odd register) or · Contents of register following register 2nd operand (if it is an even register) If the compare result is · Greater than it will be executed a branch to the instruction addressed by 3rd operand · Less than or equal to the branch will not be executed; processing resumes at the instruction following BXH Mach.Inst.Summary

BXH (Branch on indeX High) Machine Instruction Code 86 (RX Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur Examples: BXH 7,8,AGAIN R7 = R8 + R7; If R7 > R9 Branch to AGAIN; * If R7 <= R9 next instruction BXH 7,9,AGAIN R7 = R9 + R7; If R7 > R9 Branch to AGAIN; BXH 7,9,8(4) R7 = R9 + R7; If R7 > R9 Branch to instruction * whose address is [ (contents R4) + x’008’ ] Mach.Inst.Summary

BXH (Branch on indeX High) Machine Instruction Code 86 (RX Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur L R7,=A(TABADRS) L R8,=A(20) L R9,=A(TABADRS+(HOWMANY-1)*LENGTH) NEXTITEM pointed item vs desired one if found, process it and go to TABLSEEN if not, point to next item BXH R7,R8,NOTFOUND B NEXTITEM TABLSEEN ... Example: Use in a search loop: R7 = begins with table address; incremented by element table length via R8 R8 = Table element length R9 = Last element address NOTFOUND : all table read, desired item not found. BXH 7,8,NOTFOUND R7 = R8 + R7; * If R7 > R9 all table already read; end search * If R7 <= R9 table not exhausted; continue search Mach.Inst.Summary

Machine Instructions - BXLE
BXLE (Branch on indeX Less or Equal) Machine Instruction Code 87 (RS Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur BXLE is similar to BXH instruction; the difference is that the branch is done if the result of the compare is Less or Equal. 1st and 2nd operands are registers. 3rd operand is an instruction address. (a) The contents of register 2nd operand is added to the contents of register 1st operand, the result set into register 1st operand. (b) Result is compared with: · Contents of register 2nd operand (if it is an odd register) or · Contents of register following register 2nd operand (if it is an even register) If the compare result is · Less or Equal to : it will be executed a branch to the instruction addressed by 3rd operand · Greater than : the branch will not be executed; processing resumes at the instruction following BXLE Mach.Inst.Summary

BXLE (Branch on indeX Less or Equal) Machine Instruction Code 87 (RS Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur Examples: BXLE 7,8,AGAIN R7 = R8 + R7; If R7 <= R9 Branch to AGAIN; * If R7 > R9 next instruction BXLE 7,9,AGAIN R7 = R9 + R7; If R7 <= R9 Branch to AGAIN; BXLE 7,9,8(4) R7 = R9 + R7; If R7 <= R9 Branch to instruction * Whose address is [ (contents R4) + x’008’ ] Mach.Inst.Summary

BXLE (Branch on indeX Less or Equal) Machine Instruction Code 87 (RS Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur L R7,=A(TABADRS) L R8,=A(20) L R9,=A(TABADRS+(HOWMANY-1)*LENGTH) NEXTITEM compare pointed item vs desired one if found, process it and go to TABLSEEN if not, point to next item BXLE R7,R8,NEXTITEM NOTFOUND ... TABLSEEN ... Example: Use in a search loop: R7 = begins with table address; incremented by element table length via R8 R8 = Table element length R9 = Last element address NOTFOUND : all table read, desired item not found BXLE 7,8,NOTFOUND R7 = R8 + R7; * If R7 <= R9 table not exhausted; continue search * If R7 > R9 all table already read; end search Mach.Inst.Summary

Machine Instructions - C
C (Compare) Machine Instruction Code 59 (RX Instruction) Condition code 00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after C Possible Interruptions 0005 C performs an algebraic compare between a binary number in a register (1st operand) and a binary number in a storage field (a full-word, the 2nd operand). Example: C 9,CPO C 8,=F'0' C 13,=A(TABLE+430) C 1,2(4) C 1,2(,4) C 1,2(7,4) Mach.Inst.Summary

Machine Instructions - CDS
CDS (Compare Double and Swap) Machine Instruction Code BB (RS Instruction) Condition code 00 1st operand equal to 2nd operand, 3rd operand moved to 2nd operand 01 1st operand not equal to 2nd operand, 2nd operand moved to 1st operand 10 Condition code is not set as 11 after CDS 11 Condition code is not set as 11 after CDS Possible Interruptions 0004,0005,0006 1st and 3rd operands are even registers. They are considered an indication of: 1st operand: double-word composed by R1 and R1+1 3rd operand: double-word composed by R3 and R3+1 2nd operand is an storage field (double-word). Contents of 1st operand (R1 and R1+1) is compared with the contents of the double-word 2nd operand. If they are equal, the contents of the 3rd operand (R3 and R3+1) is stored into the 2nd operand double-word. If they are not equal, the contents of the double-word 2nd operand is loaded into the 1st operand (R1 and R1+1). See the following examples: Mach.Inst.Summary

Machine Instructions - CDS
CDS (Compare Double and Swap) Machine Instruction Code BB (RS Instruction) Condition code 00 1st operand equal to 2nd operand, 3rd operand moved to 2nd operand 01 1st operand not equal to 2nd operand, 2nd operand moved to 1st operand 10 Condition code is not set as 11 after CDS 11 Condition code is not set as 11 after CDS Possible Interruptions 0004,0005,0006 CDS 4,8,DW Before: R4/R5 00.BF.C CC.A0.00 R8/R9 7D.48.C DW BF.C CC.A0.00 After: R4/R5 00.BF.C CC.A0.00 DW 7D.48.C CDS 4,8,DW Before: R4/R5 00.CC.DD.EE.FF.FF.FF.FF R8/R9 7D.48.C DW BF.C CC.A0.00 After: R4/R5 00.BF.C CC.A0.00 Mach.Inst.Summary

Machine Instructions - CH
CH (Compare Halfword) Machine Instruction Code 49 (RX Instruction) Condition code 00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CH Possible Interruptions 0005 CH performs an algebraic compare between a binary number in a register (1st operand) and a binary number in a storage field (a half-word, the 2nd operand). To do that, the 2nd operand is expanded (internally in the CPU) to 4 bytes, by repeating (to the left) 16 times the leftmost bit of the half-word. Example: CH 9,FLD st operand = R9; 2nd operand = FLD field CH 8,=H'0' st operand = R8; 2nd operand = half-word with zeros CH 13,=Y(TAB+430) 1st operand = R13; 2nd operand = half-word with address of TAB+430 CH 1,2(4) st operand = R1; 2nd operand = storage half-word which * address = value of index register R4 +0[base register omitted] + x’2’ CH 1,2(,4) st operand = R1; 2nd operand = storage half-word which * address = value of base register R4 +0[index register omitted] + x’2’ CH 1,2(7,4) st operand = R1; 2nd operand = storage half-word which * address = value of base register R4 +R7[index register] + x’2’ Mach.Inst.Summary

Machine Instructions - CL
CL (Compare Logical) Machine Instruction Code 55 (RX Instruction) Condition code 00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CL Possible Interruptions 0005 The CL instruction compares logically the contents of register 1st operand and the contents of a storage full-word (2nd operand). Logical compare is done left to right, one bit at a time; the first couple of unequal bits finish the operation.. Examples: CL ,CPO bits of register 9 compared with 32 bits of 4-byte CPO CL ,=F'0' bits of register 8 compared with 32-bit of 4-byte full-word with zero CL ,2(4) bits of register 1 compared with 4-byte storage field * ( 2nd operand address = contents of index reg. 4 + displacement X’2’ [base reg. omitted = zero = not considered] ) CL ,2(,4) bits of register 1 compared with 4-byte storage field * ( 2nd operand address = [ index reg. Omitted = zero = not considered] + displacement X’2’ + base reg.4 ) CL ,2(7,4) bits of register 1 compared with 4-byte field * ( 2nd operand address = contents of index reg. 7 + displacement X’2’ + contents of base reg. 4 ) Mach.Inst.Summary

Machine Instructions - CLC
CLC (Compare Logical Character) Machine Instruction Code D5 (SS Instruction – L) Condition code 00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLC Possible Interruptions 0005 This instruction compares logically (left to right, one bit at a time) two storage fields. The first not equal couple of bits finish the compare. Examples: CLC CPOA,CPOB Only one length used = length of CPOA (e.g. 100 bytes) CLC AE+78(2),=C'*1' 2-byte (AE+78 and AE+79) storage field is compared with * byte storage field referenced via literal (contents = X’5CF1’) CLC 4(2,7),2(9) bytes field (address = base register 7 + displacement X’4’) * is compared with storage field ( address = base register 9 + displacement X’2’ ) CLC ID,2(7) n-byte storage field ID is compared with n-byte storage field * (address = base register 7 + displacement X’2’ ) CLC (5,11),AE byte storage field (address = base register 11 + displacement X’C2’) * is compared with 5-byte storage field ( address = AE+3 ) Mach.Inst.Summary

Machine Instructions- CLCL
CLCL (Compare Logical Character Long) Machine Instruction Code 0F (RR Instruction) Condition code 00 1st operand = 2nd operand or both operands have zero length. 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLCL Possible Interruptions 0005,0006 This instruction compares two storage fields, in a similar way the CLC does. Both 1st and 2nd operands must be even registers. They indicate (each one of them) a pair of even-odd registers. We’ll call them: 1st pair = R1st and R1st+1; 2nd pair = R2nd and R2nd+1 The 1st operand (receiver field) address must be in the last 3 bytes (righmost) of R1st. The 2nd operand (sender field) address must be in the last 3 bytes (righmost) of R2nd. The 1st operand length must be in the last 3 bytes (rightmost) of R1st+1. The 2nd operand length must be in the last 3 bytes (rightmost) of R2nd+1. The leftmost byte of R2nd+1 must have the padding character. The leftmost byte of R1st, the leftmost byte of R2nd and the leftmost byte of R1st+1 are not considered in the operation. Example: CLCL ,8 R2=1st operand register (dubbed as R1st above); note that R1st+1 = register 3 R8=2nd operand register (dubbed as R2nd above); note that R2nd+1 = register 9 Mach.Inst.Summary

CLCL (Compare Logical Character Long) Machine Instruction Code 0F (RR Instruction) Condition code 00 1st operand = 2nd operand or both operands are zero length. 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLCL Possible Interruptions 0005,0006 Compare is done one bit at a time, from left to right. When not 2 bits unequal are found OR when length of greater operand is exhausted compare is finished. If the operands have no equal kengths, the smaller one is extended with the padding character (internally, without any change in the field). If compare is finished due to 2 bits unequal encountered: - From the value in the rightmost 3 bytes of R1st+1 and R2nd+1 is subtracted the amount of equal bytes; if the difference was found with the padding character the rightmost 3 bytes of R1st OR R2nd+1 are zeroed (the ones who have the smallest length). - To the value of the rightmost 3 bytes of R1st and R2nd is added the amount of equal bytes. If both operands are equal (including the padding character, if needed): - The 3 rightmost bytes of R1st+1 AND R2nd+1 are zeroed. - To the 3 rightmost bytes of R1st AND R2nd is added the amount of equal bytes. In both cases : the leftmost byte of R1 and the leftmost byte of R2 are zeroed, and the leftmost byte of R1st+1 and R2nd+1 remain unchanged. Mach.Inst.Summary

CLCL (Compare Logical Character Long) Machine Instruction Code 0F (RR Instruction) Condition code 00 1st operand = 2nd operand or both operands are zero length. 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLCL Possible Interruptions 0005,0006 Example: LA 2,BUFEROUT LA 3,12000 LA 8,BUFERIN LA 9,20000 ICM 9,B'1000',C' ' AGAIN CLCL 8,9 BE EQUALS DIFFS EQU * ... EQUALS EQU * LA loads into register 2 the BUFEROUT address CLCL executes the compare between a byte field (BUFEROUT) and a byte field (BUFERIN) LA loads into register 3 the BUFEROUT length LA loads into register 8 the BUFERIN address LA loads into register 9 the BUFERIN length ICM inserts padding character into leftmost byte of register 9 Mach.Inst.Summary

Machine Instructions - CLI
CLI (Compare Logical Immediate) Machine Instruction Code 95 (SI Instruction) Condition code 00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLI Possible Interruptions 0005 This instruction compares logically (left to right, one bit at a time) two storage fields. The first operand is a “normal” storage field with its address expressed with a base+displacement address. The second operand is also a storage field, but it is located IN the instruction: it is the instruction’s 2nd byte. It’s not necessary to specify its address, only its contents. Examples (note that b1d1d1d1 is the address of the 1st operand, in the base+displacement format): CLI AE+79,C'*' Machine code = 95.5C.b1d1.d1d1 Compare with asterisk CLI 2(5),X'00' Machine code = Compare with binary zeros CLI BYTE,B' ' Machine code = 95.F0.b1d1.d1d1 Compare with character zero CLI NOP+1, Machine code = 95.F0.b1d1.d1d1 Compare with character zero Mach.Inst.Summary

Machine Instructions - CLM
CLM (Compare Logical under Mask) Machine Instruction Code BD (RS Instruction) Condition code 00 Selected bytes are equal, or mask is zero 01 Selected field of the 1st operand is less than 2nd operand 10 Selected field of the 1st operand is greater than 2nd operand 11 Condition code is not set as 11 after CLM Possible Interruptions 0005 The contents of register 1st operand is logically compared (left to right, one bit at a time) with the contents of the 2nd operand, based on the control of the mask 3rd operand. The result is reflected in the setting of the condition code. It’s a RS instruction, with the following format: Byte 1= x’BD’ (operation code); Byte 2 = left half = R1 = register 1st operand; right half = M3 =(mask) Bytes 3 and 4 = 2nd operand address (base+displacement) The 4-bit mask, left to right, are related to the 4 bytes of the register 1st operand. The register bytes whose bits in the mask are ON are considered as a contiguous field, and compared with the storage field specified in the 2nd operand (the 2nd operand must have a length equal to the number of bits ON in the mask. The register bytes whose bits in the mask are OFF are not considered in the operation. Example: CLM ,B'1011',ARCOMP The “field” composed by 1st , 3rd and 4th bytes of register 5 is compared with the 3-byte field named ARCOMP. Mach.Inst.Summary

Machine Instructions - CLR
CLR (Compare Logical Register) Machine Instruction Code 15 (RR Instruction) Condition code 00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CLR Possible Interruptions No interruptions occur The CLR instruction compares logically the contents of the 2 registers (1st operand and 2nd operand). Logical compare is done left to right, one bit at a time; the first couple of unequal bits found finish the operation. Examples: CLR , bit “string” of register 4 compared with 32 bit “string” of register 5 CLR , bit “string” of register 8 compared with 32-bit “string” of rregister 13 Mach.Inst.Summary

Machine Instructions - CP
CP (Compare Packed) Machine Instruction Code F9 (SS Instruction – L1 e L2) Condition code 00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CP Possible Interruptions 0005,0007 The CP instruction compares the contents of 2 storage fields ( 1st and 2nd operands). Both must be in the decimal packed format, and remain unchanged. The lengths can be different: the values are compared, not the sizes. Examples: CP FLDA,FLDB If FLDA = X’ C’ and FLDB = X’10000C’ * Result is : 1st operand less than 2nd operand CP COUNTLIN,=P'1' If COUNTLIN = X’999999D’ compared with X’1C’ CP 0(5,9),=P'0' Compares contents of 5-byte field at address * (base register 9 + X’0’) with zero CP TOTAL,2(7,9) Compares contents of TOTAL with 7-byte field address (base register 9 + displacement X’2’) Mach.Inst.Summary

Machine Instructions - CR
CR (Compare Register) Machine Instruction Code 19 (RR Instruction) Condition code 00 1st operand = 2nd operand 01 1st operand < 2nd operand 10 1st operand > 2nd operand 11 Condition code is not set as 11 after CR Possible Interruptions No interruptions occur The CR instruction compares 2 binary numbers within 2 registers (1st and 2nd operands). Both remain unchanged. Examples: CR 4, bit binary number in register 4 compared with 31-bit binary number in register 5 CR 8, bit binary number in register 8 compared with 31-bit binary number in register 13 Mach.Inst.Summary

Machine Instructions - CS
CS (Compare and Swap) Machine Instruction Code BA (RS Instruction) Condition code 00 1st operand equal to 2nd operand, 3rd operand moved to 2nd operand 01 1st operand not equal to 2nd operand, 2nd operand moved to 1st operand 10 Condition code is not set as 10 after CS 11 Condition code is not set as 11 after CS Possible Interruptions 0004,0005,0006 1st and 3rd operands are registers. 2nd operand is a storage field (full-word). The contents of the register 1st operand is compared with the 2nd operand full-word. If they are equal, the contents of register 3rd operand is stored in the 2nd operand full-word. If they are unequal the contents of the 2nd operand full-word is loaded into register 1st operand. Examples: CS 5,8,FW Before: R5 00.BF.C R8 7D.48.C FW 00.BF.C4.20 After: R5 00.BF.C R8 7D.48.C FW 7D.48.C0.00 Before: R5 00.BF.C R8 7D.48.C FW 00.FF.EE.DD After: R5 00.FF.EE.DD R8 7D.48.C FW 00.FF.EE.DD Mach.Inst.Summary

Machine Instructions - CVB
CVB (ConVert to Binary) Machine Instruction Code 4F (RX Instruction) Condition code Remains unchanged Possible Interruptions 0005, 0007, 0009 The decimal packed number within the 8-byte field 2nd operand (normally a double-word – it remains unchanged), is converted to binary and loaded into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after CVB 8,DOUBLE BC.4F.CA D FF.FF.FC D * nd operand = DOUBLE CVB 8,0(5,9) FF.FF.FF.FF C C * nd operand address = index register 5 + base register 9 + X’0’ CVB 8,0(,9) FF.FF.FF.FF F FF F * nd operand address = index register 0 + base register 9 + X’0’ CVB 8,0(5) FF.FF.FF.FF C FF C * nd operand address = index register 5 + base register 0 + X’0’ Mach.Inst.Summary

Machine Instructions - CVD
CVD (ConVert to Decimal [packed]) Machine Instruction Code 4E (RX Instruction) Condition code Remains unchanged Possible Interruptions 0004,0005 The binary number within the register 1st operand is converted to decimal packed format and stored into the 8-byte field 2nd operand (normally a double-word). For positive numbers or zero, sign is ‘C’. For negative numbers sign is ‘D’. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before 2nd operand before register 1st operand after 2nd operand after CVD 8,DOUBLE C * nd operand = DOUBLE CVD 8,0(5,9) FF.FF.FF.FF FB.EC.44.CC.F0.F1 FF.FF.FF.FF D * nd operand address = index register 5 + base register 9 + X’0’ CVD 8,0(,9) BA.76.FE.54.DC.32.B9 C * nd operand address = index register 0 + base register 9 + X’0’ CVD 8,0(5) AA.AA C 00.00.AA.AA C * nd operand address = index register 5 + base register 0 + X’0’ Mach.Inst.Summary

Machine Instructions - D
D (Divide) Machine Instruction Code 5D (RX Instruction) Condition code Remains unchanged Possible Interruptions 0005,0006,0008 This instruction executes a division between 2 binary numbers. 1st operand indicate an even register; it is the the first of a couple registers (even+odd); together they must have a fixed-point number, whose format is: 1 sign bit + 63 binary-digit bits. The number within this couple of registers is the dividend. The divisor is the number within the 2nd operand storage field (full-word). After division: The remainder is stored into the even register from the even-odd couple. The quotient is stored in the odd register from the even-odd couple. Examples: L 6,=F'0' Dividend: Registers 6-7 together; L 7,=F'257' They have the number 257 D 6,=F'4' Divisor: (literal) with number 4; Quotient: Register 7 = 64; Remainder: Register 6 = 1 * L 10,=F'0' Dividend: Registers together; L 11,=F'17' They have the number 17 D 10,=F'3' Divisor: (literal) with number 3; Quotient: Register 11 = 5; Remainder: Register 10 = 2 Mach.Inst.Summary

Machine Instructions - DP
DP (Divide Packed) Machine Instruction Code FD (SS Instruction – L1 e L2) Condition code Remains unchanged Possible Interruptions 0004,0005,0006,0007,000B The DP instruction executes a division between 2 storage fields, both in packed decimal format. 1st operand is the dividend, and 2nd operand is the divisor. After division the quotient and the remainder are stored in the 1st operand storage field. 2nd operand remains unchanged. About the 2nd operand divisor (a) it remains unchanged after division (b) it cannot exceed 8 bytes (c) its length cannot be greater than or equal to the 1st operand length (d) if condition b or c occurs, program will interrupt with code 0006. The remainder is stored in the rightmost bytes of the 1st operand, with divisor’s length. Code 000B interruption occurs when: · Quotient’s length is greater than the length available to it in the 1st operand · Dividend has not at least 1 leftmost zero algarism. · Divisor is zero. See the following examples: Mach.Inst.Summary

Machine Instructions - DP
DP (Divide Packed) Machine Instruction Code FD (SS Instruction – L1 e L2) Condition code Remains unchanged Possible Interruptions 0004,0005,0006,0007,000B Suppose the operands with the length and values shown in the “before” line 1st operand before nd operand before 1st operand after nd operand after DP FLDA,FLDB C C C.00.0C C DP FLDA,FLDB C C C.00.1C C DP VALUE,=P'5' C 5C C.2C 5C

Machine Instructions - DR
DR (Divide Register) Machine Instruction Code 1D (RR Instruction) Condition code Remains unchanged Possible Interruptions 0006,0009 This instruction executes a division between 2 binary numbers, both in registers. 1st operand must indicate an even register; it is the the first of a couple registers (even+odd); together they must have a fixed-point number, whose format is: 1 sign bit + 63 binary-digit bits. The number within this couple of registers is the dividend. 2nd operand is the divisor. After division: The quotient is stored into the odd register The remainder is stored into the even register If the remainder and/or quotient are = 0, their sign will be 0; remainder’s sign is the same as dividend’s sign Examples: L 12,=F'2' Divisor: Register 12 with number 2 L 4,=F'0' Dividend: Registers 4-5 together; L 5,=F'257' They have the number 257 DR 4, Quotient: Register 5 = 128; Remainder: Register 4 = 1 * L 9,=F'12' Divisor: Register 9 with number 12 L 6,=F'0' Dividend: Registers 6-7 together; L 7,=F'148' They have the number 148 DR 6, Quotient: Register 7 = 12; Remainder: Register 6 = 4 Mach.Inst.Summary

Machine Instructions - ED
ED (Edit) Machine Instruction Code DE (SS Instruction – L) Condition code 00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after ED Possible Interruptions 0004,0005,0007 Syntax: [symbol] ED receiving_field,sending_field The 1st operand must have been prepared, prior to the edition, with the edition mask (e.g. move the edition mask to the 1st operand of edit instruction). The sending field (2nd operand) is converted from packed decimal to zoned decimal, and stored into the receiving field (1st operand), ovelaying therefore the mask in the 1st operand. Edition means the control and inclusion, if needed, of sign, visual characters (e.g. decimal point, 3-digit separators), and supression of non-significant zeros. One may edit many packed fields in just one execution of ED instruction. The (only) length specified is applied just to the 1st operand. The 2nd operand must be in the decimal packed format. If any byte of the 2nd operand have in his left half the configurations A, B, C, D , E or F, it will occur a program interruption (code 0007). Edit is done left to right. Mach.Inst.Summary

ED (Edit) Machine Instruction Code DE (SS Instruction – L) Condition code 00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after ED Possible Interruptions 0004,0005,0007 The bytes of mask may have: X'20‘ = digit selector; X’21’ = significance trigger, X’22’ ) = field separator , or any other contents (in this last case, it’s just a character to be inserted for visual pirposes) During edition, each character of the receiving field (mask – 1st operand) may have go into one of the 3 ways: · Remain unchanged · Substituted by an algarism of the sending field (converted to zoned format) · Substituted by the leftmost character of the 1st operand mask (FILLING character). To make the opetion from the 3 alternatives, CPU must analyse the mask, and consider the algarism being edited (is it zero or not?). The process is as follows: Mach.Inst.Summary

ED (Edit) Machine Instruction Code DE (SS Instruction – L) Condition code 00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after ED Possible Interruptions 0004,0005,0007 · The mask’s leftmost byte is analysed; if it is X’20’ or X’21’ it’s assigned as padding character and the edition starts with it. · Each one of the following bytes can have one of the following configurations: Digit selector (X'20') or S-Trigger (X'21') or Field separator (X'22') or Any other · In the edition, when is detected a X’20’ or X’21’ in the 1st operand, instruction v erifies: - The S-Trigger : significance indicator; it is a CPU flag; it can be ON or OFF. - The digit carresponding at the 2nd operand. As a result of the verification, the configuration in the mask in the 1st operand will be substituted by the corresponding digit in the 2nd operand converted to zoned (if digit in the 1st operand is X’20’ or X’21’), or by the padding character (if not X’20’ nor X’21’). Mach.Inst.Summary

ED (Edit) Machine Instruction Code DE (SS Instruction – L) Condition code 00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after ED Possible Interruptions 0004,0005,0007 About the S-trigger: It is turned OFF (a) at the beginning of the ED execution or (b) after a X’22’ is found in the mask or (c) when a X’A’ or X’C’ or ‘E’ or ‘F’ is found in the right phalf of any byte of the 2nd operand (the packed field being edited) It is turned ON (a) after a X’21’ is detected in the mask or (b) when a ‘X20’ is detected in the mask WITH its corresponding digit in the sending field being NOT zero. For these 2 cases the right half of the byte in the sending field doesn’t have X’A’ or X’C’ or ‘E’ or ‘F’. About Field separator (X'22') : it identifies fields in a multi-field edition. It is always substituted by the padding character Examples: Mach.Inst.Summary

ED (Edit) Machine Instruction Code DE (SS Instruction – L) Condition code 00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after ED Possible Interruptions 0004,0005,0007 Note that lowercase b means a (blank) space. MVC WPAREA+5(10),MASK ED WPAREA+5(10),TOTAL ... MASK DC X' B B2020' Before: TOTAL C WPAREA+5(10) B B.20.20 b b b b , 4 5 After: TOTAL C WPAREA+5(10) F1.F2.F3.6B.F4.F5 Other examples: ED (5,7),CPO ED ARIMP+17(8),ISDRT ED (12,9),2(10) Mach.Inst.Summary

Machine Instructions - EDMK
EDMK (Edit and Mark) Machine Instruction Code DF (SS Instruction – L) Condition code 00 Last field = 0 01 Last field < 0 10 Last field > 0 11 Condition code is not set as 11 after EDMK Possible Interruptions 0004,0005,0007 This instruction is analog to the ED instruction. It loads into register 1 (bits 8-31; bits 0-7 remain unchanged) the address of the byte in the 1st operand who received the 1st non-zero digit. Note that the address is not loaded when significance is forced (using X'21'). Example: EDMK ARIMP+5(10),TOTAL Mach.Inst.Summary

Machine Instructions - EX
EX (Execute) Machine Instruction Code 44 (RX Instruction) Condition code The setting (or not) depends on the executed instruction Possible Interruptions 0003,0005,0006 The 2nd operand specifies an instruction address. The instruction it refers to is temporarily (internally in theCPU) modified according to the value of the register specified as 1st operand. With this tomporary change, it is executed. The temporary changing is made applying a boolean OR (mask = rightmost byte of 1st operand register; object = 2nd byte of instruction addressed by 2nd operand). Note that both EX operands remain unchanged. If 1st operand is register 0, OR won’t be done, the instruction will be executed as it is in storage, with no change in the 2nd byte. Example: L ,=F'22' EX ,MVC . MVC MVC ,(0,12),=CL256' ' Move will be executed with length 23 Mach.Inst.Summary

Machine Instructions - IC
IC (Insert Character) Machine Instruction Code 43 (RX Instruction) Condition code Remains unchanged Possible Interruptions 0005 The contents of the byte specified in the 2nd operand is inserted into the rightmost byte of the register 1st operand; leftmost 3 bytes remain unchanged. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register1st operand after nd operand after IC 4,BYTE C B B B IC 8,=C'K' C D2 D D2 IC 11,=HL1'125' C 7D C.2C 7D Mach.Inst.Summary

Machine Instructions - ICM
ICM (Insert Character under Mask) Machine Instruction Code BF (RS Instruction) Condition code 00 All inserted bits are 0, or mask is zero. 01 1st bit of inserted field is 1. 10 1st bit of inserted field is 0, and not all inserted bits are zero. 11 Condition code is not set as 11 after ICM. Possible Interruptions 0005 The format of this instruction is: 1st byte: X’BF’ (operation code); 2nd byte, left half : 1st operand register ; 2nd byte, right half : 3rd operand (mask); 3rd and 4th bytes : 2nd operand address, base+displacement format. The 4 bits in the mask correspond to the 4 bytes of the 1st operand register. The storage field specified in the 2nd operand must have as many bytes as the ON bits in the mask. The storage bytes are inserted left to right into the bytes of 1st operand byteswhose bits in the mask are ON. The remaining bytes of the register remain unchanged. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register1st operand after nd operand after ICM 5,B'1010',TWOBYTES A.BC 9A.00.BC A.BC 1st byte from TWOBYTES is inserted into 1st byte of register 5 and 2nd byte from TWOBYTES is inserted into the 3rd byte of register 5. Mach.Inst.Summary

Machine Instructions - IPM
IPM (Insert Program Mask) Machine Instruction Code B222 (RR InstructionE) Condition code Remains unchanged Possible Interruptions No interruptions occur Bits (3rd byte) and (4th byte right) of the instruction are ignored. Condition code and program mask (from PSW) are copied into bits 2-3 (condition code) and bits 4-7 (program mask) into the corresponding bits of 1st operand register. Bits 0-1 of the register are zeroed, and bits 8-31 remain unchanged. Example: Suppose PSW with condition code ’01’ and program mask ‘1100’ register 8 before register 8 after IPM C A 1C A Mach.Inst.Summary

Machine Instructions - L
L (Load) Machine Instruction Code 58 (RX Instruction) Condition code Remains unchanged Possible Interruptions 0005 The contents of the field specified as 2nd operand (remains unchanged and) is loaded into the register 1st operand. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register1st operand after nd operand after L 7,FULL FE.DC.BA L 14,SALVA FF.FF.FF.FD FF.FF.FF.FD FF.FF.FF.FD L 11,=F'125' D D D Other examples: L ,0(10) L ,0(,11) L ,0(10,11) L ,=F'200' Mach.Inst.Summary

Machine Instructions - LA
LA (Load Address) Machine Instruction Code 41 (RX Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur The instruction computes the 2nd operand address and loads it into the 3 rightmost bytes of register 1st operand. The leftmost byte of register is set ro zero. Example: Suppose the registers with the values shown bellow (for symbol references register 3 is supposed to be the base register for the referenced fileds, and the displacements are just for example purposes; ) register 1st operand before machine instruction register 3 before register 9 before register1st operand after register 3 after register 9 after LA 5,TABLE A.C B not used 00.0B B not used LA 5,FLD F A not used 00.A0.0F A not used LA 5,FLD+17(9) F A 00.A0.0F A LA 5,2(9,3) A 00.A A LA 5, C8 not used not used C not used not used Mach.Inst.Summary

Machine Instructions - LA
LA (Load Address) Machine Instruction Code 41 (RX Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur The instruction computes the 2nd operand address and loads it into the 3 rightmost bytes of register 1st operand. The leftmost byte of register is set ro zero. Example: Suppose the registers with the values shown bellow register 1st operand before machine instruction register 3 before register 9 before register1st operand after register 3 after register 9 after LA 5, F.FF not used not used F.FF not used not used LA 5,4095(3) F.FF 00.0A not used 00.0A.8F.FF A not used LA 5,4095(3,9) F.FF 00.0A 00.0A A Mach.Inst.Summary

Machine Instructions - LCR
LCR (Load Complement Register) Machine Instruction Code 13 (RR Instruction) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions 0008 The binary number in the register 2nd operand is complemented and stored into the register 1st operand. If the number is positive, it becomes negative; if it is negative it becomes positive. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LCR 4, FF.FF.FF.FC FF.FF.FF.FC LCR 4, FF.FF.FF.FE Mach.Inst.Summary

Machine Instructions - LH
LH (Load Halfword) Machine Instruction Code 48 (RX Instruction) Condition code Remains unchanged Possible Interruptions 0005 The 2-byte field specified as 2nd operand (remains unchanged and) is loaded into the rightmost 2 bytes of the register 1st operand. The leftmost bit of the storage field is used to fill the leftmost 2 bytes of the register 1st operand: it is expanded / copied to all bits of the first 2 bytes of the register. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register1st operand after nd operand after LH 5,FLD A.B4 FF.FF.8A.B A.B4 LH 8,HWORD FF.FF.FF.FF A.B4 A.B A.B4 More examples: LH ,HALF LH ,0(10) LH ,0(,11) LH ,0(10,11) LH ,=H'200' Mach.Inst.Summary

Machine Instructions - LM
LM (Load Multiple) Machine Instruction Code 98 (RX Instruction) Condition code Remains unchanged Possible Interruptions 0005 This instruction works with 3 operands: 1st and 3rd are registers, and 2nd is a storage field. It loads the contents of the storage field 2nd perand into the registers specified as a range by the 1st and 3rd operands. The length of the field depends on how many registers must be loaded. To load 2 registers, the area must have 8 bytes; to load 3 registers, the area must have 12 bytes, and so on. Example: LM ,1,SAVEAREA Reg Reg Reg Reg.1 < >< >< >< > | SAVEAREA | SAVEAREA = 16 bytes (bytes 0-3 = contents loaded into register 14; bytes 4-7 = contents loaded into register 15; bytes 8-11 = contents loaded into register 0; bytes = contents loaded into register 1) Another example: LM ,7,2(10) Mach.Inst.Summary

Machine Instructions - LNR
LNR (Load Negative Register) Machine Instruction Code 11 (RR Instruction) Condition code 00 Result = 0 01 Result < 0 10 Condition code is not set as 10 after LNR 11 Condition code is not set as 11 after LNR Possible Interruptions No interruptions occur The binary number of the 2nd operand is converted to negative and loaded into the register 1st operand. Negative numbers and zero remain unchanged. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LNR 4, FF.FF.FF.FC FF.FF.FF.FE FF.FF.FF.FC LNR 4, FF.FF.FF.FE LNR 4, Mach.Inst.Summary

Machine Instructions - LPR
LPR (Load Positive Register) Machine Instruction Code 10 (RR Instruction) Condition code 00 Result = 0 01 Condition code is not set as 1 after LPR. 10 Result > 0 11 Overflow Possible Interruptions 0008 The binary number of the 2nd operand converted to positive and loaded into the register 1st operand. Positive numbers and zero remain unchanged. The overflow occurs when the maximum negative value is converted to positive; in this case, the number remains unchanged. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LPR 4, FF.FF.FF.FC FF.FF.FF.FC LPR 4, LPR 4, FF Mach.Inst.Summary

Machine Instructions - LR
LR (Load Register) Machine Instruction Code 18 (RR Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur The contents of the register 2nd operand is loaded into the register 1st operand. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LR 4, FF.FF.FF.FC FF.FF.FF.FC FF.FF.FF.FC LR 4, LR 4, Mach.Inst.Summary

Machine Instructions - LTR
LTR (Load and Test Register) Machine Instruction Code 12 (RR Instruction) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Condition code is not set as 11 after LTR Possible Interruptions No interruptions occur The contents of register 2nd operand is loaded into the register 1st operand; the condition code is set according to the number loaded. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before register 2nd operand before register1st operand after register 2nd operand after LTR 4, FF.FF.FF.FC FF.FF.FF.FC FF.FF.FF.FC LTR 4, LTR 4, Mach.Inst.Summary

Machine Instructions - M
M (Multiply) Machine Instruction Code 5C (RX Instruction) Condition code Remains unchanged Possible Interruptions 0005,0006 This instruction multiplies two binary numbers. Register 1st operand must be an even register. The odd register following it must contain the multiplicand. The 2nd operand storage field must contain the multiplier. The result is a 64-bit fixed-point binary number stored into the pair of even-odd registers (specified by the 1st operand). Examples: Register 6 before Register 7 before 2nd operand before Register 6 after Register 7 after nd operand after M 6,FLDA [ Multiplicand: Register 7; Multiplier: FLDA; Result: Registers 6 and 7 together ] A M 6,=F'256' Multiplicand: Register 7; Multiplier: 256; Result: Registers 6 and 7 together FF FC FF M 6,4(2,8) Multiplicand: Register 7; Multiplier address: Index reg 2 + Base reg 8 + X’4’; Result: Registers 6 and 7 together A A Mach.Inst.Summary

Machine Instructions - M
M (Multiply) Machine Instruction Code 5C (RX Instruction) Condition code Remains unchanged Possible Interruptions 0005,0006 More examples: Register 6 before Register 7 before 2nd operand before Register 6 after Register 7 after nd operand after M 6,4(2) Multiplicand: Register 7; Multiplier address: Reg index 2 [ + Reg base 0 ] + X’4’; Result: Registers 6 and 7 together C M 6,FLD+4(1) Multiplicand: Reg 7; Multiplier address: Reg index 1 + Base register of FLD+4 + Displacement of FLD+4 + X’4’; Result: Registers 6 and 7 together AA.AA B 6C DE Mach.Inst.Summary

Machine Instructions - MC
MC (Monitor Call) Machine Instruction Code AF (SI Instruction) Condition code Remains unchanged Possible Interruptions 0006,0040 This instruction causes a program interruption if the bit that controls this event is ON in the control register. The control register mask bits are the bits 16-31, end they correspond to the classes 0-15 respectively. The leftmost 4 bits of 2nd operand (immediate) must be zero. The rightmost 4 bits of 2nd operand specify abinary number indicating the desired interruption class. If the corresponding bit in the control register 8is ON, interruption will occur. The 2nd operand address is not a storage address; it is a code to be stored at the storage address X'000156'. If the mask referred to the desired interruption is OFF in the control register 8, instruction processes as a NOP (no operation). Example: MC MONITCOD,7 Mach.Inst.Summary

Machine Instructions - MH
MH (Multiply Halfword) Machine Instruction Code 4C (RX Instruction) Condition code Remains unchanged Possible Interruptions 0005 This instruction multiplies two binary numbers. Register 1st operand must have the multiplicand. The 2nd operand 2-byte storage field must contain the multiplier. The result is a 32-bit fixed-point binary number stored into the register 1st operand. Example: Note that if an overflow occurs (this event is NOT indicated in the condition code) the result sign may not be correct. If result = zero, sign is same as positive number. Examples: Register 1st operand before 2nd operand before Register 1st operand after nd operand after MH 5,=H'4' [ Multiplicand: Register 5; Multiplier: literal 4; Result: Register 5 ] A MH 5,=F'2' Multiplicand: Register 5; Multiplier: 0 [ left half of the fullword is taken as the halfword 2nd operand] ; Result: Register 5 [TAKE CARE! right half with not taken! ] Mach.Inst.Summary

Machine Instructions - MP
MP (Multiply Packed) Machine Instruction Code FC (SS Instruction – L1 e L2) Condition code Remains unchanged Possible Interruptions 0001,0004,0005,0006,0007 This instruction multiplies two decimal packed numbers, both in storage fields. The result is stored in the 1st operand. 2nd operand can be up to 8 bytes. 2nd operand length must be less than the length of the 1st operand. If 2nd operand length is greater than or equal to the length of the 1st operand, an interruption will occur (code 0006). 1st operand must have as many zero leftmost digits as many digits the 2nd operand has. If it doesn’t happen, interruption 0007 will occur. Example: MP FLDA,FLDB 1st operand before nd operand before 1st operand after nd operand after C C C C C C C C (Error! FLDA must have at least 3 leftmost digits with zero) Mach.Inst.Summary

Machine Instructions - MR
MR (Multiply Register) Machine Instruction Code 1C (RR Instruction) Condition code Remains unchanged Possible Interruptions 0006 This instruction multiplies two binary numbers, both in registers. Register 1st operand must be an even register (its contents is not considered in the operation, unless it is [also] the multiplier). The odd register following it must contain the multiplicand. The 2nd operand register must contain the multiplier. The result is a 64-bit fixed-point binary number stored into the pair of even-odd registers (specified by the 1st operand). Example: Register 6 before Register 7 before Register 9 before Register 6 after Register 7 after Register 9 after MR 6,9 [ Multiplicand: Register 7; Multiplier: register 9; Result: Registers 6 and 7 together ] A AA.BB.CC FF.FF.FF 00.99.AA.BB FF.FF.FF Mach.Inst.Summary

Machine Instructions - MVC
MVC (MoVe Character) Machine Instruction Code D2 (SS Instruction - L) Condition code Remains unchanged Possible Interruptions 0004,0005 This instruction moves (copies) the contents of stotage field to another storage field. The move is done left to right, each byte at a time. Example: MVC FLDA,FLDB before after FLDB C1.C2.C3 C1.C2.C3 FLDA C4.C5.C6 C1.C2.C3 The sending field is the 2nd operand and remains unchanged (unless part of it is at the same time the receiving field = overlapping). The receiving field is the 1st operand. The quantity of bytes moved is determined by the 1st operand length, and both operands are treated with this same length. Examples: Suppose the operands with the length and values shown in the “before” line 1st operand before nd operand before 1st operand after nd operand after MVC WA+5(3),WR E5.C1.D3 E5.C1.D E5.C1.D3 MVC WOUT,WIN C C C MVC NICKNAM,=C'SMAIL' C3.D9.E E2.D4.C1.C9.D3 E2.D4.C1.C9.D3 E2.D4.C1.C9.D3 Mach.Inst.Summary

MVC (MoVe Character) Machine Instruction Code D2 (SS Instruction - L) Condition code Remains unchanged Possible Interruptions 0004,0005 More examples: Move spaces using an auxiliary 5-byte field (a 5-byte literal) : Suppose the operands with the length and values shown in the “before” line 1st operand before nd operand before 1st operand after nd operand after MVC WA(5),=CL5' ' 5C.5C.5C.5C.5C Alternatively, one may propagate spaces using na auxiliary 1-byte area (the literal) ! - The first MVC moves space to the leftmost byte of WA. - The second one moves 4 bytes; remember that MVC operates one byte at a time. - Follow the 4-byte move, one at a time: The 1st byte is moved to the 2nd; The 2nd to the 3rd; The 3rd byte to the 4th; The 4th byte to the 5th. Initial MVC for the leftmost byte: MVC WA(1),=C' ' C.??.??.??.?? before 40.??.??.??.?? after Mach.Inst.Summary

MVC (MoVe Character) Machine Instruction Code D2 (SS Instruction - L) Condition code Remains unchanged Possible Interruptions 0004,0005 Propagation from 1st to 2nd, from 2nd to 3rd, from 3rd to 4th and from 4th to 5th MVC WA+1(4),WA Follow MVC one byte at a time : 1st byte move: 40.??.??.??.?? 40.??.??.??.?? 40.40.??.??.?? ??.??.?? 2nd byte move : ??.??.?? ??.??.?? ??.?? ??.?? 3rd byte move : ??.?? ??.?? ?? ?? 4th byte move : ?? ?? Or, better yet: 1st move: 40.??.??.??.?? Before 40.40.??.??.?? After 2nd move: ??.??.?? Before ??.?? After 3rd move: ??.?? Before ?? After 4th move: ?? Before After Mach.Inst.Summary

Machine Instructions - MVCIN
MVCIN (MoVe Character Inverted) Machine Instruction Code E8 (SS Instruction – L) Condition code Remains unchanged Possible Interruptions 0001,0004,0005 This instruction moves (copies) the contents of the 2nd operand to the 1st operand (both are storage fields) in an inverted sequence. Note that the 1st operand address is its leftmost byte, and the 2nd operand address is its rightmost byte. Move is done each byte at a time. From the sending field’s view its from right to left. From the receiving field’s view its from left to right. If occurs any overlay (superposition), results are unpredictable. Example: Suppose the operands with the length and values shown in the “before” line 1st operand before nd operand before 1st operand after nd operand after MVCIN A(3),B C4.C5.C C1.C2.C3 C3.C2.C C1.C2.C3 MVCIN A(5),BETA C4.C5.C6.C7.C8 C1.C2.C3.C4.C5 C5.C4.C3.C2.C1 C1.C2.C3.C4.C5 Mach.Inst.Summary

Machine Instructions - MVCL
MVCL (MoVe Character Long) Machine Instruction Code 0E (RR Instruction) Condition code 00 Length of 1st operand is equal to length of 2nd operand 01 Length of 1st operand is less than length of 2nd operand 10 Length of 1st operand is greater than length of 2nd operand 11 Move not executed Possible Interruptions 0004,0005,0006 Both 1st and 2nd operands must be even registers. They indicate a couple of (even-odd) registers, herein dubbed R1st, R1st+1, R2nd and R2nd+1 This instruction move a storage field (sending field) to another storage field (receiving field), each byte at a time, left to right. Receiving field address must be in the 3 rightmost bytes of R1st. Sending field address must be in the 3 rightmost bytes of R2nd. Receiving field length must be in the 3 rightmost bytes of R1st+1. Sending field length must be in the 3 rightmost bytes of R2nd+1. The leftmost byte of R2nd+1 must contain the padding character. The leftmost byte of R1st is ignored. Same happens with leftmost byte of R1st+1 and leftmost byte of R2nd. Example: MVCL ,8 See details on following slide. Mach.Inst.Summary

MVCL (MoVe Character Long) Machine Instruction Code 0E (RR Instruction) Condition code 00 Length of 1st operand is equal to length of 2nd operand 01 Length of 1st operand is less than length of 2nd operand 10 Length of 1st operand is greater than length of 2nd operand 11 Move not executed Possible Interruptions 0004,0005,0006 L ,=A(RECEIVE) L ,=A(L’RECEIVE) L ,=A(SENDING) L ,=A(L’SENDING) ICM 9,B'1000',=C'*' MVCL 2,8 If sending field wraps from byte to byte 0 (or not), move is executed this way: · The move is executed while the receiving field’s leftmost byte is the same or it’s at the left of the leftmost byte of the sending field OR the move is executed while the receiving field’s leftmost byte is at the right of the rightmost byte of the sending field. · The move is executed while the receiving field’s leftmost byte is the same or is at the left of the leftmost byte of the sending field AND the receiving field’s leftmost byte is at the right of the rightmost byte of the sending field. The (address of the) rightmost byte of the sending field is computed using the length of the receiving or sending field (the smaller). Mach.Inst.Summary

MVCL (MoVe Character Long) Machine Instruction Code 0E (RR Instruction) Condition code 00 Length of 1st operand is equal to length of 2nd operand 01 Length of 1st operand is less than length of 2nd operand 10 Length of 1st operand is greater than length of 2nd operand 11 Move not executed Possible Interruptions 0004,0005,0006 After move: - The 3 rightmost bytes of R1st+1 (previously with the receiving field length) are set to zero (in fact, at each byte moved, it’s decremented by 1; , it is the amount of remaining bytes to move; at the end of operation remaining bytes to move = zero). To the 3 rightmost bytes of R1st (previously with the receiving field address) is added the length originally specified in R1st+1 (in fact, at each byte moved, it’s incremented by 1 = next receiving byte address). From the 3 rightmost bytes of R2nd+1 (originally with the sending field length) is subtracted the amount of moved bytes (in fact at each byte move it is decremented by 1, it is the amount of remaining bytes to move; at the end remaining bytes to move = zero) - To the 3 rightmost bytes of R2nd (previously with sending field address) it is added the number of bytes moved from sending to receiving field (in fact, at each byte moved, it’s incremented by 1 = next sending byte address) Leftmost R1st byte and leftmost R2nd byte are set to zero, even if move is not done. - Leftmost R1st+1 byte and leftmost R2nd+1 byte remain unchanged. Mach.Inst.Summary

Machine Instructions - MVI
MVI (MoVe Immediate) Machine Instruction Code 92 (SI Instruction) Condition code Remains unchanged Possible Interruptions 0004,0005 This instruction moves (copies) a constant 1-byte storage field (2nd operand – immediate operand) to another storage 1-byte field. 2nd operand (mmediate operand) is the sending field and 1st operand is the receiving field. Examples: MVI FLDA,C'*' or MVI FLDA,X'5C' or MVI FLDA,B' ' or MVI FLDA,92 FLDA before Immediate operand before FLDA after Immediate operand after C 5C C Other examples: MVI WAREA+72,C'/' MVI (4),X'80' Mach.Inst.Summary

Machine Instructions - MVN
MVN (MoVe Numerics) Machine Instruction Code D1 (SS Instruction - L) Condition code Remains unchanged Possible Interruptions 0004,0005 This instruction is similar to MVC, but it moves onle the right half of the bytes. Example: Suppose the operands with the length and values shown in the “before” line 1st operand before nd operand before 1st operand after nd operand after MVN FLDA,FLB A.BC 18.3A.5C A.BC MVN TOT+4(1),=X'0C' F 0C C 0C Mach.Inst.Summary

Machine Instructions - MVO
MVO (MoVe with Offset) Machine Instruction Code F1 (SS Instruction – L1 e L2) Condition code Remains unchanged Possible Interruptions 0004,0005 The MVO instruction moves the contents of the 2nd operand storage field to the 1st operand storage field, from righ to left, with displacement of half byte: the right half of the receveing field rightmost byte remains unchanged. The right half of the rightmost byte of sending field is sent to the left half of the rightmost byte of receiving field. And so on. If 1st operand isn’t large enough to receive all digits sent from the 1st operand, the leftmost half-bytes are truncated. If 1st operand is larger than enough to receive all digits sent from the 1st operand, the leftmost half-bytes are filled with X’0’. Examples: MVO RECFLD,SENFLD SENFLD Before SENFLD After RECFLD Before C RECFLD After C Mach.Inst.Summary

Machine Instructions - MVO
MVO (MoVe with Offset) Machine Instruction Code F1 (SS Instruction – L1 e L2) Condition code Remains unchanged Possible Interruptions 0004,0005 MVO CPOA,CPOB Before After 1º Case CPOB CPOA A A 2º Case CPOB AB AB.72 CPOA A.5C.B9.FC A.B7.2C Other examples: MVO ARCALC(5),ARCALC(4) MVO (4,7),ARCALC MVO AREA,2(5,8) MVO (7,13),19(5,15) Mach.Inst.Summary

Machine Instructions - MVZ
MVZ (MoVe Zones) Machine Instruction Code D3 (SS Instruction – L) Condition code Remains unchanged Possible Interruptions 0004,0005 The MVZ instruction is similar to the MVC, but it moves onle the left half of the bytes. Examples: Suppose the operands with the length and values shown in the “before” line 1st operand before nd operand before 1st operand after nd operand after MVZ FLDA,FLB A.BC 72.94.B A.BC MVZ TOT,=4C'0' C5 F0.F0.F0.F0.F0 F1.F2.F3.F4.F5 F0.F0.F0.F0.F0 Mach.Inst.Summary

Machine Instructions - N
N ([boolean] aNd) Machine Instruction Code 54 (RX Instruction) Condition code 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after N 11 Condition code is not set as 11 after N Possible Interruptions 0005 This instruction executes a boolean AND between a register (1st operand) and a 4-byte storage field (2nd operand). Mask bit =0 then result bit = 0; mask bit = 1 then reault bit = remain unchanged Example: N ,FIELDX Before After Register 13 B4.EF.2F.A A8 FIELDX FF FF Other examples: N ,=F'15' N ,0(4) N ,0(,4) N ,0(8,4) Mach.Inst.Summary

Machine Instructions - NC
NC ([boolean] aNd Character) Machine Instruction Code D4 (SS Instruction – L) Condition code 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after NC 11 Condition code is not set as 11 after NC Possible Interruptions 0004, 0005 This instruction executes a boolean AND between 2 storage fields (1st and 2nd operands). Mask bit =0 then result bit = 0; mask bit = 1 then reault bit = remain unchanged Example: NC FLDA,FLDB Before After FLDA EF.2F.A A8 FLDB FF FF Mach.Inst.Summary

Machine Instructions - NI
NI ([boolean] aNd [with] Immediate [operand]) Machine Instruction Code 94 (SI Instruction) Condition code 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after NI 11 Condition code is not set as 11 after NI Possible Interruptions 0004, 0005 This instruction executes a boolean AND between 2 storage fields (1 byte each; 1st operand = field specified using its address; 2nd operand = immediate field, it’s the 2nd byte of the instruction). Mask bit =0 then result bit = 0; mask bit = 1 then reault bit = remain unchanged Example: NI BYTE,X'0F' Before After BYTE B Immediate Op. 0F F Mach.Inst.Summary

Machine Instructions - NR
NR ([boolean] aNd Register) Machine Instruction Code 14 (RR Instruction) Condition code 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after NR 11 Condition code is not set as 11 after NR Possible Interruptions No interruptions occur This instruction executes a boolean AND between 2 registers. Mask bit =0 then result bit = 0; mask bit = 1 then reault bit = remain unchanged Example: NR ,8 Before After Register B4.EF.2F.A A8 Register FF FF Mach.Inst.Summary

Machine Instructions - O
O ([boolean] Or) Machine Instruction Code 56 (RX Instruction) Condition code 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after O 11 Condition code is not set as 11 after O Possible Interruptions 0005 This instruction executes a boolean OR between a register (1st operand) and a 4-byte storage field (2nd operand). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = 1 Example: O ,FIELDF Before After Register 13 B4.EF.2F.A8 B4.EF.2F.FF FIELDF FF FF Mach.Inst.Summary

Machine Instructions - OC
OC ([boolean] Or Character) Machine Instruction Code D6 (SS Instruction – L) Condition code 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after OC 11 Condition code is not set as 11 after OC Possible Interruptions 0004, 0005 This instruction executes a boolean OR between 2 storage fields (1st and 2nd operands). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = 1 Example: OC FLDA,FLDB Before After FLDA EF.2F.A8 EF.2F.FF FLDB FF FF Mach.Inst.Summary

Machine Instructions - OI
OI ([boolean] Or [with] Immediate [operand]) Machine Instruction Code 96 (SI Instruction) Condition code 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after OI 11 Condition code is not set as 11 after OI Possible Interruptions 0004, 0005 This instruction executes a boolean OR between 2 storage fields (1 byte each; 1st operand = field specified using its address; 2nd operand = immediate field, it’s the 2nd byte of the instruction). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = 1 Example: OI BYTE,X'0F' Before After BYTE B BF Immediate Operand 0F F Mach.Inst.Summary

Machine Instructions - OR
OR ([boolean] Or Register) Machine Instruction Code 16 (RR Instruction) Condition code 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after OR 11 Condition code is not set as 11 after OR Possible Interruptions No interruptions occur This instruction executes a boolean OR between 2 registers. Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = 1 Example: OR ,8 Before After Reg. 5 B4.EF.2F.A8 B4.EF.2F.FF Reg FF FF Mach.Inst.Summary

Machine Instructions - PACK
Machine Instruction Code F2 (SS Instruction – L1 e L2) Condition code Remains unchanged Possible Interruptions 0004,0005 The PACK instruction moves a storage zoned field to a storage packed field. The intended function is to convert a numeric field from zoned format to packed format. NO validation is done in the sending field; if its contents is not a valid decimal zoned number, the operation flows normally. 1st operand is the receiving field and 2nd operand is the sending field. The operation is done from right to left. The two halves of the rightmost byte of the sending field are inverted and moved to the rightmost byte of the receiving field. After that, each right half byte of the sending field is sent to a half of the receiving field. 2nd operand remains unchanged. If the receiving field is smaller than needed to fit all digits from the sending field, the leftmost digits are truncated. If the receiving field is greater than needed to fit all digits from sending field, the remaining left digits are filled with X’0’. Example: PACK FLDA,FLDB Before After FLDB F1.F2.F3.F4 F1.F2.F3.F4 FLDA B7.2A F Mach.Inst.Summary

Machine Instructions - PACK
Machine Instruction Code F2 (SS Instruction – L1 e L2) Condition code Remains unchanged Possible Interruptions 0004,0005 PACK FLDA,FLDB 2ºcase FLDB F1.F2.F3.F4 F1.F2.F3.F4 FLDA C9.4A F 3ºcase FLDB 9A.48.F9.DB 9A.48.F9.DB FLDA B7.DF A.89.BD Note the 3rd case. The sending field is not validated about being zoned. The receiving field may not become a valid decimal packed field. More examples: PACK VALUE,READAREA+5(9) PACK HOWMUCH+2(7),2(8,5) PACK (10,2),AREA PACK (5,7),2(3,8) PACK DOUBLE,DOUBLE PACK BYTE,BYTE Mach.Inst.Summary

Machine Instructions - S
S (Subtract) Machine Instruction Code 5B (RX Instruction) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions 0005,0008 Instruction S subtracts algebraically the binary number in the 4-byte storage field 2nd operand from the bynary number of the register 1st operand. Result is stored into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register 1st operand after nd operand after S 5,=F'259' BF.D 00.00.BE.CF S 7,FULL D FF.FF.FF.0A S 7,4(2,8) FF.FF.FE 07.FF.FF.FD S 7,4(2) FF.FF.FF 07.FF.FF.FD S 7,4(,8) FF.FF.FF.FF FF.FF.FF.FF Mach.Inst.Summary

Machine Instructions - SH
SH (Subtract Halfword) Machine Instruction Code 4B (RX Instruction) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions 0005,0008 Instruction SH subtracts algebraically the binary number in the 2-byte storage field 2nd operand from the bynary number of the register 1st operand. Result is stored into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register 1st operand after nd operand after SH 5,=H'259' B.C A.C SH 5,HALF D D FF.FF.FF D SH 5,4(2,8) (decimal ) (decimal –30584) (decimal ) SH 5,4(2) (decimal ) (decimal ) (decimal ) Mach.Inst.Summary

Machine Instructions - SL
SL (Subtract Logical) Machine Instruction Code 5F (RX Instruction) Condition code Condition code is not set as 00 after SL 01 Result <> 0, sign not lost 10 Result = 0, sign lost 11 Result <> 0, sign lost Possible Interruptions 0005 Instruction S subtracts logically the binary number in the 4-byte storage field 2nd operand from the binary number of the register 1st operand. Result is stored into 1st operand register. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register 1st operand after nd operand after SL 5,=F'259' BF.D 00.00.BE.CF SL 7,FULL D A SL 7,4(2,8) FF.FF.FE 07.FF.FF.FD SL 7,4(2) FF.FF.FF 07.FF.FF.FD Mach.Inst.Summary

Machine Instructions - SLA
SLA (Shift Left Algebraic) Machine Instruction Code 8B (RS Instruction) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions No interruptions occur This instruction shifts algebraically, to the left, the bits of the register 1st operand. The sign bit remains unchanged, and the other 31 bits are shifted. The “new” bits to the right are set to zero. It’s an RS instruction, and its bits are ignored. The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 15. Example: SLA ,3 Register 5 before Shift FF.80.9A.00 Register 5 after Shift FC.04.D0.00 Mach.Inst.Summary

Machine Instructions SLDA
SLDA (Shift Left Double Algebraic) Machine Instruction Code 8F (RS Instruction) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions 0004, 0008 The register specified as 1st operand indicates the a pair of registers (R1st and R1st+1), taken as a number with 64-bit (1 bit = sign; 63 bits = number). This instruction shifts algebraically, to the left, the bits of the number inside the 2 registers (both treated as only onr number). The sign bit remains unchanged, and the other 63 bits are shifted. The “new” bits to the right are set to zero. It’s an RS instruction, and its bits are ignored. The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 63. Example: SLDA ,3 Registers 8 and 9 before Shift FF.80.9A.00 Registers 8 and 9 after Shift FC.04.D0.00 Mach.Inst.Summary

Machine Instructions - SLDL
SLDL (Shift Left Double Logical) Machine Instruction Code 8D (RS Instruction) Condition code Remains unchanged Possible Interruptions 0006 The register specified as 1st operand indicates a pair of registers (R1st and R1st+1), taken as a number with 64-bit. This instruction shifts logically, to the left, the bits of the number inside the 2 registers (both treated as only onr number). All 64 bits are shifted (including sign bit). The “new” bits to the right are set to zero. It’s an RS instruction, and its bits are ignored. The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 63. Example: SLDL ,4 Registers 8 and 9 before Shift 12.FE.3D.4C 5B.6A.78.90 Registers 8 and 9 after Shift 2F.E3.D4.C5 B6.A Mach.Inst.Summary

Machine Instructions - SLL
SLL (Shift Left Logical) Machine Instruction Code 89 (RS Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur The register specified as 1st operand indicates a register, taken as a 32-bit number. This instruction shifts logically, to the left, the bits of the number inside the register. All 32 bits are shifted (including sign bit). The “new” bits to the right are set to zero. It’s an RS instruction, and its bits are ignored. The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 32. Example: SLL ,2 Register 5 before Shift B9.4F.FF.FF Register 5 after Shift E5.3F.FF.FC Mach.Inst.Summary

Machine Instructions - SLR
SLR (Subtract Logical Register) Machine Instruction Code 1F (RR Instruction) Condition code 00 Condition code is not set as 00 after SLR 01 Result <> 0, sign not lost 10 Result = 0, sign lost 11 Result <> 0, sign lost Possible Interruptions No interruptions occur Instruction SLR subtracts logically the binary number in the register 2nd operand from the binary number in the register 1st operand. Result is stored into 1st operand register. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register 1st operand after nd operand after SLR 7, B0.C4.E 00.B0.C4.E SLR 10, 7F.FF.FF.FF Mach.Inst.Summary

Machine Instructions - SP
SP (Subtract Packed) Machine Instruction Code FB (SS Instruction – L1 e L2) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions 0001,0004,0005,0007,000A This instruction subtracts the contents of the 2nd operand from the contents of the 1st operand. Both must be storage fields in the decimal packed format. Result is stored into 1st operand field. Examples: SP FLDA,FLDB Before After FLDB C C FLDA C C More examples: SP VALUE,VALUE SP TOTAL,=P'1' SP AE+5(8),AE+15(3) SP (2,7),4(1,8) Mach.Inst.Summary

Machine Instructions - SPM
SPM (Set Program Mask) Machine Instruction Code 04 (RR Instruction) Condition code Is set with the contents of bits 2 and 3 of register 1st operand Possible Interruptions No interruptions occur This is RR instruction. Its bits are not considered. The contents of 1st operand register is used to take the values of condition code and program mask to store them into PSW. The value of bits 2-3 are set to the condition code. The value of bits 4,5,6 and 7 are set to the PSW program mask. The bits 0-1 and 8-31 are ignored. Example: SPM 8 Mach.Inst.Summary

Machine Instructions - SR
SR (Subtract Register) Machine Instruction Code 1B (RR Instruction) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions 0008 This instruction subtracts the contents of the register 2nd operand from the contents of the register 1st operand. Result is stored into register 1st operand. Then: Minuend : 1st operand ; Subtrahend : 2nd operand ; Result : 1st operand Examples: Suppose the operands with the length and values shown in the “before” line Register 1st operand before Register 2nd operand before Register 1st operand after Register 2nd operand after SR 7, FF.FF 00.00.FF.FE SR 2, FF.FF FF.FF Mach.Inst.Summary

Machine Instructions - SRA
SRA (Shift Right Algebraic) Machine Instruction Code 8A (RS Instruction) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Condition code is not set as 11 after SRA Possible Interruptions No interruptions occur This instruction shifts algebraically, to the right, the bits of the register 1st operand. The sign bit remains unchanged, and the other 31 bits are shifted. The “new” bits to the right are set to zero. It’s an RS instruction, and its bits are ignored. The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 15. Example: SRA ,3 Register 5 before Shift FF.80.0A.00 Register 5 after Shift 8F.F Mach.Inst.Summary

Machine Instructions - SRDA
SRDA (Shift Right Double Algebraic) Machine Instruction Code 8E (RS Instruction) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Condition code is not set as 11 after SRDA Possible Interruptions 0006 The register specified as 1st operand indicates the a pair of registers (R1st and R1st+1), taken as a number with 64-bit (1 bit = sign; 63 bits = number). This instruction shifts algebraically, to the right, the bits of the number inside the 2 registers (both treated as only one number). The sign bit remains unchanged, and the other 63 bits are shifted. The “new” bits to the left are set to zero. It’s an RS instruction, and its bits are ignored. The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 63. Example: SRDA ,4 Registers 8 and 9 before Shift C FF Registers 8 and 9 after Shift C F Mach.Inst.Summary

Machine Instructions - SRDL
SRDL (Shift Right Double Logical) Machine Instruction Code 8C (RS Instruction) Condition code Remains unchanged Possible Interruptions 0006 The register specified as 1st operand indicates the a pair of registers (R1st and R1st+1), taken as a number with 64-bit. This instruction shifts logically, to the right, the bits of the number inside the 2 registers (both treated as only onr number). All 64 bits are shifted (including sign bit). The “new” bits to the left are set to zero. It’s an RS instruction, and its bits are ignored. The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 63. Example: SRDL ,4 Registers 8 and 9 before Shift 12.FE.3D.4C 5B.6A.78.90 Registers 8 and 9 after Shift 01.2F.E3.D4 C5.B6.A7.89 Mach.Inst.Summary

Machine Instructions - SRL
SRL (Shift Right Logical) Machine Instruction Code 88 (RS Instruction) Condition code Remains unchanged Possible Interruptions No interruptions occur The register specified as 1st operand indicates a register, taken as a 32-bit number. This instruction shifts logically, to the right, the bits of the number inside the register. All 32 bits are shifted (including sign bit). The “new” bits to the left are set to zero. It’s an RS instruction, and its bits are ignored. The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits to shift; maximum is 32. Example: SRL ,2 Register 5 before Shift B9.4F.FF.FF Register 5 after Shift 2E.53.FF.FF Mach.Inst.Summary

Machine Instructions - SRP
SRP (Shift and Round Packed) Machine Instruction Code F0 (SS Instruction) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions 0001,0004,0005,0007,000A This is a SS instruction, and its format is the following: 1 byte = operation code 1/2 byte = L1 = 1st operand length - 1 1/2 byte = I3 = 3rd operand (immediate operand) 2 bytes = 1st operand base+displacement address 2 bytes = 2nd operand base+displacement address The 1st operand is a decimal packed storage field; it is shifted based upon the information provided by the 2nd operand: the sense of shift and the amount of digits to be shifted. If shift is to be done rightwards the number is rounded accordingly 3rd operand. Mach.Inst.Summary

SRP (Shift and Round Packed) Machine Instruction Code F0 (SS Instruction) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions 0001,0004,0005,0007,000A The 6 rightmost bits of the number computed as the “address” of 2nd operand are analysed this way: · Leftmost bit indicates the sense of the shift: OFF means shift leftwards; ON means rightwards. · The number composed by the remaining 5 bits indicates the amount of digits to be shifted (if shift rightwards, this number is negative). The round is done by adding the number specified in the 3rd operand to the last shifted digit and, if it is 1, it is added to the number-result after shift. See the following examples: Mach.Inst.Summary

SRP (Shift and Round Packed) Machine Instruction Code F0 (SS Instruction) Condition code 00 Result = 0 01 Result < 0 10 Result > 0 11 Overflow Possible Interruptions 0001,0004,0005,0007,000A SRP TOTAL,61,5 TOTAL Before C TOTAL After C (shifts 3 digits to the right) SRP TOTAL,3,0 TOTAL Before C TOTAL After C (shifts 3 digits to the left) These rules make it easier to specify shift sense and amount of digits: Shift leftwards = specify directly the amount of digits SRP TOTAL,3,5 Specify amount in the 2nd operand = shifts “amount” digits to the left (in the example = 3) Shift rightwards = specify (64 – amount of digits) SRP TOTAL,64-3,5 Specify [64-amount] in the 2nd operand = shifts “amount” digits to the right (In the example = 3) Mach.Inst.Summary

Machine Instructions - ST
ST (Store [from register to storage]) Machine Instruction Code 50 (RX Instruction) Condition code Remains unchanged Possible Interruptions 0004,0005 The register 1st operand (remain unchanged and) is stored into the 2nd operand 4-byte storage field. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register1st operand after nd operand after ST 7,FULL FE.DC.BA FE.DC.BA FE.DC.BA.98 ST 14,SAVE FF.FF.FF.FD Other examples: ST ,FULL+4 ST ,0(2) ST ,0(,8) Mach.Inst.Summary

Machine Instructions - STC
STC (STore Character) Machine Instruction Code 42 (RX Instruction) Condition code Remains unchanged Possible Interruptions 0004,0005 The rightmost byte of register 1st operand (remain unchanged and) is stored into the 2nd operand 1-byte storage field. Examples: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register1st operand after nd operand after STC 7,BYTE FE.DC.BA FE.DC.BA STC 14,0(5) FF Mach.Inst.Summary

Machine Instructions - STCK
STCK (STore ClocK) Machine Instruction Code B205 (Instrução S) Condition code 00 Clock status allows set 01 Clock status does not allow set 10 Clock status is error 11 Condition code is not set as 11 after STCK Possible Interruptions 0004 TOD clock contents is stored into the 8-byte storage field specified in the 2nd operand. Clock must be is set, stop or no-set state. The rightmost bytes are set to zero. If TOD clock is in error state, contents stored is unpredictable. If TOD clock is not operational, all bytes are set to zero. Example: STCK DW Mach.Inst.Summary

Machine Instructions - STCM
STCM (STore Character under Mask) Machine Instruction Code BE (RS Instruction) Condition code Remains unchanged Possible Interruptions 0004,0005 The format of this instruction is: 1st byte: X’BE’ (operation code); 2nd byte, left half : 1st operand register ; 2nd byte, right half : 3rd operand (mask); 3rd and 4th bytes : 2nd operand address, base+displacement format. The 4 bits in the mask correspond to the 4 bytes of the 1st operand register. The storage field specified in the 2nd operand must have as many bytes as the ON bits in the mask. The register 1st operand bytes corresponding to the ON bits of the mask are stored into the 2nd operand storage bytes (taken as a contiguous field). 1st operand remains unchanged. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register1st operand after nd operand after STCM 5,B’1010’,TWOBYTES A.BC 1st byte of register 5 is stored into byte TWOBYTES and 3rd byte of register 5 is stored into byte TWOBYTES+1 Mach.Inst.Summary

Machine Instructions - STH
STH (STore Halfword) Machine Instruction Code 40 (RX Instruction) Condition code Remains unchanged Possible Interruptions 0004,0005 The rightmost 2 bytes of register 1st operand (remain unchanged and) are stored into the 2nd operand 2-byte storage field. Example: Suppose the operands with the length and values shown in the “before” line register 1st operand before nd operand before register1st operand after nd operand after STH 5,FLD A A.B4 A A STH 8,HWORD FF.FF.FF.FF FF.FF FF.FF.FF.FF FF.FF Other examples: STH ,SAVE+18 STH ,0(2) STH ,0(,8) STH ,0(2,8) STH ,FLD Mach.Inst.Summary

Machine Instructions - STM
STM (STore Multiple) Machine Instruction Code 90 (RX Instruction) Condition code Remains unchanged Possible Interruptions 0004,0005 This instruction works with 3 operands: 1st and 3rd are registers, and 2nd is a storage field. It stores the contents of the registers specified as a range by the 1st and 3rd operands into the storage field 2nd perand. The length of the field depends on how many registers must be stored. To store 2 registers, the area must have 8 bytes; to store 3 registers, the area must have 12 bytes, and so on. Example: STM ,1,SAVE SAVE = 16 bytes (bytes 0-3 = contents of register 14; bytes 4-7 = contents of register ; bytes 8-11 = contents of register 0; bytes = contents of register 1) | SAVE | < >< >< >< > Reg Reg Reg Reg.1 Another example: STM ,7,2(10) Mach.Inst.Summary

Machine Instructions - SVC
SVC (SuperVisor Call) Machine Instruction Code 0A (RR Instruction) Condition code (Remains unchanged in the old PSW) Possible Interruptions No interruptions occur The format of this instruction is: 1st byte = operation code; 2nd byte = SVC number This instruction causes a program interruption; this interruption demands CPU to execute a call to the operating system (supervisor) to execute some function. The code (2nd byte – from 0 to 255 – X’00’ up to X’FF’) determines the function to be executed by supervisor . Examples: SVC SVC Some MVS-z/OS SVCs: X'00' (000) = EXCP/XDAP X'13' (019) = OPEN X'01' (001) = WAIT/WAITR/PRTOV X'14' (020) = CLOSE X'02' (002) = POST X'23' (035) = WTO/WTOR X'04' (004) = GETMAIN X'24' (036) = WTL X'05' (005) = FREEMAIN X'5D' (093) = TGET/TPUT X'0B' (011) = TIME X'63' (099) = DYNALLOC X'0D' (013) = ABEND X'6B' (107) = MODESET Mach.Inst.Summary

Machine Instructions - TM
TM (Test under Mask) Machine Instruction Code 91 (SI Instruction) Condition code 00 All bits tested are OFF, or mask is zero 01 Some bits tested are ON and others are OFF 10 Condition code is not set as 10 after TM 11 All bits tested are ON Possible Interruptions 0005 This instruction tests the bits of the 1-byte storage field specified by the 1st operand, using the mask specified in the 2nd operand (self-defining term). The mask indicates whose bits must be tested. The ON bits in the mask indicate the bits of the stoprage byte to be tested. Test means: is the bit(s) ON or OFF? To reflect the result, condition code is set. Example: TM BYTE,X'9C' Bits 0, 3, 4 and 5 of BYTE are tested More examples: TM KEYAB,B' ' Bits 0, and 7 of KEYAB are tested TM 0(4), Bits 4,5,6 and 7 of [base register 4 + displacement X’0’] are tested TM 2(8),X'80' Bit 0 [base register 8 + displacement X’2’] is tested Mach.Inst.Summary

Machine Instructions - TR
TR (TRanslate) Machine Instruction Code DC (SS Instruction – L) Condition code Remains unchanged Possible Interruptions 0004,0005 TR instruction moves the contents of 2nd operand to the 1st operand, according to the 1st operand contents. The move is done left to right, each byte at a time, this way: · The contents of each byte of the 1st operand is added (internally) to the 2nd operand address; · The byte at the resulting address is moved (copied) to the byte of the 1st operand. · 2nd operand remains unchanged Example: TR ACSD,TABLE Before ACSD FF.05 TABLE C1.48.B9.D7.A1.C3.D9.5C.4B A bytes After ACSD B9.C1.4B.1A.C3 TABLE Remains unchanged More examples : TR (5,7),0(10) TR WAREA+7(10),TABASTER TR (5,124),FIELD Mach.Inst.Summary

TR (TRanslate) Machine Instruction Code DC (SS Instruction – L) Condition code Remains unchanged Possible Interruptions 0004,0005 More examples : To translate uppercase EBCDIC letters into lowercase EBCDIC letters; invalid letters are converted to EBCDIC spaces CONVTB1 DC 256C' ' EBCDIC spaces ORG CONVTB1+C'A' “Return” to Uppercase A DC C'abcdefghi' Substitute original spaces by lowwercase ORG CONVTB1+C'J' “Return” to Uppercase J DC C'jklmnopqr' Substitute original spaces by lowwercase ORG CONVTB1+C'S' “Return” to Uppercase S DC C'stuvwxyz' Substitute original spaces by lowwercase ORG , Return to byte folowing CONVTB1 To translate uppercase EBCDIC letters into uppercase ASCII letters; invalid letters are converted to ASCII spaces CONVTB2 DC 256X'20' ASCII spaces ORG CONVTB2+C'A' “Return” to Uppercase A DC X' ' Substitute EBCDIC value by ASCII value DC X'4A4B4C4D4E4F505152' Substitute EBCDIC value by ASCII value DC X' A' Substitute EBCDIC value by ASCII value ORG , Return to byte folowing CONVTB2 Mach.Inst.Summary

TR (TRanslate) Machine Instruction Code DC (SS Instruction – L) Condition code Remains unchanged Possible Interruptions 0004,0005 More examples : To translate uppercase ASCII letters into uppercase EBCDIC letters; invalid “letters” are converted to EBCDIC spaces CONVTB3 DC 256X'40' EBCDIC spaces ORG CONVTB2+X'41' Volta para A maiusculo ASCII DC C'ABCDEFGHIJKLMNOPQRSTUVWXYZ' Substitui ASCII value by EBCDIC ORG , Return to byte CONVTB3+256 Mach.Inst.Summary

Machine Instructions - TRT
TRT (TRanslate and Test) Machine Instruction Code DD (SS Instruction – L) Condition code 00 All bytes tested are with X'00' 01 Test ended before the last byte to be tested. 10 Test ended at the last byte to be tested, and it wasn’t with X'00' 11 Condition code is not set as 11 after TRT Possible Interruptions 0005 This instruction tests bytes of the 2nd operand, verifying their status (X’00’ or not). The 1st tested byte NOT in X’00’ ends the instruction execution. 1st operand indicates the 2nd operand bytes to be tested: TRT adds the contents of each byte of the 1st operand to the 2nd operand address (same as TR instruction); the byte at the resulting address is tested with X’00’. When a non-X’00’ byte is detected instruction stores in the register 1 (bits 8-31; bits 0-7 remain unchanged) the address of the 1st operand byte that lead to the 2nd operand non-X’00’ byte; it also stores in register 2 (bits 24-31; bits 0-23 remain unchanged) the contents of the 2nd operand byte not in X’00’. This instruction is generally used to: Mach.Inst.Summary

TRT (TRanslate and Test) Machine Instruction Code DD (SS Instruction – L) Condition code 00 All bytes tested are with X'00' 01 Test ended before the last byte to be tested. 10 Test ended at the last byte to be tested, and it wasn’t with X'00' 11 Condition code is not set as 11 after TRT Possible Interruptions 0005 a) Validate a decimal zoned field (1st operand – only valid digits): TRT CART+9(6),TABNUM BZ NUMÉRIC . TABNUM DC X'FF',10X'00',6X'FF' b) Validate an alphanumeric field (1st operand – only uppercase letters and spaces) TRT CART+9(6),TABALFAB BZ FABETIC TABALFA DC CL256X'FF' ORG TABALFAB+C' ' DC X'00' ORG TABALFAB+C'A' DC X'00' ORG TABALFAB+C'J' ORG TABALFAB+C'S' DC X'00' ORG Mach.Inst.Summary

TRT (TRanslate and Test) Machine Instruction Code DD (SS Instruction – L) Condition code 00 All bytes tested are with X'00' 01 Test ended before the last byte to be tested. 10 Test ended at the last byte to be tested, and it wasn’t with X'00' 11 Condition code is not set as 11 after TRT Possible Interruptions 0005 c) Find a character (* in the example) in a string of characters (e.g. for parsing). TRT (80,7),TABASTER BZ NOTASTER register 1 has the byte with * . TABASTER DC X'00' ORG TABASTER+C'*' DC X'FF' ORG Mach.Inst.Summary

Machine Instructions - TS
TS (Test ans Set) Machine Instruction Code 93 (Instrução S) Condition code 00 Leftmost bit OFF 01 Leftmost bit ON 10 Condition code is not set as 10 after TS 11 Condition code is not set as 11 after TS Possible Interruptions 0004,0005 Second byte of instruction is ignored. The leftmost bit of the (only) operand is tested (ON or OFF). After the test all bits of the byte are set to 1 (ON). Condition code is set according to the result of the test. Example: TS BYTE Mach.Inst.Summary

Machine Instructions - UNPK
UNPK (UNPacK) Machine Instruction Code F3 (SS Instruction – L1 e L2) Condition code Remains unchanged Possible Interruptions 0004,0005 The UNPK instruction moves a storage packed field to a storage zoned field. The intended function is to convert a numeric field from packed format to zoned format. NO validation is done in the sending field; if its contents is not a valid decimal packed number, the operation flows normally. 1st operand is the receiving field and 2nd operand is the sending field. The operation is done from right to left. The two halves of the rightmost byte of the sending field are inverted and moved to the rightmost byte of the receiving field. After that, each half byte of the sending field is sent to a right half of a receiving field byte, and the left half is set to X’F’. 2nd operand remains unchanged. If the receiving field is smaller than needed to fit all digits from the sending field, the leftmost digits are truncated. If the receiving field is greater than needed to fit all digits from sending field, the remaining left bytes are filled with X’F0’. Example: UNPK FLDA,FLDB Before After FLDB C C FLDA B8.4C.D0 F2.F3.F4.C5 Mach.Inst.Summary

Machine Instructions - UNPK
UNPK (UNPacK) Machine Instruction Code F3 (SS Instruction – L1 e L2) Condition code Remains unchanged Possible Interruptions 0004,0005 More examples: UNPK FLDA,FLDB Before After FLDB C C FLDA B8.4C.D0 F0.F1.F2.C3 UNPK WRITAREA+5(12),TOTLIQ UNPK AX2,2(3,7) UNPK (10,8),T4B2F+3(5) UNPK (13,10),0(5,3) Mach.Inst.Summary

Machine Instructions - X
X ([boolean] eXclusive or Character) Machine Instruction Code 57 (RX Instruction) Condition code 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after X 11 Condition code is not set as 11 after X Possible Interruptions 0005 This instruction executes a boolean Exclusive OR between a register (1st operand) and a 4-byte storage field (2nd operand). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = inverted Example: X ,FIELDF Before After Register 13 B4.EF.2F.A8 B4.EF.2F.57 FIELDF FF FF Mach.Inst.Summary

Machine Instructions - XC
XC ([boolean] eXclusive or Character) Machine Instruction Code D7 (SS Instruction – L) Condition code 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after XC 11 Condition code is not set as 11 after XC Possible Interruptions 0004, 0005 This instruction executes a boolean EXCLUSIVE OR between 2 storage fields (1st and 2nd operands). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = inverted Example: XC FLDA,FLDB Before After FLDA EF.2F.A8 EF.2F.57 FLDB FF Mach.Inst.Summary

Machine Instructions - XI
XI ([boolean] eXclusive or [with] Immediate [operand]) Machine Instruction Code 97 (SI Instruction) Condition code 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after OI 11 Condition code is not set as 11 after OI Possible Interruptions 0004, 0005 This instruction executes a boolean EXCLUSIVE OR between 2 storage fields (1 byte each; 1st operand = field specified using its address; 2nd operand = immediate field, it’s the 2nd byte of the instruction). Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = inverted Example: NI BYE,X’0F’ before After BYTE B BB Immediate operand 0F F Mach.Inst.Summary

Machine Instructions - XR
XR ([boolean] eXclusive or Register) Machine Instruction Code 17 (RR Instruction) Condition code 00 Result = 0 01 Result <> 0 10 Condition code is not set as 10 after XR 11 Condition code is not set as 11 after XR Possible Interruptions No interruptions occur This instruction executes a boolean EXCLUSIVE OR between 2 registers. Mask bit =0 then result bit = remains unchanged; mask bit = 1 then reault bit = inverted Example: XR ,8 Before After Register B4.EF.2F.A8 B4.EF.2F.57 Register FF FF Mach.Inst.Summary

Machine Instructions - ZAP
ZAP (Zero and Add Packed) Machine Instruction Code F8 (SS Instruction – L1 e L2) Condition code 00 Sender field = 0 01 Sender field < 0 10 Sender field > 0 11 Overflow Possible Interruptions 0001,0004,0005,0007,000A 2nd operand must be a packeddecimal storage field. This instruction zeroes (decimal packed zero) the 1st operand and add the value of the 2st operand to the 1st. 2nd operand remains unchanged. Note that this process is done internally (in the CPU). That’s the reason one can specify the same storage field as 1st and also as 2nd operand; this is often used to test the number (positive, negative or zero) because ZAP sets the condition code When we do ZAP FLD,FLD before zeroing FLD, its contents are internally saved. After being zeroed, when add is done the original contents is available; then it returns to the original value. Mach.Inst.Summary

Machine Instructions - ZAP
ZAP (Zero and Add Packed) Machine Instruction Code F8 (SS Instruction – L1 e L2) Condition code 00 Se o campo movido = 0 01 Se o campo movido < 0 10 Se o campo movido > 0 11 Overflow Possible Interruptions 0001,0004,0005,0007,000A ZAP CPOA,CPOB Before After 1st Case CPOB C C CPOA B4.F C 2nd Case CPOB C C CPOA B C More examples: ZAP TOTAL,=P'0' ZAP CONTLIN,=P'2' Mach.Inst.Summary

Macro Instructions MACRO INSTRUCTIONS

Sorry... It’s not in the scope of this course...
Macro Instructions MACRO INSTRUCTIONS Sorry... It’s not in the scope of this course...

Appendix - Links LINKS z/Architecture
ESA Enterprise Systems Architecture / XC Extended Configuration (para z/VM) High Level Assembler

Appendix – Instructions by operation code
Some instructions (ordered by operation code) Mnemonic Code Type SR B RR MR C RR DR D RR ALR E RR SLR F RR STH RX LA RX STC RX IC RX EX RX BAL RX BCT RX BC RX LH RX CH RX AH A RX SH B RX MH C RX BAS D RX CVD E RX Mnemonic Code Type CVB F RX ST RX LAE RX N RX CL RX O RX X RX L RX C RX A A RX S B RX M C RX D D RX AL E RX SL F RX STD RX MXD RX LD RX CD RX AD A RX Mnemonic Code Type BALR RR BCTR RR BCR RR SVC A RR BSM B RR BASSM 0C RR BASR D RR MVCL E RR CLCL F RR LPR RR LNR RR LTR RR LCR RR NR RR CLR RR OR RR XR RR LR RR CR RR AR A RR Continues...

Appendix – Instructions by operation code
Some instructions (ordered by operation code) Mnemonic Code Type SD B RX MD C RX DD D RX AW E RX SW F RX STE RX LE RX CE RX BXH RS BXLE RS SRL RS SLL RS SRA A RS SLA B RS SRDL C RS SLDL D RS SRDA E RS SLDA F RS STM RS TM SI Mnemonic Code Type MVI SI TS S NI SI CLI SI OI SI XI SI LM RS MC AF SI LRA B RX STCK B S CS BA RS CDS BB RS CLM BD RS STCM BE RS ICM BF RS MVN D SS/L MVC D SS/L MVZ D SS/L NC D SS/L CLC D SS/L Mnemonic Code Type OC D SS/L XC D SS/L TR DC SS/L TRT DD SS/L ED DE SS/L EDMK DF SS/L MVCIN E SS/L SRP F SS/L1I3 MVO F SS/L1L2 PACK F SS/L1L2 UNPK F SS/L1L2 ZAP F SS/L1L2 CP F SS/L1L2 AP FA SS/L1L2 SP FB SS/L1L2 MP FC SS/L1L2 DP FD SS/L1L2

Appendix – Instructions by mnemonic
Some instructions (ordered by mnemonic) Mnemonic Code Type A A RX AD A RX AH A RX AL E RX ALR E RR AP FA SS/L1L2 AR A RR AW E RX BAL RX BALR RR BAS D RX BASR D RR BASSM 0C RR BC RX BCR RR BCT RX BCTR RR BSM B RR BXH RS BXLE RS Mnemonic Code Type C RX CD RX CDS BB RS CE RX CH RX CL RX CLC D SS/L CLCL F RR CLI SI CLM BD RS CLR RR CP F SS/L1L2 CR RR CS BA RS CVB F RX CVD E RX D D RX DD D RX DP FD SS/L1L2 DR D RR Mnemonic Code Type ED DE SS/L EDMK DF SS/L EX RX IC RX ICM BF RS L RX LA RX LAE RX LCR RR LD RX LE RX LH RX LM RS LNR RR LPR RR LR RR LRA B RX LTR RR M C RX MC AF SI Continues...

Appendix – Instructions by mnemonic
Some instructions (ordered by mnemonic) Mnemonic Code Type MD C RX MH C RX MP FC SS/L1L2 MR C RR MVC D SS/L MVCIN E SS/L MVCL E RR MVI SI MVN D SS/L MVO F SS/L1L2 MVZ D SS/L MXD RX N RX NC D SS/L NI SI NR RR O RX OC D SS/L OI SI OR RR Mnemonic Code Type PACK F SS/L1L2 S B RX SD B RX SH B RX SL F RX SLA B RS SLDA F RS SLDL D RS SLL RS SLR F RR SP FB SS/L1L2 SR B RR SRA A RS SRDA E RS SRDL C RS SRL RS SRP F SS/L1I3 ST RX STC RX STCK B S Mnemonic Code Type STCM BE RS STD RX STE RX STH RX STM RS SVC A RR SW F RX TM SI TR DC SS/L TRT DD SS/L TS S UNPK F SS/L1L2 X RX XC D SS/L XI SI XR RR ZAP F SS/L1L2

Appendix – EBCDIC - Some characters
Some EBCDIC configurations HEX CARATER 40 Space 60 - hiphen 81 a A2 s D0 } Right brace F0 4B . point 61 / slash 82 b A3 t D1 J F1 1 4C < less than 6B , comma 83 c A4 u D2 K F2 2 4D ( Left parenheses 6C % percent 84 d A5 v D3 L F3 3 4E + Plus sign 6D _ underscore 85 e A6 w D4 M F4 4 4F | Vertical bar 6E > Greater than 86 f A7 x D5 N F5 5 50 & Ampersand 6F ? Question mark 87 g A8 y D6 O F6 6 5A ! Exclamation mark 7A : colon 88 h A9 z D7 P F7 7 5B $ Dollar sign 7B # number sign 91 i C0 { Left brace D8 Q F8 8 5C * Asterisk 7C @ at 92 j C1 A D9 R F9 9 5D ) Right parentheses 7D ' apostrophe 93 k C2 B E0 \ Backslash 5E ; Semicolon 7E = equals 94 l C3 C E2 S 5F  Not 7F " quotes 95 m C4 D E3 T 96 n C5 E E4 U 97 o C6 F E5 V 98 p C7 G E6 W 99 q C8 H E7 X 9A r C9 I E8 Y E9 Z

Appendix – ASCII - Some characters
Some ASCII configurations HEX CARATER 20 Space 30 0 zero 40 @ at 50 P 60 ` grave accent 70 p 21 ! exclamation mark 31 1 one 41 A 51 Q 61 a 71 q 22 “ quotes 32 2 two 42 B 52 R 62 b 72 r 23 # number 33 3 three 43 C 53 S 63 c 73 s 24 $ dollar sign 34 4 four 44 D 54 T 64 d 74 t 25 % percent sign 35 5 five 45 E 55 U 65 e 75 u 26 & ampersand 36 6 six 46 F 56 V 66 f 76 v 27 ‘ apostrophe 37 7 seven 47 G 57 W 67 g 77 w 28 ( Left parentheses 38 8 eight 48 H 58 X 68 h 78 x 29 ) Right parentheses 39 9 nine 49 I 59 Y 69 i 79 y 2A * asterisk 3A : colon 4A J 5A Z 6A j 7A z 2B + plus sign 3B ; semicolon 4B K 5B [ Left bracket 6B k 7B { Left brace 2C , comma 3C < less than 4C L 5C \ back slash 6C l 7C | Vertical Slash 2D - hyphen 3D = equals 4D M 5D ] Right bracket 6D m 7D } Right brace 2E . point 3E > greater 4E N 5E ^ circumflex 6E n 7E ~ tilde 2F / slash 3F ? question mark 4F O 5F _ (underscore) 6F o

Questions Questions

(Q) Exercises 1-12 (Convert decimal to binary)

(Q) Exercises 13-24 (Convert decimal to hexadecimal)

(Q) Exercises 25-36 (Convert binary to hexadecimal)

(Q) Exercises 37-48 (Convert hexadecimal to binary)
Exercise 37 : (CAFE)16 = (?)2 Exercise 38 : (CDF)16 = (?)2 Exercise 39 : (1AB4D)16 = (?)2 Exercise 40 : (15)16 = (?)2 Exercise 41 : (F)16 = (?)2 Exercise 42 : (87B54)16 = (?)2 Exercise 43 : (1001)16 = (?)2 Exercise 44 : (234)16 = (?)2 Exercise 45 : (CAD)16 = (?)2 Exercise 46 : (7F7)16 = (?)2 Exercise 47 : (1990)16 = (?)2 Exercise 48 : (33)16 = (?)2

(Q) Exercises 49-60 (Convert binary to decimal)

(Q) Exercises 61-72 (Convert hexadecimal to decimal)
Exercise 62 : (AAF45)16 = (?)10 Exercise 63 : (1B567)16 = (?)10 Exercise 64 : (100)16 = (?)10 Exercise 65 : (1000)16 = (?)10 Exercise 66 : (FF)16 = (?)10 Exercise 67 : (FFF)16 = (?)10 Exercise 68 : (CDF)16 = (?)10 Exercise 69 : (CAFE)16 = (?)10 Exercise 70 : (FACA)16 = (?)10 Exercise 71 : (DAD0)16 = (?)10 Exercise 72 : (F1E2D3C4)16 = (?)10

(Q) Exercises 73-84 (Add numbers in binary)

(Q) Exercises 85-96 (Subtract numbers in binary)

(Q) Exercises 97-108 (Add numbers in hexadecimal)
Exercise 97 : (F12B)16 + (321)16 = (?)16 Exercise 98 : (1100)16 + (111)2 = (?)16 Exercise 99 : (1000F)16 + (F0001)16 = (?)16 Exercise 100 : (A9B8C7)16 + (D6E5F4)16 = (?)16 Exercise 101 : (CAFE)16 + (CDF)16 = (?)16 Exercise 102 : (B001)16 + (FD)16 = (?)16 Exercise 103 : (999)16 + (111)16 = (?)16 Exercise 104 : (123456)16 + (789ABC)16 = (?)16 Exercise 105 : (FFF)16 + (EEE)16 = (?)16 Exercise 106 : (DDD)16 + (333)16 = (?)16 Exercise 107 : (987AED)16 + (CF01)16 = (?)16 Exercise 108 : (FACA)16 + (CAFE)16 = (?)16

(Q) Exercises 109-120 (Subtract numbers in hexadecimal)
Exercise 109 : (F1C5)16 - (101)16 = (?)16 Exercise 110 : (1AD87C)16 - (FDE9)2 = (?)16 Exercise 111 : (112233)16 - (44556)16 = (?)16 Exercise 112 : (AABBCC)16 - (DDEEF)16 = (?)16 Exercise 113 : (F1E2D3)16 - (C4B5A6)16 = (?)16 Exercise 114 : (FF00001)16 - (10000F)16 = (?)16 Exercise 115 : (CAFE)16 - (FACA)16 = (?)16 Exercise 116 : (CDF)16 - (FDC)16 = (?)16 Exercise 117 : (10001)16 - (20001)16 = (?)16 Exercise 118 : (10000)16 - (FFFE)16 = (?)16 Exercise 119 : (0)16 - (9)16 = (?)16 Exercise 120 : (0)16 - (1A)16 = (?)16

(Q) Exercises 121-126 (Representing binary numbers in bytes)
Exercise 121 : (1)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16 Exercise 122 : (-1)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16 Exercise 123 : (10)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16 Exercise 124 : (-10)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16 Exercise 125 : (17)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16 Exercise 126 : (-17)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16

Exercise 127 : (254)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16 Exercise 128 : (-254)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16 Exercise 129 : (100000)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16 Exercise 130 : ( )10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16 Exercise 131 : (32000)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16 Exercise 132 : (-32000)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16

Exercise 133 : (63000)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16 Exercise 134 : (-63000)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16 Exercise 135 : (1010)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16 Exercise 136 : (-1010)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16 Exercise 137 : (4095)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16 Exercise 138 : (-4095)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16

Exercise 139 : (4097)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16 = (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16 Exercise 140 : (-4097)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16

(Q) Exercises 141-152 (Representing packed numbers in bytes)
Exercise 141 : (1)10 = (in decimal-packed format) Exercise 142 : (-1)10 = (in decimal-packed format) Exercise 143 : (10)10 = (in decimal-packed format) Exercise 144 : (-10)10 = (in decimal-packed format) Exercise 145 : (17)10 = (in decimal-packed format) Exercise 146 : (-17)10 = (in decimal-packed format) Exercise 147 : (254)10 = (in decimal-packed format) Exercise 148 : (-254)10 = (in decimal-packed format) Exercise 149 : (100000)10 = (in decimal-packed format) Exercise 150 : ( )10 = (in decimal-packed format) Exercise 151 : (32000)10 = (in decimal-packed format) Exercise 152 : (-32000)10 = (in decimal-packed format)

(Q) Exercises 153-160 (Representing packed numbers in bytes)
Exercise 153 : (63000)10 = (in decimal-packed format) Exercise 154 : (-63000)10 = (in decimal-packed format) Exercise 155 : (1010)10 = (in decimal-packed format) Exercise 156 : (-1010)10 = (in decimal-packed format) Exercise 157 : (4095)10 = (in decimal-packed format) Exercise 158 : (-4095)10 = (in decimal-packed format) Exercise 159 : (4097)10 = (in decimal-packed format) Exercise 160 : (-4097)10 = (in decimal-packed format)

(Q) Exercises 161-172 (Representing zoned numbers in bytes)
Exercise 161 : (1)10 = (in decimal-zoned format) Exercise 162 : (-1)10 = (in decimal-zoned format) Exercise 163 : (10)10 = (in decimal-zoned format) Exercise 164 : (-10)10 = (in decimal-zoned format) Exercise 165 : (17)10 = (in decimal-zoned format) Exercise 166 : (-17)10 = (in decimal-zoned format) Exercise 167 : (254)10 = (in decimal-zoned format) Exercise 168 : (-254)10 = (in decimal-zoned format) Exercise 169 : (100000)10 = (in decimal-zoned format) Exercise 170 : ( )10 = (in decimal-zoned format) Exercise 171 : (32000)10 = (in decimal-zoned format) Exercise 172 : (-32000)10 = (in decimal-zoned format)

(Q) Exercises 173-180 (Representing zoned numbers in bytes)
Exercise 173 : (63000)10 = (in decimal-zoned format) Exercise 174 : (-63000)10 = (in decimal-zoned format) Exercise 175 : (1010)10 = (in decimal-zoned format) Exercise 176 : (-1010)10 = (in decimal-zoned format) Exercise 177 : (4095)10 = (in decimal-zoned format) Exercise 178 : (-4095)10 = (in decimal-zoned format) Exercise 179 : (4097)10 = (in decimal-zoned format) Exercise 180 : (-4097)10 = (in decimal-zoned format)

(Q) Exercises 181-194 (Representing character strings in bytes)
Exercise 181 : “17“ = (in alphanumeric EBCDIC) Exercise 182 : “-17“ = (in alphanumeric EBCDIC) Exercise 183 : “AF$BD“ = (in alphanumeric EBCDIC) Exercise 184 : “-AF4BD“ = (in alphanumeric EBCDIC) Exercise 185 : “ALBERTO“ = (in alphanumeric EBCDIC) Exercise 186 : “15-9“ = (in alphanumeric EBCDIC) Exercise 187 : “-4095“ = (in alphanumeric EBCDIC) Exercise 188 : “4095“ = (in alphanumeric EBCDIC) Exercise 189 : “*&$//“ = (in alphanumeric EBCDIC) Exercise 190 : “12+3“ = (in alphanumeric EBCDIC) Exercise 191 : “I LOVE HER“ = (in alphanumeric EBCDIC) Exercise 192 : “US$ 2,584.73“ = (in alphanumeric EBCDIC) Exercise 193 : “US$ 1 MILLION“ = (in alphanumeric EBCDIC) Exercise 194 : “PANCHO’S BAR“ = (in alphanumeric EBCDIC)

(Q) Exercises 195-209 (Representing fields in bytes)
Exercises must be considered as a program starting at address X’ ’, that is, first area (exercise 195) begins at address zero. The DS defined areas must be computed to determine the addresses. Assume the 1st statement of the program is USING *,9. Exercise 195: DC C'123' Exercise 196: DC C'+123' Exercise 197: DC C'-123' Exercise 198: DC C'12.3' Exercise 199: DC C'1AB8' Exercise 200: DC C'01101' Exercise 201: DC C'A+B=C' Exercise 202: DC CL4'A' Exercise 203: DC CL4'ABCDEF' Exercise 204: DC 3CL2'A' Exercise 205: DC 2CL3'A,B' Exercise 206: DC C'ME&&YOU' Exercise 207: DC C'''S MUSIC' Exercise 208: DC Exercise 209: DC CL3'*'

Exercise 210: DC 3C'*' Exercise 211: DC X'123' Exercise 212: DC X'-123' Exercise 213: DC X'1AB2C3' Exercise 214: DC X'1AB2F4G3' Exercise 215: DC XL3'12D' Exercise 216: DC XL3'AABBCCDDEE' Exercise 217: DC X'1,22,333,4444' Exercise 218: DC XL2'1,22,333' Exercise 219: DC 2X'1,22,333' Exercise 220: DC 2XL2'1,22' Exercise 221: DC B' ' Exercise 222: DC B'1' Exercise 223: DC BL2'1111' Exercise 224: DC B'1, ' Exercise 225: DC BL2'1, '

Exercise 226: DC 2B'1000' Exercise 227: DC 2BL2'1000' Exercise 228: DC F'10' Exercise 229: DC F'+10' Exercise 230: DC F'-10' Exercise 230: DC F'-15,+16' Exercise 231: DC 2F'22' Exercise 232: DC 2F'33,44' Exercise 233: DC FL3'258' Exercise 234: DC 2FL1'255' Exercise 235: DC F'128000' Exercise 236: DC H'10' Exercise 237: DC H'+10' Exercise 238: DC H'-10' Exercise 239: DC H'-15,+16'

Exercise 240: DC 2H'22' Exercise 241: DC 2H'33,44' Exercise 242: DC HL3'258' Exercise 243: DC 2HL1'255' Exercise 244: DC H'128000' Exercise 245: DC P'123' Exercise 246: DC P'+123' Exercise 247: DC P'-123' Exercise 248: DC PL4'456' Exercise 249: DC PL1'789' Exercise 250: DC P'1,-22,333,-4444' Exercise 251: DC PL2'1,-22,333,-4444' Exercise 252: DC 3P'0' Exercise 253: DC PL3'0' Exercise 254: DC 2P'1,22,333'

Exercise 255: DC 2PL2'1,22,333' Exercise 256: DC Z'123' Exercise 257: DC Z'+123' Exercise 258: DC Z'-123' Exercise 259: DC ZL4'456' Exercise 260: DC ZL1'789' Exercise 261: DC Z'1,-22,333,-4444' Exercise 262: DC ZL3'1,-22,333,-4444' Exercise 263: DC 3Z'0' Exercise 264: DC ZL3'0' Exercise 265: DC 2Z'1,22,333' Exercise 266: DC 2ZL3'1,22,333'

Exercise 267: SIMBZZ DC A(0) Exercise 268: SIMBAA DC A(127) Exercise 269: SIMBBB DC A(X'8000') Exercise 270: SIMBCC DC A(B'1111') Exercise 271: SIMBDD DC A(C'*') Exercise 272: SIMBEE DC A(*) Exercise 273: SIMBFF DS CL17 Exercise 274: SIMBGG DC A(*) Exercise 275: SIMBHH DC A(SIMBGG) Exercise 276: SIMBII DC A(SIMBAA+12) Exercise 277: SIMBJJ DC A(SIMBII-SIMBBB) Exercise 278: SIMBKK DC AL1(*-SIMBKK) Exercise 279: SIMBLL DC 5AL1(*-SIMBLL)

Exercise 280: SIMBMM DC AL2(3,5,7) Exercise 281: SIMBNN DC A(SIMBII+5*2) Exercise 282: SIMBOO DC A(SIMBNN+X' ') Exercise 283: SIMBPP DC 4AL2(*-SIMBPP) Exercise 284: SIMBQQ DC A(SIMBVV) Exercise 285: SIMBRR DC A(SIMBKK,SIMBJJ) Exercise 286: SIMBSS DC A(SIMBTT+40) Exercise 287: SIMBTT DC A(SIMBUU,*,80) Exercise 288: SIMBUU DC 2A(*-SIMBUU) Exercise 289: SIMBVV DC A(C'AMO') Exercise 290: SIMBWW DC A(X'7FFFFFFF')

Exercise 291: YY1 DC Y(SIMBWW) Exercise 292: YY2 DC Y(10) Exercise 293: YY3 DC Y(L'YY2) Exercise 294: SS1 DC S(SIMBAA) Exercise 295: SS2 DC S(SS1) Exercise 296: SS3 DC S(10) Exercise 297: SS4 DC S(*) Exercise 298: SS5 DC A(125),F'33',C'*',2H'6,18' Exercise 299: SS6 DC X'1,1',B'1,1',C'1,1' Exercise 300: LAST DC 256AL1(255+LAST-*)

(Q) Exercise 301 (Decoding instructions)
Exercise 301 : Decode the following set of instructions; for each one, specify: Operation code (machine code) Menmonic Assembler code - Instruction address (suppose 1st instruction at address X’ ’) - Operands (register, base register, index register, displacement; if operand is in storage, compute the operand address; to compute the operand’s addresses suppose the general registers with the following contents: R00= R04= R08= R12=00000C00 R01= R05= R09= R13=00000D00 R02= R06= R10=00000A00 R14=00000E00 R03= R07= R11=00000B00 R15=00000F00 Instructions to decode: 1ABB41278CF00A13980F334445E00CB490EC0D00FA CCD

Answers Answers

(A) Exercises 1-12 (Convert decimal to binary)

(A) Exercises 13-24 (Convert decimal to hexadecimal)
Exercise 13 : (987654)10 = (F1206)16 Exercise 14 : (4095)10 = (FFF)16 Exercise 15 : (7)10 = (7)16 Exercise 16 : (1023)10 = (3FF)16 Exercise 17 : (4096)10 = (1000)16 Exercise 18 : (255)10 = (FF)16 Exercise 19 : (1024)10 = (400)16 Exercise 20 : ( )10 = (98BD91)16 Exercise 21 : (256)10 = (100)16 Exercise 22 : (1025)10 = (401)16 Exercise 23 : (999888)10 = (F41D0)16 Exercise 24 : (65432)10 = (FF98)16

(A) Exercises 25-36 (Convert binary to hexadecimal)
Exercise 25 : ( )2 = (7C7521)16 Exercise 26 : ( )2 = (2071FE0FE)16 Exercise 27 : (1100)2 = (C)16 Exercise 28 : ( )2 = (7F1)16 Exercise 29 : ( )2 = (AAA8CC7)16 Exercise 30 : ( )2 = (199999)16 Exercise 31 : ( )2 = (8001)16 Exercise 32 : ( )2 = (201)16 Exercise 33 : ( )2 = (1FC07F)16 Exercise 34 : (1)2 = (1)16 Exercise 35 : ( )2 = (CAFE)16 Exercise 36 : ( )2 = (56B8E01F8F)16

(A) Exercises 37-48 (Convert hexadecimal to binary)
Exercise 37 : (CAFE)16 = ( )2 Exercise 38 : (CDF)16 = ( )2 Exercise 39 : (1AB4D)16 = ( )2 Exercise 40 : (15)16 = (10101)2 Exercise 41 : (F)16 = (1111)2 Exercise 42 : (87B54)16 = ( )2 Exercise 43 : (1001)16 = ( )2 Exercise 44 : (234)16 = ( )2 Exercise 45 : (CAD)16 = ( )2 Exercise 46 : (7F7)16 = ( )2 Exercise 47 : (1990)16 = ( )2 Exercise 48 : (33)16 = (110011)2

(A) Exercises 49-60 (Convert binary to decimal)

(A) Exercises 61-72 (Convert hexadecimal to decimal)
Exercise 62 : (AAF45)16 = (700229)10 Exercise 63 : (1B567)16 = (111975)10 Exercise 64 : (100)16 = (256)10 Exercise 65 : (1000)16 = (4096)10 Exercise 66 : (FF)16 = (255)10 Exercise 67 : (FFF)16 = (4095)10 Exercise 68 : (CDF)16 = (3295)10 Exercise 69 : (CAFE)16 = (51966)10 Exercise 70 : (FACA)16 = (64202)10 Exercise 71 : (DAD0)16 = (56016)10 Exercise 72 : (F1E2D3C4)16 = ( )10

(A) Exercises 73-84 (Add numbers in binary)

(A) Exercises 85-96 (Subtract numbers in binary)

(A) Exercises 97-108 (Add numbers in hexadecimal)
Exercise 97 : (F12B)16 + (321)16 = (F44C)16 Exercise 98 : (1100)16 + (111)2 = (1211)16 Exercise 99 : (1000F)16 + (F0001)16 = (100010)16 Exercise 100 : (A9B8C7)16 + (D6E5F4)16 = (1809EBB)16 Exercise 101 : (CAFE)16 + (CDF)16 = (D7DD)16 Exercise 102 : (B001)16 + (FD)16 = (B0FE)16 Exercise 103 : (999)16 + (111)16 = (AAA)16 Exercise 104 : (123456)16 + (789ABC)16 = (19BBF12)16 Exercise 105 : (FFF)16 + (EEE)16 = (1EED)16 Exercise 106 : (DDD)16 + (333)16 = (1110)16 Exercise 107 : (987AED)16 + (CF01)16 = (9949EE)16 Exercise 108 : (FACA)16 + (CAFE)16 = (1C5C8)16

(A) Exercises 109-120 (Subtract numbers in hexadecimal)
Exercise 109 : (F1C5)16 - (101)16 = (F0C4)16 Exercise 110 : (1AD87C)16 - (FDE9)2 = (19DA93)16 Exercise 111 : (112233)16 - (44556)16 = (CDCDD)16 Exercise 112 : (AABBCC)16 - (DDEEF)16 = (9CDCDD)16 Exercise 113 : (F1E2D3)16 - (C4B5A6)16 = (2D2D2D)16 Exercise 114 : (FF00001)16 - (10000F)16 = (FDFFFF2)16 Exercise 115 : (CAFE)16 - (FACA)16 = (...FFFFD034)16 Exercise 116 : (CDF)16 - (FDC)16 = (...FFFFFD03)16 Exercise 117 : (10001)16 - (20001)16 = (...FFFF0000)16 Exercise 118 : (10000)16 - (FFFE)16 = (2)16 Exercise 119 : (0)16 - (9)16 = (...FFFFFFF7)16 Exercise 120 : (0)16 - (1A)16 = (...FFFFFFE6)16

(A) Exercises 121-126 (Representing binary numbers in bytes)
= ( )2 = ( )16 Exercise 122 : (-1)10 = ( )2 = (FFFF)16 = ( )2 = (FFFFFFFF)16 Exercise 123 : (10)10 = ( )2 = (000A)16 = ( )2 = ( A)16 Exercise 124 : (-10)10 = ( )2 = (FFF6)16 = ( )2 = (FFFFFFF6)16 Exercise 125 : (17)10 = ( )2 = (0011)16 = ( )2 = ( )16 Exercise 126 : (-17)10 = ( )2 = (FFEF)16 = ( )2 = (FFFFFFEF)16

Exercise 127 : (254)10 = ( )2 = (00FE)16 = ( )2 = (000000FE)16 Exercise 128 : (-254)10 = ( )2 = (FF02)16 = ( )2 = (FFFFFF02)16 Exercise 129 : (100000)10 = (impossible to represent in 2 bytes) = ( )2 = (000186A0)16 Exercise 130 : ( )10 = (impossible to represent in 2 bytes) = ( )2 = (FFFE7960)16 Exercise 131 : (32000)10 = ( )2 = (7D00)16 = ( )2 = (00007D00)16 Exercise 132 : (-32000)10 = ( )2 = (8300)16 = ( )2 = (FFFF8300)16

Exercise 133 : (63000)10 = (impossible to represent in 2 bytes) = ( )2 = (FFFFF618)16 Exercise 134 : (-63000)10 = (impossible to represent in 2 bytes) = ( )2 = (FFFF09E8)16 Exercise 135 : (1010)10 = ( )2 = (03F2)16 = ( )2 = (000003F2)16 Exercise 136 : (-1010)10 = ( )2 = (FC0E)16 = ( )2 = (FFFFFC0E)16 Exercise 137 : (4095)10 = ( )2 = (0FFF)16 = ( )2 = (00000FFF)16 Exercise 138 : (-4095)10 = ( )2 = (F001)16 = ( )2 = (FFFFF001)16

= ( )2 = ( )16 Exercise 140 : (-4097)10 = ( )2 = (EFFF)16 = ( )2 = (FFFFEFFF)16

(A) Exercises 141-152 (Representing packed numbers in bytes)
Exercise 141 : (1)10 = [ ] = [ 1C ] Exercise 142 : (-1)10 = [ } = [ 1D ] Exercise 143 : (10)10 = [ ] = [ 010C ] Exercise 144 : (-10)10 = [ ] = [ 10D ] Exercise 145 : (17)10 = [ ] = [ 017C ] Exercise 146 : (-17)10 = [ ] = [ 017D ] Exercise 147 : (254)10 = [ ] = [ 254C ] Exercise 148 : (-254)10 = [ ] = [ 254D ] Exercise 149 : (100000)10 = [ ] = [ C ] Exercise 150 : (100000)10 = [ ] = [ D ] Exercise 151 : (32000)10 = [ ] = [ 32000C ] Exercise 152 : (-32000)10 = [ ] = [ 32000D ]

(A) Exercises 153-160 (Representing packed numbers in bytes)
Exercise 153 : (63000)10 = [ ] = [ 63000C ] Exercise 154 : (-63000)10 = [ ] = [ 63000D ] Exercise 155 : (1010)10 = [ ] = [ 01010C ] Exercise 156 : (-1010)10 = [ ] = [ 01010D ] Exercise 157 : (4095)10 = [ ] = [ 04095C ] Exercise 158 : (-4095)10 = [ ] = [ 04095D ] Exercise 159 : (4097)10 = [ ] = [ 04097C ] Exercise 160 : (-4097)10 = [ ] = [ 04097D ]

(A) Exercises 161-172 (Representing zoned numbers in bytes)
Exercise 161 : (1)10 = [ ] = [ F1 ] Exercise 162 : (-1)10 = [ } = [ D1 ] Exercise 163 : (10)10 = [ ] = [ F1F0 ] Exercise 164 : (-10)10 = [ ] = [ F1D0 ] Exercise 165 : (17)10 = [ ] = [ F1F7 ] Exercise 166 : (-17)10 = [ ] = [ F1D7 ] Exercise 167 : (254)10 = [ ] = [ F2F5F4 ] Exercise 168 : (-254)10 = [ ] = [ F2F5D4 ] Exercise 169 : (100000)10 = [ ] = [ F1F0F0F0F0F0 ] Exercise 170 : ( )10 = [ ] = [ F1F0F0F0F0D0 ] Exercise 171 : (32000)10 = [ ] = [ F3F2F0F0F0 ] Exercise 172 : (-32000)10 = [ ] = [ F3F2F0F0D0 ]

(A) Exercises 173-180 (Representing zoned numbers in bytes)
[ ] = [ F6F3F0F0F0 ] Exercise 174 : (-63000)10 = [ ] = [ F6F3F0F0D0 ] Exercise 175 : (1010)10 = [ ] = [ F1F0F1F0 ] Exercise 176 : (-1010)10 = [ ] = [ F1F0F1D0 ] Exercise 177 : (4095)10 = [ ] = [ F4F0F9F5 ] Exercise 178 : (-4095)10 = [ ] = [ F4F0F9D5 ] Exercise 179 : (4097)10 = [ ] = [ F4F0F9F7 ] Exercise 180 : (-4097)10 = [ ] = [ F4F0F9D7 ]

(A) Exercises 181-194 (Representing character strings in bytes)
Exercise 181 : “17“ = [ F1F7 ] Exercise 182 : “-17“ = [ 60F1F7 ] Exercise 183 : “AF$BD“ = [ C1C66BC2C4 ] Exercise 184 : “-AF4BD“ = [ 60C1C6F4C2C4 ] Exercise 185 : “ALBERTO“ = [ C1D3C2C5D9E3D6 ] Exercise 186 : “15-9“ = [ F1F560F9 ] Exercise 187 : “-4095“ = [ 60F4F0F9F5 ] Exercise 188 : “4095“ = [ F4F0F9F5 ] Exercise 189 : “*&$//“ = [ 5C505B6161 ] Exercise 190 : “12+3“ = [ F1F24EF3 ] Exercise 191 : “I LOVE HER“ = [ C940D3D6E5C540C8C5D9 ] Exercise 192 : “US$ 2,584.73“ = [ E4E25B40F26BF5F8F44BF7F3 ] Exercise 193 : “US$ 1 MILLION“ = [ E4E25B40F140D4C9D3D3C9D6D5 ] Exercise 194 : “PANCHO’S BAR“ = [ D7C1C5C3C8D67DE240C2C1D9 ]

(A) Exercises 195-209 (Representing fields in bytes)
Exercises must be considered as a program starting at address X’ ’, that is, first area (exercise 195) begins at address zero. The DS defined areas must be computed to determine the addresses. Assume the 1st statement of the program is USING *,9. * Address Contents Exercise 195: DC C'123' F1.F2.F3 Exercise 196: DC C'+123' E.F1.F2.F3 Exercise 197: DC C'-123' F1.F2.F3 Exercise 198: DC C'12.3' B F1.F2.4B.F3 Exercise 199: DC C'1AB8' F F1.C1.C2.F8 Exercise 200: DC C'01101' F0.F1.F1.F0.F1 Exercise 201: DC C'A+B=C' C1.4E.C2.7E.C3 Exercise 202: DC CL4'A' D C Exercise 203: DC CL4'ABCDEF' C1.C2.C3.C4 Exercise 204: DC 3CL2'A' C1.40.C1.40.C1.40 Exercise 205: DC 2CL3'A,B' B C1.6B.C2.C1.6B.C2 Exercise 206: DC C'ME&&YOU' D4.C5.50.E8.D6.E4 Exercise 207: DC C'''S MUSIC' D.E2.40.D4.E4.E2.C9.C3 Exercise 208: DC F 7C.7C.D6.C9 Exercise 209: DC CL3'*' C.40.40

* Address Contents Exercise 210: DC 3C'*' C.5C.5C Exercise 211: DC X'123' Exercise 212: DC X'-123' *** error *** Exercise 213: DC X'1AB2C3' B 1A.B2.C3 Exercise 214: DC X'1AB2F4G3' *** error *** Exercise 215: DC XL3'12D' E D Exercise 216: DC XL3'AABBCCDDEE' CC.DD.EE Exercise 217: DC X'1,22,333,4444' Exercise 218: DC XL2'1,22,333' A Exercise 219: DC 2X'1,22,333' Exercise 220: DC 2XL2'1,22' Exercise 221: DC B' ' Exercise 222: DC B'1' Exercise 223: DC BL2'1111' F Exercise 224: DC B'1, ' FF Exercise 225: DC BL2'1, ' FF

* Address Contents Exercise 226: DC 2B'1000' B 08.08 Exercise 227: DC 2BL2'1000' D (align) Exercise 228: DC F'10' A Exercise 229: DC F'+10' A Exercise 230: DC F'-10' C FF.FF.FF.F6 Exercise 230: DC F'-15,+16' FF.FF.FF.F Exercise 231: DC 2F'22' Exercise 232: DC 2F'33,44' A C C Exercise 233: DC FL3'258' B Exercise 234: DC 2FL1'255' B3 FF.FF 00B (align) Exercise 235: DC F'128000' B F4.00 Exercise 236: DC H'10' BC 00.0A Exercise 237: DC H'+10' BE 00.0A Exercise 238: DC H'-10' C0 FF.F6 Exercise 239: DC H'-15,+16' C2 FF.F

* Address Contents Exercise 240: DC 2H'22' C Exercise 241: DC 2H'33,44' CA C C Exercise 242: DC HL3'258' D Exercise 243: DC 2HL1'255' D5 FF.FF 00D7 00 (align) Exercise 244: DC H'128000' D8 F4.00 Exercise 245: DC P'123' DA 12.3C Exercise 246: DC P'+123' DC 12.3C Exercise 247: DC P'-123' DE 12.3D Exercise 248: DC PL4'456' E C Exercise 249: DC PL1'789' E4 9C Exercise 250: DC P'1,-22,333,-4444' 00E5 1C.02.2D.33.3C D Exercise 251: DC PL2'1,-22,333,-4444' 00ED 00.1C.02.2D.33.3C.44.4D Exercise 252: DC 3P'0' F5 0C.0C.0C Exercise 253: DC PL3'0' F C Exercise 254: DC 2P'1,22,333' FB 1C.02.2C.33.3C.1C.02.2C.33.3C

* Address Contents Exercise 255: DC 2PL2'1,22,333' C.02.2C.33.3C 00.1C.02.2C.33.3C Exercise 256: DC Z'123' F1.F2.C3 Exercise 257: DC Z'+123' F1.F2.C3 Exercise 258: DC Z'-123' F1.F2.D3 Exercise 259: DC ZL4'456' A F0.F4.F5.C6 Exercise 260: DC ZL1'789' E C9 Exercise 261: DC Z'1,-22,333,-4444' 011F F1.F2.D2.F3.F3.C3.F4.F4.F4.D4 Exercise 262: DC ZL3'1,-22,333,-4444' 0129 F0.F0.C1.F0.F2.D2.F3.F3.C3 F4.F4.F4.D4 Exercise 263: DC 3Z'0' C0.C0.C0 Exercise 264: DC ZL3'0' F0.F0.F0 Exercise 265: DC 2Z'1,22,333' B C1.F2.C2.F3.F3.C3 C1.F2.C2.F3.F3.C3 Exercise 266: DC 2ZL3'1,22,333' F0.F0.C1.F0.F2.C2.F3.F3.C3 F0.F0.C1.F0.F2.C2.F3.F3.C3

* Address Contents (align) Exercise 267: SIMBZZ DC A(0) C Exercise 268: SIMBAA DC A(127) F Exercise 269: SIMBBB DC A(X'8000') Exercise 270: SIMBCC DC A(B'1111') F Exercise 271: SIMBDD DC A(C'*') C C Exercise 272: SIMBEE DC A(*) Exercise 273: SIMBFF DS CL ??.??.??.??.??.??.??.??.?? ??.??.??.??.??.??.??.?? (align) Exercise 274: SIMBGG DC A(*) Exercise 275: SIMBHH DC A(SIMBGG) C Exercise 276: SIMBII DC A(SIMBAA+12) C Exercise 277: SIMBJJ DC A(SIMBII-SIMBBB) C Exercise 278: SIMBKK DC AL1(*-SIMBKK) Exercise 279: SIMBLL DC 5AL1(*-SIMBLL)

* Endereço Conteúdo Exercise 280: SIMBMM DC AL2(3,5,7) E Exercise 281: SIMBNN DC A(SIMBII+5*2) A A Exercise 282: SIMBOO DC A(SIMBNN+X' ') 01A A4 Exercise 283: SIMBPP DC 4AL2(*-SIMBPP) AC 00.06 Exercise 284: SIMBQQ DC A(SIMBVV) B D8 Exercise 285: SIMBRR DC A(SIMBKK,SIMBJJ) B Exercise 286: SIMBSS DC A(SIMBTT+40) C EC Exercise 287: SIMBTT DC A(SIMBUU,*,80) C D0 C8 Exercise 288: SIMBUU DC 2A(*-SIMBUU) D Exercise 289: SIMBVV DC A(C'AMO') D8 00.C1.D4.D6 Exercise 290: SIMBWW DC A(X'7FFFFFFF') DC 7F.FF.FF.FF

* Address Contents Exercise 291: YY1 DC Y(SIMBWW) E0 01.DC Exercise 292: YY2 DC Y(10) E2 00.0A Exercise 293: YY3 DC Y(L'YY2) E Exercise 294: SS1 DC S(SIMBAA) E Exercise 295: SS2 DC S(SS1) E8 91.E6 Exercise 296: SS3 DC S(10) EA 00.0A Exercise 297: SS4 DC S(*) EC 91.EC 01EE (align) Exercise 298: SS5 DC A(125),F'33',C'*',2H'6,18' 01F D 5C 00 (align) Exercise 299: SS6 DC X'1,1',B'1,1',C'1,1' F1.6B.F1

(A) Exercise 300 (Representing fields in bytes)
* Endereço Conteúdo Exercise 300: LAST DC 256AL1(255+LAST-*) FF.FE.FD.FC.FB.FA.F9.F8.F7.F6.F5.F4.F3.F2.F1.F0 * EF.EE.ED.EC.EB.EA.E9.E8.E7.E6.E5.E4.E3.E2.E1.E0 * DF.DE.DD.DC.DB.DA.D9.D8.D7.D6.D5.D4.D3.D2.D1.D0 * CF.CE.CD.CC.CB.CA.C9.C8.C7.C6.C5.C4.C3.C2.C1.C0 * BF.BE.BD.BC.BB.BA.B9.B8.B7.B6.B5.B4.B3.B2.B1.B0 * AF.AE.AD.AC.AB.AA.A9.A8.A7.A6.A5.A4.A3.A2.A1.A0 * F.9E.9D.9C.9B.9A * F.8E.8D.8C.8B.8A * F.7E.7D.7C.7B.7A * F.6E.6D.6C.6B.6A * A9 5F.5E.5D.5C.5B.5A * B9 4F.4E.4D.4C.4B.4A * C9 3F.3E.3D.3C.3B.3A * D9 2F.2E.2D.2C.2B.2A * E9 1F.1E.1D.1C.1B.1A * F9 0F.0E.0D.0C.0B.0A

(A) Exercise 301 (Decoding instructions)
Exercise 301 : Decode the following set of instructions 1ABB41278CF00A13980F334445E00CB490EC0D00FA CCD ----////////----//////// //////// //////////// Suppose the general registers with the following values: R00= R04= R08= R12=00000C00 R01= R05= R09= R13=00000D00 R02= R06= R10=00000A00 R14=00000E00 R03= R07= R11=00000B00 R15=00000F00

Exercise 301 : Decode the following set of instructions 1ABB41278CF00A13980F334445E00CB490EC0D00FA CCD ----////////----//////// //////// //////////// 1ABB Operation code (machine code) = 1A Mnemonic Assembler code = AR (add register) - Instruction address = X’ ’ - Operands = 1st operand = register 11; 2nd operand = register 11 41278CF0 Operation code (machine code) = 41 Mnemonic Assembler code = LA (load address) - Instruction address = X’ ’ Operands = 1st operand = register 2; 2nd operand : index register = register 7 2nd operand : base register = register 8 2nd operand : displacement = X’CF0’ 2nd operand address = X’ ’+X’ ’+X’CF0’= X’00001BF0’ Continues...

Exercise 301 : Decode the following set of instructions 1ABB41278CF00A13980F334445E00CB490EC0D00FA CCD ----////////----//////// //////// //////////// 0A13 Operation code (machine code) = 0A Mnemonic Assembler code = SVC (supervisor call) - Instruction address = X’ ’ - Operands = supervisor call code = X’13’ = (19)10 = open 980F3344 Operation code (machine code) = 98 Mnemonic Assembler code = LM (load multiple) - Instruction address = X’ ’ Operands = 1st operand = register 0; 3rd operand : register = register 15 (X’F’) 2nd operand : base register = register 3 2nd operand : displacement = X’344’ 2nd operand address = X’ ’+X’344’= X’ ’ Continues...

Exercise 301 : Decode the following set of instructions 1ABB41278CF00A13980F334445E00CB490EC0D00FA CCD ----////////----//////// //////// //////////// 45E00CB4 Operation code (machine code) = 45 Mnemonic Assembler code = BAL (branch and link) - Instruction address = X’ C’ Operands = 1st operand = register 14 (X’E’); nd operand : index register = register 0 2nd operand : base register = register 0; 2nd operand : displacement = X’CB4’ 2nd operand address = X’CB4’= X’00000CB4’ 90EC0D00 Operation code (machine code) = 90 Mnemonic Assembler code = STM (store multiple) - Instruction address = X’ ’ Operands = 1st operand = register 14 (X’E’); 3rd operand : register = register 12 (X’C’) 2nd operand : base register = register 0; 2nd operand : displacement = X’D00’ 2nd operand address = X’D00’= X’00000D00’ Continues...

Exercise 301 : Decode the following set of instructions 1ABB41278CF00A13980F334445E00CB490EC0D00FA CCD ----////////----//////// //////// //////////// FA CC Operation code (machine code) = FA Mnemonic Assembler code = AP (add packed) - Instruction address = X’ ’ 1st operand length = 9 bytes; 1st operand base register = register 3; 1st operand displacement= X’054’; 1st operand address= X’ ’+X’054’ = X’ ’ 2nd operand length = 3 bytes; 2nd operand base register = register 4; 2nd operand displacement = X’8CC’; 2nd operand address= X’ ’+X’8CC’ = X’00000CCC’ D Operation code (machine code) = D2 Mnemonic Assembler code = MVC (move character) - Instruction address = X’ A’ 1st operand length = 131 bytes; 1st operand base register = register 3; 1st operand displacement= X’344’; 1st operand address= X’ ’+X’344’ = X’ ’ 2nd operand length = 131 bytes; 2nd operand base register = register 5; 2nd operand displacement = X566’; 2nd operand address= X’ ’+X’566’ = X’00000A66’

Programming Hints Programming Hints

Interesting things, useful things, awful but used things, etc...
Programming Hints Interesting things, useful things, awful but used things, etc...

Programming Hints Let’s figure out an 11K program, with only one base register PROG START USING *,3 USING specified when Location Counter has zero (assembly time) LR 3,15 Load 1st and only base register (run time) 4K 3K Part of the program that is within the range of the base register R3; any symbol herein declared, which must be converted to Base+Displacement has R3 as base register. This part of rhe program is outside from the range of the base register. Any symbol herein declared, which must be converted to Base+Displacement : ERROR

Programming Hints Let’s figure out an 11K program, with 2 base registers PROG START USING *,3, USING specified when Loc. Counter has zero (assembly time) LR 3, Load 1st base register (run time) LA 7,2048(3) Begin loading 2nd base register (run time) LA 7,2048(3,7) Complete loading 2nd base register (run time) 4K 3K This part of the programt is outside the range of both base registers; any symbol herein declared, which must be converted to Base+Displacement: ERROR Part of the program that is within the range of the base register R3; any symbol herein declared, which must be converted to Base+Displacement has R3 as base register. Part of the program that is within the range of the base register R7; any symbol herein declared, which must be converted to Base+Displacement has R7 as base register.

Programming Hints Let’s figure out an 11K program, with 3 base registers PROG START USING *,3,7, USING specified when Loc. Counter has zero (assembly time) LR 3, Load 1st base register (run time) LA 7,2048(3) Begin loading 2nd base register (run time) LA 7,2048(3,7) Complete loading 2nd base register (run time) LA 6, Begin loading 2nd base register (run time) LA 6,4095(6,7) Complete loading 2nd base register (run time) 4K 3K Part of the program within the range of the base register R6 “Part in excess” for base reg R7 Part of the program within the range of the base register R3 Part of the program within the range of the base register R7

Part of the program within the range of the base register R3
Programming Hints Let’s figure out a 1000K program, with only one base register PROG START USING *,3 USING specified when Location Counter has zero (assembly time) LR 3,15 Load 1st and only base register (run time) 4K 996K Part of the program within the range of the base register R3 This part of the programt is outside the range of the base register; any symbol herein declared, which must be converted to Base+Displacement: ERROR

Part of the program within the range of the base register R3
Programming Hints Let’s figure out a 1000K program, with only one base register 4K Instructions Areas 996K Part of the program within the range of the base register R3 This part of the programt is outside the range of the base register; any symbol herein declared, which must be converted to Base+Displacement: ERROR

Programming Hints Let’s figure out a 1000K program, with only one base register Instrutions Areas (with base reg.) Areas (WITHOUT base register) END (source program finish) Implicit (END) LTORG LITERALS declared by LTORG (without base) Part of the program within the range of the base register R3 This part of the programt is outside the range of the base register; any symbol herein declared, which must be converted to Base+Displacement: ERROR

Programming Hints Let’s figure out a 1000K program, with only one base register Instruction Areas (with base) Areas (WITHOUT base) END (source program finish) Explicitly declared (by programmer) LTORG LITERALS declared by LTORG (with base) Areas still WITH base Part of the program within the range of the base register R3 This part of the programt is outside the range of the base register; any symbol herein declared, which must be converted to Base+Displacement: ERROR

Programming Hints Let’s figure out a 1000K program, with only one base register Instruction Areas (with base) Areas (WITHOUT base) END (source program finish) Explicitly declared (by programmer) LTORG LITERALS declared by LTORG (with base) Areas still WITH base Let’s take a good and detailed look

Are within the range of the base register.
Programming Hints Let’s figure out a 1000K program, with only one base register Instructions Areas Início das áreas “grandes” (supor: 1os 100 bytes de uma área de bytes, por ex. TABXX) TABXX DS 1000CL500 Literals (with base) Restante da área ( bytes) + uma 2ª área grande TABYY + Uma pequena área de 4 bytes (XYZ) LTORG - instructions, - areas before LTORG, - literals and the beginning of the “big” areas (specifically the first 100 bytes from TABXX) Are within the range of the base register.

Programming Hints - 1st 100 bytes of TABXX
Let’s figure out a 1000K program, with only one base register Instruções Áreas LTORG TABXX DS CL500 100 1os bytes de TABXX Demias bytes de TABXX TABYY DS CL 1000CL52 XYZ DS CL4 Literais (com base) - 1st 100 bytes of TABXX Are within the range of the base register - Next bytes of TABXX - All bytes of TABYY - 4 bytes of XYZ Are outside the range of the base register

Programming Hints Let’s figure out a 1000K program, with only one base register Instructions Areas LTORG TABXX DS CL500 1st 100 bytes of TABXX Demias bytes de TABXX TABYY DS CL 1000CL52 XYZ DS CL4 Literals (with base) LA R9,TABXX OK! TABXX (TABXX address ís the address of the leftmost byte of TABXX) is within the range of the base register L R9,=A(TABXX) OK! The literal with TABXX address is within the range of the base register LA R9,TABXX+1 OK! TABXX+1 is na address within the range of the base register L R9,=A(TABXX+1) OK! The literal with TABXX+1 address is within the range of the base register LA R9,TABXX+99 OK! TABXX+99 is an address within the range of the base register L R9,=A(TABXX+99) OK! The literal with TABXX+99 address is within the range of the base register

Programming Hints Let’s figure out a 1000K program, with only one base register Instruções Áreas LTORG TABXX DS CL500 100 1os bytes de TABXX Demias bytes de TABXX TABYY DS CL 1000CL52 XYZ DS CL4 Literais (com base) LA R9,TABXX+100 ERROR!!! TABXX+100 é o 101º. Byte de TABXX, e, portanto, o primeiro a NÃO ser servido pelo registrador base. L R9,=A(TABXX+100) OK! A literal que tem o endereço de TABXX+100 está dentro do alcance do registrador base LA R9,TABYY ERROR!! TABYY é um endereço que NÃO está dentro do alcance do registrador base L R9,=A(TABYY) OK! A literal que tem o endereço de TABYY está dentro do alcance do registrador base LA R9,XYZ ERROR!!! XYZ é um endereço que NÃO está dentro do alcance do registrador base L R9,=A(XYZ) OK! A literal que tem o endereço de XYZ está dentro do alcance do registrador base

Programs with 1 base register Assembler specification
Programming Hints Programs with 1 base register Assembler specification and runtime load

Loading base register with entry point address with LR
Programming Hints Loading base register with entry point address with LR PROG START USING *, LR 3,15 LOAD FIRST AND ONLY BASE REGISTER * REG 3 CONTAINS THE ENTRY POINT ADDRESS * THIS TYPE OF LOAD (WITH LR) IS OFTEN USED IN MVS Loading base register with entry point address with BALR+BCTR+BCTR PROG START USING *, BALR 3,0 LOAD INTO R3 THE ADDRESS JUST AFTER BALR BCTR 3,0 SUBTRACTS BCTR 3,0 SUBTRACTS 1 ONCE MORE * HERE REGISTER 3 IS OK; * IT HAS THE ENTRY POINT ADDRESS

Programs with 2 base registers Assembler specification
Programming Hints Programs with 2 base registers Assembler specification and runtime load

Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address with LA May I do this way? PROG START USING *,3, LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,4096(4) LOAD INTO R4 THE VALUE OF R NO! Why not? Because maximum displacement is 4095 (X’FFF’) !!! Assembly error !

Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address with LA+LA+AR You may do this way... PROG START USING *,3, LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,1 LOAD NUMBER 1 INTO REG LA 4,4095(4) ADD * RESULT = AR 4,3 ADD ENTRY POINT. * R4 CONTENTS = ENTRY POINT * OR ENTRY POINT + X’001000’ * OK ! R3 AND R4 PROPERLY LOADED !

Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address with LA+LA+AR Or that way... PROG START USING *,3, LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,4095 LOAD NUMBER 4095 INTO REG LA 4,1(4) ADD 1 * RESULT = AR 4,3 ADD ENTRY POINT. * R4 CONTENTS = ENTRY POINT * OR ENTRY POINT + X’001000’ * OK ! R3 AND R4 PROPERLY LOADED !

Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address with LA+LA Even this way... PROG START USING *,3, LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,1 LOAD NUMBER 1 INTO REG LA 4,4095(3,4) ADD ENTRY POINT * R4 CONTENTS = ENTRY POINT * OR ENTRY POINT + X’001000’ * OK ! R3 AND R4 PROPERLY LOADED !

Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address with LA+LA You may do like this... PROG START USING *,3, LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4, LOAD NUMBER 1 INTO REG LA 4,2048(3,4) ADD ENTRY POINT * R4 CONTENTS = ENTRY POINT * OR ENTRY POINT + X’001000’ * OK ! R3 AND R4 PROPERLY LOADED !

Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address with LA+LA Or like this... PROG START USING *,3, LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4, LOAD R4 WITH # LA 4,3096(3,4) ADD ENTRY POINT * R4 CONTENTS = ENTRY POINT * OR ENTRY POINT + X’001000’ * OK ! R3 AND R4 PROPERLY LOADED !

Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address with LA Is it correct? PROG START USING *,3, LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS LA 4,PROG+4096 LOAD “DIRECTLY” ENTRY POINT NO! Why not? Because the address PROG isn’t in the range of first base register (R3), so far the only one correctly loaded. Assembly error.

Programming Hints Loading 1st base register with entry point address with LR and 2nd with entry point address with L And about this way? PROG START USING *,3, LR 3,15 LOAD FIRST BASE REGISTER * REG 3 CONTENTS = ENTRY POINT ADDRESS L ,=A(PROG+4096) LOAD “DIRECTLY” ENTRY POINT IT DEPENDS ON ... ! The contents of the literal is being loaded into R4. If the literal is outside the range of the FIRST BASE REGISTER (R3) (THE ONLY ONE CORRECTLY LOADED SO FAR), THEN this is INVALID to prepare the second base register. Assembly error. (case 1) ELSE, this way (using the literal) is VALID. (case 2)

Programming Hints Program = 8k
Loading 1st base register with entry point address with LR and 2nd with entry point address with L CASE 1 : Literal is outside range of the 1st base register (R3), and it is the only one prepared so far. You can’t do this way ! Assembly error. PROG START USING *,3, LR 3, L ,=A(PROG+4096) ( L needs the 2nd base register prepared, but... L prepares the 2nd base register! Execution time error!) END ( literals are declared after END) =A(PROG+4096) Program = 8k This part is served by 1st base register This part is served by 2nd base register

Programming Hints Program = 8k
Loading 1st base register with entry point address with LR and 2nd with entry point address with L CASE 2 : Literal is in the range of the first base register (R3), and it is the only one prepared so far, so you can do this way. PROG START USING *,3, LR 3, L ,=A(PROG+4096) B SKIP LTORG =A(PROG+4096) SKIP ... END (other literals declared here) = =... Program = 8k This part is served by 1st base register Forces the literal to be defined here. This part is served by 2nd base register

THE END

IBM Mainframes Assembler

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