1. Digital Integrated Circuits A Design Perspective
EE141
Digital Integrated Circuits A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
Manufacturing Process
July 30, 2002

2. CMOS Process

3. A Modern CMOS Process
Dual-Well Trench-Isolated CMOS Process

4. Circuit Under Design

5. Its Layout View

6. The Manufacturing Process
For a great tour through the IC manufacturing process and its different steps, check

7. Photo-Lithographic Process
optical
mask
oxidation
photoresist
photoresist coating
removal (ashing)
stepper exposure
Typical operations in a single
photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
spin, rinse, dry
step

8. Patterning of SiO2 Chemical or plasma etch Si-substrate
Hardened resist
SiO 2
(a) Silicon base material
Si-substrate
Photoresist
SiO 2
(d) After development and etching of resist,
chemical or plasma etch of SiO
Si-substrate 2
(b) After oxidation and deposition
Hardened resist
of negative photoresist
SiO 2
Si-substrate
UV-light
Patterned
(e) After etching
optical mask
Exposed resist
SiO 2
Si-substrate
Si-substrate
(f) Final result after removal of resist
(c) Stepper exposure

9. CMOS Process at a Glance
Define active areas
Etch and fill trenches
Implant well regions
Deposit and pattern
polysilicon layer
Implant source and drain
regions and substrate contacts
Create contact and via windows
Deposit and pattern metal layers

10. CMOS Process Walk-Through+
p-epi
(a) Base material: p+ substrate
with p-epi layer p +
p-epi
SiO 2 3 Si N 4
(b) After deposition of gate-oxide and
sacrificial nitride (acts as a
buffer layer) p +
(c) After plasma etch of insulating
trenches using the inverse of
the active area mask

11. CMOS Process Walk-Through
SiO 2
(d) After trench filling, CMP
planarization, and removal of
sacrificial nitride
(e) After n-well and V Tp
adjust implants n
(f) After p-well and V Tn
adjust implants p

12. CMOS Process Walk-Through
(g) After
polysilicon deposition
and etch
poly(silicon)
(h) After n +
source/drain and p
source/drain implants. These
steps also dope the polysilicon.
(i) After deposition of SiO 2
insulator and contact hole etch.
SiO

13. CMOS Process Walk-Through
(j) After deposition and
patterning of first Al layer. Al
(k) After deposition of SiO 2
insulator, etching of via’s,
deposition and patterning of
second layer of Al. Al
SiO

14. Advanced Metallization

15. Advanced Metallization

16. Design Rules

17. 3D Perspective
Polysilicon
Aluminum

18. Design Rules Interface between designer and process engineer
Guidelines for constructing process masks
Unit dimension: Minimum line width
scalable design rules: lambda parameter
absolute dimensions (micron rules)

19. Cross Section & Layout View
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Cross Section & Layout View
gnd
Vout
vdd
thin
Oxide
Vin(Poly)
Polysilicon p+ n+
P substrate
N WELL
Butting
contact
Vin (Polysilicon)
Nimp
Pimp
CMOS 的反相器的橫截面圖與佈局(layout)圖
P WELL

20. Definition For Parameters Of Layout Rules
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Definition For Parameters Of Layout Rules
基本定義 (Definition)
Width
Space
Enclosure
Extension
Overlap
1.請記住這些名稱的定義
2.接下來所介紹的 layout rules 必須熟記在心，
在畫 layout 時務必遵守這些規則。

21. Layout (Design) Rules (I)
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Layout (Design) Rules (I)
1. NW (N well) n+
Metal 1 NW
PW：沒有被NW包圍
的區域都視為
P well
1.a
1.c
1.b
這個 NW的電位
與左邊二個 NW
的電位是不同的，
因為沒有任何的
導線做為連接。
這二個 NW
是同電位的，
因為由 Metal 1
做為導線連接
單位為um

22. Layout (Design) Rules (II)
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Layout (Design) Rules (II)
2. OD (thin oxide)
2.e/2.f
2.a NW n+ p+
Poly PW
2.i
2.j
2.c
2.b
2.g
2.d
2.h
單位為μm

23. Layout (Design) Rules (III)
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Layout (Design) Rules (III)
3. PO (Poly)
n+ / p+
3.g
3.d
3.e
3.a or 3.b PO
3.f
3.c
單位為μm

24. Layout (Design) Rules (IV)
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Layout (Design) Rules (IV)
4. PP(P implantation)
NP(N implantation)
4.c
4.h p+ PO PP
4.a
4.e
4.b OD n+ NP
4.i
4.d
4.g
4.f
單位為μm

25. Layout (Design) Rules (V)
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Layout (Design) Rules (V)
5. CO (contact) n+
5.c
5.k
5.b PO
5.a
5.d
5.j
5.f p+
5.i
5.g
5.e OD
單位為μm

26. Layout (Design) Rules (VI)
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Layout (Design) Rules (VI)
6. M1 (Metal 1)
6.b
6.d
6.c CO M1
6.a
>10um
current
單位為μm

27. Layout (Design) Rules (VII)
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Layout (Design) Rules (VII)
7. VIA (VIA 1)
7.d
7.f
7.a
7.e OD PO
7.g
>10um M1 CO
7.h
7.c
7.b
VIA
7.i
單位為μm

28. Layout (Design) Rules (VIII)
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Layout (Design) Rules (VIII)
8. M2 (Metal 2) M2
8.b
8.d
8.c
VIA
8.a
>10um
current
8.e
單位為μm

29. Layout (Design) Rules (IX)
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Layout (Design) Rules (IX)
9. VIA 2
9.e
9.a M1 M3
9.d
>10um M2
9.c
9.b
VIA2
VIA1
單位為μm

30. Layout (Design) Rules (X)
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Layout (Design) Rules (X)
10. M3 (Metal 3) M3
10.b
10.e
10.c
VIA2
10.a
>10um
current
10.d
單位為μm

31. Cell Butting Rules (A) 左圖為使用 0.6um Single Poly Double
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Cell Butting Rules (A) 原點
(0,0)
左圖為使用 0.6um Single Poly Double
Metal 製程之每一個 Standard Cell 都必
須遵守CMOS 第一種的共同規則例子。
主要的用意是在使任意的兩個 Cell 在
做連接後，都還能符合 Design Rule。
一般高度都是固定的，而寬度以
pitch(2.4um) 為單位，依照 Cell 電晶體
數目的不同，寬度的大小就不同，但都
必須是 pitch 的倍數。
而一般“單位 pitch”就是指兩個 pin中心
點相互間最小的距離。
接地線(VSS/Metal 1) 的左下角為原點須
放在 layout 圖上游標所指的原點(0,0)。
VDD與VSS 須使用 Metal 1 做為連線且
位置及高度都是固定的。(exp.，21.2um)
其餘的數字如 0.9 或 0.9Mini 意思是寬
度至少大於 0.9um，而 1.2Max 意思是
寬度不可以超過 1.2um。

32. CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color
Representation
Yellow
Green
Red
Blue
Magenta
Black
Select (p+,n+)

33. Layers in 0.25 mm CMOS process

34. Intra-Layer Design Rules4
Metal2 3

35. Transistor Layout

36. Vias and Contacts

37. Select Layer

38. CMOS Inverter Layout

39. Layout Editor

40. Design Rule Checker
poly_not_fet to all_diff minimum spacing = 0.14 um.

41. Sticks Diagram 1 V 3 In Out GND Dimensionless layout entities
Stick diagram of inverter
Dimensionless layout entities
Only topology is important
Final layout generated by “compaction” program

42. Packaging

43. Packaging Requirements
Electrical: Low parasitics
Mechanical: Reliable and robust
Thermal: Efficient heat removal
Economical: Cheap

44. Bonding Techniques

45. Tape-Automated Bonding (TAB)

46. Flip-Chip Bonding

47. Package-to-Board Interconnect

48. Package Types

49. Package Parameters

50. Multi-Chip Modules