1. Scaling

2. Contents Wafer size scaling Chip size scaling Wafer thickness scaling
Projection lithography
Etch scaling (from wet to dry)
Selectivity scaling (CMOS gate)
Gate oxide scaling
Junction depth scaling
Thermal budget scaling (RTA)
Film thickness scaling (MLM, constant AR
Fab size scaling
Fab cost scalingLinewidth scaling

3. Wafer thickness scaling
Wafer size scaling
525 µm
625 µm
725 µm
775 µm
?? 925 µm
Wafer thickness scaling

4. Wafer size and demand
Doering, R. & Y. Nishi: Limits of integrated circuit manufacturing, Proc. IEEE Vol. 89 (2001) p. 375

5. New prediction

7. Useful chips & edge exclusion

8. Chip scaling and wafer scaling

9. Chip size vs. Yield Good Money chips USD 255 1020 98 1176 32 1696
6 1632
4 1668
EE141 © Digital Integrated Circuits 2nd Introduction 1 Digital Integrated Circuits A Design Perspective Introduction Jan M. Rabaey Anantha Chandrakasan.

10. Optical projection lithography
Sources of radiation
(UV 365 nm-436 nm,
DUV 193 nm-248 nm,
EUV, X-rays, electrons, ions)
Optical system I
(lenses, mirrors)
Mask (pattern)
Optical system II
Numerical aperture NA=sin 
Imaging medium (resist)
Wafer (with patterns)
Wafer stage
(alignment mechanism)

11. Reduction factor, often 5X
Mask 1 µm minimum linewidth
5X optical reduction 
0.2 µm on wafer

12. Projection litho performance

13. Table 10.1: Linewidth scaling of CMOS
Wavelength Aperture k factor Linewidth DoF
=436 nm NA=0.38 k1= µm 1.5µm
=365 nm NA=0.48 k1= µm 0.8 µm
=248 nm NA=0.60 k1= µm 0.35 µm
=248 nm NA=0.65 k1= µm 0.30 µm
Because depth of focus (DoF) gets smaller, CMP planarization becomes more important all the time.

14. Projection lithography scaling
Lin, MEMS2010

15. Photomask cost scaling
Min LW Cost
3 µm 300 euros
1 µm 500 euros
1 µm euros, quality checked
Mask LW Wafer LW Cost
1 µm µm euros
0.5 µm 0.1 µm euros
200 nm 40 nm euros
100 nm 20 nm euros
1X litho
5X reduction litho

16. Refresher: etch profiles
Wet etching  isotropic profile
Plasma etching  anisotropic profile

17. Wet etched profile: 1 µm thick film

18. Plasma etched profile: 1 µm film

19. Wet etched profile: 200 nm film

20. Plasma etched profile: 200 nm film

21. Etch back Conformal deposition
Anisotropic etch 200 nm/min for 1 minute.
400 nm
200 nm

22. Etch time, end point and overetch
100 nm
300 nm
100 % conformal deposition.
200 nm
Etch rate 100 nm/min.
Anisotropic etch.
Etch time 1 min.
 spacers formed
Etch time 3 minutes; i.e. 2 minutes overetch (200%). Clears spacers.

23. CMOS gate etch selectivity
CMOS linewidth: 5 µm
Polysilicon gate: 500 nm thick
Gate oxide thickness (LW/50) = 100 nm
Etch selectivity poly:oxide = 10:1
Overetch = 50 %
Oxide loss = nm
Oxide loss = % of original thickness
CMOS linewidth: 1 µm
Polysilicon gate: 300 nm thick
Gate oxide thickness (LW/50) = 20 nm
Overetch = 50 %
Oxide loss = same % loss as in above,
Calculate etch selectivity poly:oxide needed to achieve this !

25. CMOS linewidth: 5 µm
Polysilicon gate: 500 nm thick
Gate oxide thickness (LW/50) = 100 nm
Etch selectivity poly:oxide = 10:1
Presume: 500 nm/min poly  50 nm/min oxide
Overetch = 50 %  0.5 min oxide etched 
Oxide loss = 25 nm
Oxide loss = 25% of original thickness
CMOS linewidth: 1 µm
Polysilicon gate: 300 nm thick
Gate oxide thickness (LW/50) = 20 nm
Overetch = 50 %
Oxide loss = same % loss as in above,
Calculate etch selectivity poly:oxide needed! Presume 300 nm/min  50% oe is 30 secs
5 nm loss allowed  10 nm/min oxide rate
 30:1 selectivity needed

26. Gate oxide scaling Rule of thumb (valid for 1970-2000):
linewith/50 = gate oxide thickness
5 µm  100 nm
1 µm  20 nm
0.5 µm  10 nm
0.2 µm  4 nm
0.1 µm  2 nm HERE WE RUN INTO PROBLEMS…

27. High-k dielectrics ZrO2 HfO2 High dielectric constants of
ca. 20 (vs. 4 for SiO2)
Deposited by ALD.
SiO2 formed in the first steps of ALD, because H2O used as a precursor.

28. Equivalent oxide thickness
Example:
6 nm ZrO2: EOT = (4/23)*6 nm + 0 nm = 1 nm
1 nm SiO2 + 6 nm ZrO2: EOT = (4/23)*6 nm + 1 nm = 2 nm

29. Junction depth scaling
Thermal diffusion vs. ion implantation
300 nm deep  300 nm sideways
300 nm deep  100 nm sideways

30. CMOS S/D scaling 5 µm gate length 0.5 µm S/D diffusion depth
 4 µm Leffective
1.5 µm gate length
0.5 µm S/D diffusion depth
 0.5 µm Leffective

31. S/D scaling trick #1: implant energy down
e.g. 50 keV B+
e.g. 10 keV B+ or 50 keV BF2+
Sideways spreading is 1/3 of vertical depth, for both.

32. S/D scaling trick #2: spacers
Anisotropic etching of a conformal film
Ion implantation 
Leff = Lithographic !

33. Spacers and LDDs extended
Energy X
Energy scaled down  narrow spacer enough.

34. Thermal budget scaling & RTA
Ion implantation always requires a high temperature annealing step to get rid of implant damage.
I/I damage anneal time is short compared with diffusion because only local movement of atoms needed, e.g. to move an interstitial atom into a lattice site.
As S/D junction needs to be shallower, anneal thermal budget (T,t) needs to be scaled down.
E.g. 1100oC & 30 secs  1100oC & 15 secs  1050oC & 15 secs but then 1200oC & 1 s  1200oC & 0.1 sec

35. Sheet resistance scaling
Rs  /T
I/I dose constant 1015 cm-2
Use simple box approximation in transforming dose to concentration
S/D 1 µm deep  1019 cm-3  Rs = 0.01 Ω-cm/10-4 cm = 100 Ω
S/D 0.1 µm  1020 cm-3  Ω-cm/10-5 cm = 100 Ω

36. Aspect ratio scaling
Actually, aspect ratio (height:width) does NOT scale; it has remained more or less 1:1 for decades.

37. 8-level IC metallization

38. Fab cost scaling 1957 0.2 M$ 1967 2.5 M$ 1977 10 M$ 1987 100 M$
2017 ?

39. Fab size scaling Year Wafer size LW WPM* 1970 3” 10 µm 1000
mm 2 µm 5000
mm 0.8 µm 10000
mm µm 20000
mm 32 nm 50000
mm 11 nm 70000
* Wafer starts per month

40. Wafer specifications for CMOS
Wafer size mm
Thickness µm
TTV µm
Warp µm
Flatness <3 <2 < µm
Oxygen pmma
OISF <10 none none cm-2
Particles #/wafer
Particle size µm
Metal impurities * atoms/cm2