1.
Dear Colleagues, In agreement with the CMS Upgrade Managers, the Tracker will hold a review of R&D activities related to outer tracker modules on March This includes of course Front-End electronics (ASICs, Hybrids, Opto, System, etc.). The review is meant to provide a complete and exhaustive view of the ongoing R&D, hence superseding all the initial R&D proposals. Presentations are invited on the following topics:
a. electronics for 2S modules: i. System ii. CBC iii. Concentrator iv. Hybrid v. Assembly and prototyping vi. Roadmap
b. electronics for PS modules: i. System ii. MPA iii. SSA iv. Hybrid v. Assembly and prototyping vi. Roadmap
c. electronics for VPS modules: i. System ii. VICTR iii. Interposer iv. Stacked assembly v. Prototyping vi. Roadmap
d. Electronic services: i. Power ii. Opto Groups pursuing active R&D in these areas for the CMS tracker are invited to contact me before Friday 8 March to organize their presentations. Best regards, Francois
R. Lipton

2. Proposed Schedule Via Last Module (Ron) Flex option R&D Plans
Introduction (Marvin or Marcello)
design principles and long barrel concept
Rod-based geometry
Z information-passing
Simulated performance
Off-detector consequences
3DIC Program (Gregory)
VICTR status and testing
3D status
10x10 Module R&D (Ron)
Interposer
Bonding
Mass, planarity
Arlon results
Large area issues
Yield and active edge R&D
Via Last Module (Ron)
Flex option
R&D Plans
FEA (Marvin)
VICTR II chip (Marvin)
Design principles
Data flow
Z data transfer
Pipeline design
Differences from MPA
Plans
Large area and via last modules
Active edge
Design collaboration with CERN (Ron + Gregory)
R. Lipton

3. Schedule Draft talks by next Wednesday
Discussion during the Thursday meeting.
R. Lipton

4. Interconnect and ASIC Technologies for Tracking Triggers at LHC
1033
1035
1032 cm-2 s-1
1034
The Problem
At HL-LHC intense beams will collide every 25 ns
~ interactions per collision
Interesting events are rare – we can record 100k/40Mhz
The goal of a track based trigger is to identify interesting events by the pattern of hits in the tracking systems.
->Send only high momentum (low curvature) tracks to analysis
9/26/2012
Ronald Lipton

5. Long Barrel Design Principles: Tracker designed for L1 Track/Trigger
Hierarchical design with local track finding
Sensor pitch
Long strip sensor for r-phi measurement
Strip length set by occupancy and interposer via density to about 1 cm
Short strip sensor for r-phi, r-z measurement
Strip length set by z vertex measurement and tracklet extrapolation
100 micron Strip pitch set by momentum resolution and tracklet extrapolation
R. Lipton

6. Geometry
Layers are organized into rods which fully contain all 2 GeV tracklets
Layer pair separation ~4 cm
Lever arm for tracklet extrapolation and momentum determination
Allows for sufficient rod overlap to fully contain all 2 GeV tracks
A box beam support structure of sufficient rigidity can be implemented in the long barrel with 4 cm flange spacing
Beam can contain power bussing, DC-DC converters, GBT, optical cables
Beam also acts as a ground plane and shield
Long Barrel design
Allows for uniform implementation of modules
Consistent, simple track finding
R. Lipton

7. Simulation Text Circle area proportional to false stub probability
Full GEANT simulation of long barrel calculated for 200 pile-up events per bunch crossing with 50ns bunch spacing
Crucial issues for design:
Turn-on curves
Accuracy of tracklet extrapolation to other layers
Stub occupancy
Stubs/window - example L1->L9 .3 cm2 x .07/40 stubs/cm2 xing = 5x10-4
Inner
layer
proj.
Mid
layer
proj.
Text
Outer
layer
proj.
.35 MHz/cm2
.18 MHz/cm2
.07 MHz/cm2
N. Pozzobon, E. Salvati, A. Ryd

8. Data Rates Rates fall rapidly with Z and radius
Stubs provide ~ factor of 20 data reduction wrt tracks, 40 wrt hits
Simulations indicate that 4 stubs/module/xing is sufficient for non tt events
Tracks
Hit
strips
Clusters
Stubs
Tracklets
Central
Middle
Edge
Stubs/module per crossing Layer 1

9. Track Trigger Geometry
Correlate hits from sensors separated by ~1 mm
Displacement of hits between top and bottom sensors determines momentum
Compare hit locations locally to minimize data flow
Pixelate bottom sensor to provide information in Z dimension
3D electronics technology allows direct access to top and bottom sensors.
The design must be simple and inexpensive enough to build 100’s of square meters of modules.
Two 3D-based designs under consideration interposer-based and via-last
9/26/2012
Ronald Lipton

10. 1 x 6 micron through silicon vias Oxide bonded short strip sensors
Interposer Module
Via-Last Module
(FNAL design)
1 x 6 micron through silicon vias
Oxide bonded short strip sensors
Analog signals through PCB interposer
1 cm long strips
50 x 250 micron through silicon vias
Bump bonded short strip sensors
Analog signals through flex jumper
2.5 cm long strips (set by chip size)
TSVs
250m
Top detector
Analog
signals
Short (0.125 cm) strips
Short (1.25 mm) strips
Long (1 cm) strips
Analog
signals
Flex Jumper
Interposer
Carbon Foam Spacer
20m
Amp/disc cluster
and stub formation
TSVs
Short (1.25 mm) strips
Long (2.5 cm) strips

11. a Via-Last Based Module Pixel/strip ROIC Foam spacer TSV Long strip
sensor
Short strip
sensor
Flex
jumper
R. Lipton

12. VICTR 3D Chip
VICTR 3D chips (0.13 micron, two tier) received last June and tested without sensors.
One wafer each with copper and oxide inter-tier bonds
All basic functions work
Need to lower voltage to get phi tier shift register to work reliably – explains some earlier odd results
First 4 pairs of the second set of wafers have now been bonded and topside processing will be performed in next ~two months. This should give us full wafers for bottom (short strip) sensor interconnect.
The sensor integration process will be reviewed in early March at Ziptronix. We expect that work will take 2 months.

13. Interposer-based Demonstration Stack
We have been working on bonding of the interposer and long strip sensor to the VICTR 3D chip.
Gold studs or solder bumps placed on individual chips
Initial attempt with gold studs to silicon interposer did not result in good adhesion
Gold studded VICR was bonded to a sensor with a PCB interposer – this worked.
Initial test showed expected noise increase, but the chip may now be damaged – loss of daisy chain connection
R. Lipton

14. Active Edge/3D Integration
Future detectors will require large areas of pixelated sensors
The natural size of these devices is set by the IC reticule - ~2x3 cm.
Larger area devices are currently limited by:
Access to interconnects (dead area)
Bump bond cost and pitch
Placement yield of ~25 ICs on a 10 x 10 cm2 sensor
Stitching can help, but yield issues limit sizes of stitched arrays.
3D technologies being developed by the IC industry promise low cost, very fine pitch (4 micron) wafer-scale bonding technologies with all contacts through the backside, eliminating area lost to bond pads
R. Lipton

15. Active Edges
Both Particle Physics and x-ray imaging typically require thick (>200mm) silicon sensors
These sensors must provide for dead regions near the edges to limit leakage current caused by cut damage
The “active edge” process developed for 3D sensors avoids this by using DRIE and subsequent edge dopant insertion to make the edges active electrodes.
These can be butted to form active tiles
VTT Active Edge sensor
R. Lipton

16. Current Project (FNAL/Cornell/SLAC)
Aim – Develop an affordable process for producing active tiles to decouple IC device and placement yields for large area modules
Combine 3D wafer bonding with active edges to form buttable tiles
Based on full wafer oxide (DBI) bonding of sensors to ROICs
Faster and potentially cheaper
Resulting stack must be singulated and handle wafer removed
Demonstration project uses active edge sensors from VTT dummy IC wafers from Cornell and singulation at SLAC/Stanford
Full stack before singulation
R. Lipton l

17. Technology Components
Ziptronix DBI bonding array
From Tezzaron 3D wafer run
Chip-to-wafer oxide bond demonstration
4 micron pitch
Stack after thinning and singulation
200m
R. Lipton

18. Active Edge Active edge wafers received from VTT
Test structure and initial strip testing
Top wafer being processed at Cornell – they have had problems with tungsten and we may switch to aluminum
We will use the patterned wafer for a pilot singulation test with SLAC
We will review the layouts and integration process with Ziptronix in March.
R. Lipton
Test Structure results

19. Infieri might want to explore this
Alternatives
Current oxide bonded wafer-wafer process
Wafer-wafer bonding will require 200 or 300 mm sensor wafers to match ROICS
These wafers would have to have active edge SOI processing
Could be expensive
Active edge waver topology makes oxide bonding difficult
Cu stud bonded chip-wafer process
Sensor tiles bonded to ROIC wafers
Avoids large sensor wafers but more bonding
3D integration of the resulting stack either with via last or imbedded TSV processes
Standard dicing
Infieri might want to explore this
R. Lipton

20. Expose TSV or insert via last vias
Process Cartoon
Solder or
Cu stud
Sensor
ROIC
TSV
Bond sensor tiles
Expose TSV or insert via last vias
Pattern bottom
singlulate
R. Lipton

21. R&D Issues Bonding technology (oxide, cu stud, solder) Planarity
Backside processing – via last, imbedded TSV …
Singulation
Active edge processing
8” SOI sensor wafers
Alternatives to DRIE (cleaving/ALD)
R. Lipton