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Tomasulo algorithm 윤진훈.

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1 Tomasulo algorithm 윤진훈

2 Tomasulo algorithm ? 동적 스케쥴링
RAW 해저드 : 브로드캐스트를 활용, 오퍼랜드를 사용가능 하자마자 실행 WAR, WAW 해저드 : 레지스터 리네이밍 기법 사용 Reservation station : 이슈를 기다리는 명령들의 오퍼랜드를 저장하는 버퍼 Op : 연산 Qj, Qk : 예약 스테이션 Vj, Vk : 소스 오퍼랜드의 값 Busy : 사용 가능 여부 A : 메모리 주소 계산에 필요한 정보 저장 명령어 진행 과정 Issue Execute Write result

3 Example Source 실행 사이클 우선순위 L/S 1사이클 ADD, SUB 2사이클 MUL 4사이클 DIV 10사이클
Bypass 1사이클 Broadcast 1사이클 우선순위 LOAD → STORE → DIV → MUL → SUB → ADD

4 Example Cycle 0 Instruction status IS EX WR ADD F0, F1, F2 LOAD
F1, [R1] MUL F3, F5, F0 SUB F6, F3, F10 DIV F8, F9, F2 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 N LD 0 ALU 1 ST 0 MUL 0 MUL 1 Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10

5 Example Cycle 1 Instruction status IS EX WR ADD F0, F1, F2 1 LOAD
F1, [R1] MUL F3, F5, F0 SUB F6, F3, F10 DIV F8, F9, F2 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y R(F1) R(F2) LD 0 N ALU 1 ST 0 MUL 0 MUL 1 Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 명령어 큐에서 명령어를 꺼낸다. RS 상태 확인 후 Op를 입력한다. 레지스터로부터 Operand를 읽어온다.

6 Example Cycle 2 Instruction status IS EX WR ADD F0, F1, F2 1 2 LOAD
F1, [R1] MUL F3, F5, F0 SUB F6, F3, F10 DIV F8, F9, F2 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y R(F1) R(F2) LD 0 [R1] ALU 1 N ST 0 MUL 0 MUL 1 Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 Operand가 사용가능 하므로 실행됨

7 Example Cycle 3 Instruction status IS EX WR ADD F0, F1, F2 1 2 LOAD
F1, [R1] 3 MUL F3, F5, F0 SUB F6, F3, F10 DIV F8, F9, F2 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y R(F1) R(F2) LD 0 [R1] ALU 1 N ST 0 MUL 0 R(F5) MUL 1 Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F1은 WAR 해저드이다. 그러나 ADD에서 오퍼랜드를 이미 복사해놨기 때문에 상관없다. ADD의 결과값을 받아야 하는 RAW 해저드

8 Example Cycle 4 Instruction status IS EX WR ADD F0, F1, F2 1 2 4 LOAD
F1, [R1] 3 MUL F3, F5, F0 SUB F6, F3, F10 DIV F8, F9, F2 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y R(F1) R(F2) LD 0 N ALU 1 R(F10) MUL 0 ST 0 R(F5) MUL 1 Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 M(2) 우선순위에 따라 LOAD 먼저 처리 ADD에서 연산이 끝나지 않았음에도 LOAD의 결과가 나온 것에 주목 실행 못함 레지스터에 결과값이 반영됨

9 Example Cycle 5 Instruction status IS EX WR ADD F0, F1, F2 1 2 5 LOAD
F1, [R1] 3 4 MUL F3, F5, F0 SUB F6, F3, F10 DIV F8, F9, F2 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 N LD 0 ALU 1 Y R(F10) MUL 0 ST 0 R(F5) MUL 1 R(F9) R(F2) Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 M(1) M(2) 레지스터에 결과값이 반영됨

10 Example Cycle 6 Instruction status IS EX WR ADD F0, F1, F2 1 2 5 LOAD
F1, [R1] 3 4 MUL F3, F5, F0 SUB F6, F3, F10 DIV F8, F9, F2 6 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y R(F9) ALU 1 LD 0 N R(F10) MUL 0 ST 0 R(F5) M(1) MUL 1 R(F2) Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 M(2) Broadcasting에 1사이클

11 Example Cycle 7 Instruction status IS EX WR ADD F0, F1, F2 1 2 5 LOAD
F1, [R1] 3 4 MUL F3, F5, F0 7 SUB F6, F3, F10 DIV F8, F9, F2 6 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y R(F9) ALU 1 LD 0 N R(F10) MUL 0 ST 0 [R1] R(F5) M(1) MUL 1 R(F2) Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 M(2) Bypass에 1사이클

12 Example Cycle 8 Instruction status IS EX WR ADD F0, F1, F2 1 2 5 LOAD
F1, [R1] 3 4 MUL F3, F5, F0 7 SUB F6, F3, F10 DIV F8, F9, F2 6 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y R(F9) ALU 1 LD 0 N R(F10) MUL 0 ST 0 [R1] R(F5) M(1) MUL 1 R(F2) Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 8 M(2) RS가 꽉 차서 이슈 불가능

13 Example Cycle 9 Instruction status IS EX WR ADD F0, F1, F2 1 2 5 LOAD
F1, [R1] 3 4 MUL F3, F5, F0 7 SUB F6, F3, F10 DIV F8, F9, F2 6 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y R(F9) ALU 1 LD 0 N R(F10) MUL 0 ST 0 [R1] R(F5) M(1) MUL 1 R(F2) Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 9 M(2)

14 Example Cycle 10 Instruction status IS EX WR ADD F0, F1, F2 1 2 5 LOAD
F1, [R1] 3 4 MUL F3, F5, F0 7 SUB F6, F3, F10 DIV F8, F9, F2 6 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y R(F9) ALU 1 LD 0 N R(F10) MUL 0 ST 0 [R1] R(F5) M(1) MUL 1 R(F2) Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 10 M(2)

15 Example Cycle 11 Instruction status IS EX WR ADD F0, F1, F2 1 2 5 LOAD
F1, [R1] 3 4 MUL F3, F5, F0 7 11 SUB F6, F3, F10 DIV F8, F9, F2 6 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y R(F9) ALU 1 LD 0 N R(F10) MUL 0 ST 0 [R1] MUL 1 R(F2) Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 M(1) M(2) M(3)

16 Example Cycle 12 Instruction status IS EX WR ADD F0, F1, F2 1 2 5 LOAD
F1, [R1] 3 4 MUL F3, F5, F0 7 11 SUB F6, F3, F10 DIV F8, F9, F2 6 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y R(F9) ALU 1 LD 0 N R(F10) M(3) ST 0 [R1] MUL 0 MUL 1 R(F2) Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 12 M(1) M(2) Broadcasting에 1사이클

17 Example Cycle 13 Instruction status IS EX WR ADD F0, F1, F2 1 2 5 LOAD
F1, [R1] 3 4 MUL F3, F5, F0 7 11 SUB F6, F3, F10 13 DIV F8, F9, F2 6 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y R(F9) ALU 1 LD 0 N M(3) R(F10) ST 0 [R1] MUL 0 MUL 1 R(F2) Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 M(1) M(2) Bypass에 1사이클

18 Example Cycle 14 Instruction status IS EX WR ADD F0, F1, F2 1 2 5 LOAD
F1, [R1] 3 4 MUL F3, F5, F0 7 11 SUB F6, F3, F10 13 DIV F8, F9, F2 6 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y R(F9) ALU 1 LD 0 N M(3) R(F10) ST 0 [R1] MUL 0 MUL 1 R(F2) Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 14 M(1) M(2)

19 Example Cycle 15 Instruction status IS EX WR ADD F0, F1, F2 1 2 5 LOAD
F1, [R1] 3 4 MUL F3, F5, F0 7 11 SUB F6, F3, F10 13 15 DIV F8, F9, F2 6 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y R(F9) ALU 1 LD 0 N R(F3) R(F4) ST 0 [R1] MUL 0 MUL 1 R(F2) Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 M(1) M(2) M(3) M(4)

20 Example Cycle 16 Instruction status IS EX WR ADD F0, F1, F2 1 2 5 LOAD
F1, [R1] 3 4 MUL F3, F5, F0 7 11 SUB F6, F3, F10 13 15 DIV F8, F9, F2 6 16 F2, F6, F9 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y R(F9) M(4) LD 0 N ALU 1 R(F3) R(F4) ST 0 [R1] MUL 0 MUL 1 Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 M(1) M(2) M(3) M(5) SUB의 Broadcasting에 1사이클 DIV 연산 결과 반영

21 Example Cycle 17 Instruction status IS EX WR ADD F0, F1, F2 1 2 5 LOAD
F1, [R1] 3 4 MUL F3, F5, F0 7 11 SUB F6, F3, F10 13 15 DIV F8, F9, F2 6 16 F2, F6, F9 17 STORE F8, [R1] F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y M(4) R(F9) LD 0 N ALU 1 R(F3) R(F4) ST 0 [R1] MUL 0 MUL 1 Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 M(1) M(2) M(3) M(5) Bypass에 1사이클 DIV의 Broadcasting에 1사이클

22 Example Cycle 18 Instruction status IS EX WR ADD F0, F1, F2 1 2 5 LOAD
F1, [R1] 3 4 MUL F3, F5, F0 7 11 SUB F6, F3, F10 13 15 DIV F8, F9, F2 6 16 F2, F6, F9 17 STORE F8, [R1] 18 F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y M(4) R(F9) LD 0 N ALU 1 ST 0 [R1] MUL 0 MUL 1 Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 M(1) M(8) M(3) M(5)

23 Example Cycle 19 Instruction status IS EX WR ADD F0, F1, F2 1 2 5 LOAD
F1, [R1] 3 4 MUL F3, F5, F0 7 11 SUB F6, F3, F10 13 15 DIV F8, F9, F2 6 16 F2, F6, F9 17 19 STORE F8, [R1] 18 F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 Y M(4) R(F9) LD 0 N ALU 1 ST 0 MUL 0 MUL 1 Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 M(1) M(8) M(3) M(5) 우선순위에 따라 STORE 먼저 처리

24 Example Cycle 20 Instruction status IS EX WR ADD F0, F1, F2 1 2 5 LOAD
F1, [R1] 3 4 MUL F3, F5, F0 7 11 SUB F6, F3, F10 13 15 DIV F8, F9, F2 6 16 F2, F6, F9 17 20 STORE F8, [R1] 18 19 F1, F3, F4 Reservation Station Time Name Busy Op Vj Vk Qj Qk Address ALU 0 N LD 0 ALU 1 ST 0 MUL 0 MUL 1 Register result status clock F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 M(1) M(8) M(6) M(3) M(4) M(5)

25 Tomasulo algorithm Broadcast Out of order Instruction Queue
FP Register 8 7 Write Result ADD F0, F1, F2 1 FIFO Read Value 3 Value F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 LOAD F1, [R1] LOAD F1, [R1] MUL F3, F5, F0 Issue ADD F0, F1, F2 SUB F6, F3, F10 MUL F3, F5, F0 DIV F8, F9, F2 Opcode 2 SUB F6, F3, F10 ADD F2, F6, F9 DIV F8, F9, F2 STORE F8, [R1] ADD F1, F3, F4 ADD F1, F3, F4 STORE F8, [R1] Operand 4 ADD F2, F6, F9 Broadcast Reservation Station 7 RS ALU 0 RS ALU 1 RS MUL 0 RS MUL 1 RS LD 0 RS ST 0 Execute 5 Execute ALU 0 ALU 1 MUL 0 MUL 1 LD 0 ST 0 6 Write CDB Common data bus

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