1. FONT5 digital feedback boards
Xilinx Virtex5 FPGA
Clocked at 357 MHz
9 ADC channels
Texas instruments ADS5474
Sampling rate of 357 MHz
14 (13) bit resolution
Will focus here mainly on 9-channel DAQ
Envisage an incremental firmware design and implementation
Can’t feedback until we can measure beam reliably
Ben Constance
FONT Meeting 10th July 2009 1

2. FONT5 firmware - Introduction
Difficult to know how much detail to go into here
Settled on system-type diagrams
Some connections, e.g. handshaking, left out for clarity
More of a logical layout than a technical design
Design is modular
Simplicity of design and simulation
Lots of logic duplication across the 9 channels
Recycle as much of FONT4 firmware as possible
Colour-coding in block diagrams
Green: module exists and can be reused without modification
Yellow: some trivial modification necessary
Red: new logic, or major modification required
Blue: Virtex5 primitive
Ben Constance
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3. FONT5 firmware - Layout
The following modules are described over the next slides:
357 MHz clock input
RS232 control
Timing, trigger and clock synchronisation
ADC sampling control
Ben Constance
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4. 357 MHz clock input
The 357 MHz clock is brought into the FPGA as in FONT4 firmware
PLL configured as a jitter filter
200 MHz reference generated by DCM for IODELAY control
‘Master’ input delay set during laboratory calibration (more later)
Ben Constance
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5. RS232 control
Ben Constance
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6. Timing, clock and trigger synchronisation (1)
Ben Constance
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7. Timing, clock and trigger synchronisation (2)
Ben Constance
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8. ADC sampling control (1)
Nominal data delay set with master delay during lab. Calibration
sample_scan and inc used to vary ADC sampling point
Module will automagically correct for temperature etc. variations in FPGA-ADC signal propagation
Ben Constance
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9. ADC sampling control (2)
Ben Constance
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10. ADC sampling control (3)
Alignment monitor module
ADC data ready signal transitions when data change (polarity random)
Take N sets of 3 samples of data ready with the logic 357 MHz on both rising and falling edge
Count number of sample 1, 2 & 3 that are set
Expect all of sample 1 set and all of sample 3 unset, or vice versa
Expect a fraction of sample 2 set if sampling correctly
If fraction of sample 2 set above threshold, and most are equal to sample 1, reduce delay on data. If most are equal to sample 3, increase delay
Ben Constance
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11. Other DAQ considerations
So far assumed that entire ring clock’s worth of data will be returned. However:
357MHz = 166 samples/channel
2 bytes per sample = 3,009 bytes/pulse
10 bits per byte = 30,090 bits/pulse
So just for data would need 45,070 baud. This is beyond RS232 specs.
Either compress data (run-length), or return just part of the ring clock cycle.
Ben Constance
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12. Action plan Plan to begin simulations of ‘red’ modules
It will be possible to perform some basic tests with the FONT4 boards
Once all modules fully tested, will begin implementation of a ‘DAQ’ firmware for the Virtex5
When the FONT5 board becomes available, the delays will be calibrated in lab and ADC response tested
The board will then be ready for commissioning and calibration/resolution studies at ATF
The feedback path will be implemented once DAQ fully tested
This will remain the same as for FONT4 (yellow module), i.e. feedback LUT, multiplier and delay loop but duplicated for P2 – K1 and P3 – K2
Ben Constance
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